High voltage undervoltage detection circuit and high voltage circuit and chip thereof

Abstract

The present disclosure provides a high-voltage undervoltage detection circuit and its high-voltage circuit and chip. The high-voltage undervoltage detection circuit includes a voltage-dividing sampling circuit, a pull-up current control circuit, a pull-down current control circuit, a voltage comparison circuit and an output circuit connected with electrical signals; the voltage-dividing sampling circuit is used to access the high-voltage signal to be detected, and generate a sampling voltage signal under the drive of the high-voltage signal to be detected, and transmit the sampling voltage signal to the pull-up current control circuit; the pull-up current control circuit is used to generate a pull-up current under the drive of the sampling voltage signal and the preset high-voltage signal and transmit it to the pull-down current control circuit; the pull-down current control circuit is used to form a detection voltage signal under the drive of the pull-up current and transmit it to the voltage comparison circuit; the voltage comparison circuit is used to drive the output circuit to output a high-voltage undervoltage lockout signal in response to the detection voltage signal being less than the rated voltage signal. The present disclosure has no power consumption on the power supply voltage during the standby undervoltage detection stage of the high-voltage circuit, and the standby current is smaller.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit design, and in particular to a high-voltage undervoltage detection circuit and a high-voltage circuit and chip thereof. Background Art

[0002] Nor flash memory (a non-volatile storage technology) chips are used as code storage in various electronic devices. In order to meet the application requirements of various electronic equipment products for high speed and low power consumption and cope with fierce market competition, Nor flash memory chips need to achieve the design goals of high speed, low power consumption and low cost.

[0003] For Nor flash memory, the power supply is generally 1.2V, 1.8V or 3.3V. The read operation of the ETOX (Erasable Programmable Through Oxide) process requires high voltage to be applied to the control gate. Depending on the process node, the gate voltage of the read operation is generally between 5V and 6.5V, which needs to be generated inside the chip through a boost circuit (such as a charge pump circuit). The establishment speed of this boost circuit needs to meet two scenarios: 1. For the first address of the read operation, it needs to be established after the read instruction and the selected address are received, and before the sense amplifier is enabled; 2. For the scenario of switching word lines, it needs to be established after the previous address is switched, and before the sense amplifier is enabled.

[0004] As the read speed requirements become higher and higher, the read voltage build-up time becomes shorter and shorter, resulting in higher and higher requirements for the boost circuit drive capability, which in turn increases the chip cost, especially for low power supply voltage products. In order to meet this demand, the existing practice is to add a standby high voltage circuit to pre-raise the read operation voltage signal inside the chip to the standby voltage, which can be lower than the read voltage or approximately equal to the read voltage. However, a negative impact is the increase in standby power consumption. Summary of the invention

[0005] The technical problem to be solved by the present disclosure is to overcome the defect of high standby power consumption of the standby high voltage circuit in the prior art, and to provide a high voltage undervoltage detection circuit and its high voltage circuit and chip.

[0006] The present invention solves the above technical problems through the following technical solutions:

[0007] According to a first aspect of the present disclosure, there is provided a high voltage undervoltage detection circuit, the high voltage undervoltage detection circuit comprising a voltage division sampling circuit, a pull-up current control circuit, a pull-down current control circuit, a voltage comparison circuit and an output circuit connected with electrical signals;

[0008] The voltage-dividing sampling circuit is used to access the high-voltage signal to be detected, and generate a sampling voltage signal under the drive of the high-voltage signal to be detected, and transmit the sampling voltage signal to the pull-up current control circuit;

[0009] The pull-up current control circuit is used to generate a pull-up current and transmit it to the pull-down current control circuit under the drive of the sampling voltage signal and the preset high voltage signal;

[0010] The pull-down current control circuit is used to form a detection voltage signal under the drive of the pull-up current and transmit it to the voltage comparison circuit;

[0011] The voltage comparison circuit is used for generating a driving signal and transmitting it to the output circuit in response to the detection voltage signal being less than the rated voltage signal, so as to drive the output circuit to output a high-voltage under-voltage lockout signal.

[0012] Preferably, the high voltage undervoltage detection circuit further includes a reset circuit;

[0013] The reset circuit is connected to the voltage comparison circuit;

[0014] The reset circuit is used to generate a reset drive signal based on a first external trigger signal to drive the voltage comparison circuit to reset.

[0015] Preferably, the high voltage undervoltage detection circuit further includes a node initialization circuit and a level conversion circuit;

[0016] The node initialization circuit is connected to the pull-up current control circuit, the voltage comparison circuit and the level conversion circuit respectively, and the level conversion circuit is also connected to the voltage comparison circuit, the pull-up current control circuit and the voltage division sampling circuit;

[0017] The node initialization circuit is used to generate a first initialization signal under the drive of the second external trigger signal and the driving signal, and transmit the first initialization signal to the pull-up current control circuit;

[0018] The level conversion circuit is used to generate a gate voltage control signal under the drive of the second external trigger signal and the drive signal, and transmit the gate voltage control signal to the pull-up current control circuit;

[0019] The pull-up current control circuit is also used for resetting under the driving of the first initialization signal and the gate voltage control signal;

[0020] The node initialization circuit is further configured to generate a second initialization signal based on the first external trigger signal, and transmit the second initialization signal to the voltage comparison circuit, so that the voltage comparison circuit is reset under the drive of the reset drive signal and the second initialization signal.

[0021] Preferably, the high voltage undervoltage detection circuit further includes a buffer circuit;

[0022] The voltage comparison circuit is connected to the output circuit, the node initialization circuit, and the level conversion circuit via the buffer circuit;

[0023] The buffer circuit is used for shaping and buffering the driving signal.

[0024] Preferably, the pull-up current control circuit comprises a first PMOS (P-Channel-Oxide-Semiconductor) tube and a first NMOS (N-Metal-Oxide-Semiconductor) tube, wherein the first NMOS tube is a deep N-well high-voltage thick-gate NMOS tube;

[0025] The pull-down current control circuit includes a depletion-type MOS (metal-oxide-semiconductor field-effect transistor) tube and a second NMOS tube;

[0026] The voltage comparison circuit includes a second PMOS tube and a third NMOS tube;

[0027] The drain and deep N-well of the first NMOS tube are both used to access the high-voltage signal to be detected, the gate of the first NMOS tube is used to access the preset high-voltage signal, the P-well (P-type well) and source of the first NMOS tube are both connected to the well and source of the first PMOS tube, the gate of the first PMOS tube is connected to the voltage-dividing sampling circuit, and the drain of the first PMOS tube is connected to the drain of the depletion-type MOS tube;

[0028] The source of the depletion-type MOS tube is connected to the drain of the second NMOS tube, the gate of the second PMOS tube, and the gate of the third NMOS tube; the gate of the depletion-type MOS tube is connected to the gate of the second NMOS tube, the drain of the second PMOS tube, the drain of the third NMOS tube, and the output circuit; and the source of the second NMOS tube is grounded;

[0029] The source of the second PMOS tube is connected to the power supply voltage, and the source of the third NMOS tube is grounded.

[0030] Preferably, the high voltage undervoltage detection circuit further includes a reset circuit;

[0031] The reset circuit includes a fourth NMOS tube;

[0032] The drain of the fourth NMOS tube is connected to the source of the depletion-type MOS tube, the drain of the second NMOS tube, the gate of the second PMOS tube, and the gate of the third NMOS tube. The gate of the fourth NMOS tube is used to receive a first external trigger signal. The source of the fourth NMOS tube is grounded.

[0033] Preferably, the high voltage undervoltage detection circuit further includes a node initialization circuit and a level conversion circuit;

[0034] The pull-up current control circuit further includes a fifth NMOS transistor; wherein the fifth NMOS transistor is the deep N-well high-voltage thick-gate NMOS transistor;

[0035] The voltage comparison circuit also includes a third PMOS tube and a fourth PMOS tube;

[0036] The node initialization circuit includes a first inverter, a first NAND gate, a sixth NMOS transistor and a fifth PMOS transistor;

[0037] The level conversion circuit comprises a second inverter, a third inverter, a second NAND gate, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube;

[0038] The P well and source of the first NMOS tube are connected to the drain of the fifth NMOS tube and the well of the first PMOS tube, the P well and source of the fifth NMOS tube are connected to the source of the first PMOS tube and the drain of the sixth NMOS tube, the gate of the fifth NMOS tube is connected to the drain of the eighth PMOS tube and the drain of the ninth NMOS tube, and the deep N well of the fifth NMOS tube is used to access the high voltage signal to be detected;

[0039] The input end of the first inverter and the input end of the second inverter are both used to receive a second external trigger signal, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate, the second input end of the second NAND gate, the gate of the third PMOS tube, the drain of the second PMOS tube, the drain of the third NMOS tube, the gate of the fourth PMOS tube, the drain of the fifth PMOS tube, the gate of the second NMOS tube, and the gate of the depletion-type MOS tube are connected to each other, the output end of the first NAND gate is connected to the gate of the sixth NMOS tube, the source of the sixth NMOS tube is grounded, the source of the fifth PMOS tube is connected to the power supply voltage and the source of the fourth PMOS tube, and the gate of the fifth PMOS tube is used to receive the first external trigger signal;

[0040] The drain of the fourth PMOS tube is connected to the drain of the first PMOS tube and the drain of the depletion-type MOS tube, the drain of the third PMOS tube is connected to the source of the depletion-type MOS tube, the drain of the second NMOS tube, the drain of the fourth NMOS tube, the gate of the second PMOS tube, and the gate of the fifth PMOS tube, and the source of the third PMOS tube is connected to the power supply voltage;

[0041] The first input end of the second NAND gate is connected to the output end of the second inverter, the output end of the second NAND gate is connected to the gate of the seventh NMOS tube and the input end of the third inverter, the output end of the third inverter is connected to the gate of the eighth NMOS tube, the drain of the ninth NMOS is connected to the drain of the sixth PMOS tube and the gate of the seventh PMOS tube, the gate of the sixth PMOS tube, the drain of the seventh PMOS tube, the drain of the eighth NMOS tube, the gate of the eighth PMOS tube, and the gate of the ninth NMOS tube are connected to each other, the source of the sixth PMOS tube, the source of the seventh PMOS tube, and the source of the eighth PMOS tube are all used to access the high-voltage signal to be detected, and the source of the seventh NMOS tube, the source of the eighth NMOS tube, and the source of the ninth NMOS tube are all grounded.

[0042] Preferably, the high voltage undervoltage detection circuit further comprises a buffer circuit arranged between the voltage comparison circuit and the output circuit;

[0043] The buffer circuit includes a ninth PMOS tube, a tenth PMOS tube, a tenth NMOS tube and an eleventh NMOS tube;

[0044] The source of the ninth PMOS tube and the source of the tenth PMOS tube are both connected to the power supply voltage, the gate of the ninth PMOS tube, the gate of the tenth NMOS tube, the gate of the third PMOS tube, the drain of the second PMOS tube, the drain of the third NMOS tube, the gate of the fourth PMOS tube, and the drain of the fifth PMOS tube are connected to each other, the drain of the ninth PMOS tube, the gate of the tenth PMOS tube, the drain of the tenth NMOS tube, and the gate of the eleventh NMOS tube are connected to each other, the drain of the tenth PMOS tube, the drain of the eleventh NMOS tube, the second input end of the first NAND gate, the second input end of the second NAND gate, the gate of the depletion-type MOS tube, the gate of the second NMOS tube, and the output circuit are connected to each other, and the source of the tenth NMOS tube and the source of the eleventh NMOS tube are both grounded.

[0045] Preferably, the pull-up current control circuit further includes a twelfth NMOS tube; wherein the twelfth NMOS tube is the deep N-well high-voltage thick-gate NMOS tube;

[0046] The pull-down current control circuit also includes a thirteenth NMOS tube;

[0047] The drain, gate and deep N-well of the twelfth NMOS tube are all used to access the high-voltage signal to be detected, and the drain of the first NMOS tube is connected to the P-well and source of the twelfth NMOS tube;

[0048] The source of the second NMOS tube is connected to the drain of the thirteenth NMOS tube, the gate of the thirteenth NMOS tube is connected to the gate of the depletion-type MOS tube, the gate of the second NMOS tube, and the output circuit, and the source of the thirteenth NMOS tube is grounded.

[0049] Preferably, the voltage-dividing sampling circuit comprises a resistance voltage-dividing sampling circuit;

[0050] The resistor voltage-dividing sampling circuit comprises a first voltage-dividing resistor and a second voltage-dividing resistor, one end of the first voltage-dividing resistor is used to access the high-voltage signal to be detected, the other end of the first voltage-dividing resistor is connected to one end of the second voltage-dividing resistor and is connected to the pull-up current control circuit, and the other end of the second voltage-dividing resistor is grounded;

[0051] or,

[0052] The voltage-dividing sampling circuit comprises a MOS diode voltage-dividing sampling circuit;

[0053] The MOS diode voltage division sampling circuit comprises a first voltage division sampling unit and a second voltage division sampling unit connected in sequence;

[0054] The first voltage division sampling unit includes a first number of deep N-well high-voltage thick-gate NMOS transistors connected in sequence, and the second voltage division sampling unit includes a second number of the deep N-well high-voltage thick-gate NMOS transistors connected in sequence;

[0055] The connection method of the sequentially connected deep N-well high-voltage thick-gate NMOS tubes includes connecting the P-well and source of the previous deep N-well high-voltage thick-gate NMOS tube to the gate and drain of the next deep N-well high-voltage thick-gate NMOS tube;

[0056] The gate and drain of the first deep N-well high-voltage thick-gate NMOS tube of the first voltage-dividing sampling unit are used to access the high-voltage signal to be detected, the p-well and source of the last deep N-well high-voltage thick-gate NMOS tube of the first voltage-dividing sampling unit are connected to the gate and drain of the first deep N-well high-voltage thick-gate NMOS tube of the second voltage-dividing sampling unit and are accessed to the pull-up current control circuit, and the p-well and source of the last deep N-well high-voltage thick-gate NMOS tube of the second voltage-dividing sampling unit are grounded.

[0057] According to a second aspect of the present disclosure, a high voltage circuit is provided, wherein the high voltage circuit comprises the high voltage undervoltage detection circuit described in the first aspect of the present disclosure.

[0058] Preferably, the high-voltage circuit further includes a first boost circuit, a second boost circuit, a high-voltage detection control circuit, a transmission power NMOS tube, a first high-voltage switch, a second high-voltage switch, a first voltage stabilizing capacitor, a second voltage stabilizing capacitor and a load circuit;

[0059] The output end of the first boost circuit is connected to the first voltage stabilizing capacitor, the high voltage undervoltage detection circuit, and the gate of the transmission power NMOS tube via the first high voltage switch;

[0060] The output end of the second boost circuit is connected to the high-voltage detection control circuit, and the output end of the second boost circuit is also connected to the second voltage stabilizing capacitor, the high-voltage undervoltage detection circuit, and the drain of the transmission power NMOS tube via the second high-voltage switch;

[0061] The P well and source of the transmission power NMOS tube are connected to the load circuit;

[0062] The high voltage detection control circuit is connected to the high voltage undervoltage detection circuit, the first boost circuit, and the second boost circuit;

[0063] The high-voltage detection control circuit is used for triggering the first boost circuit and the second boost circuit to stop working in response to the high-voltage signal to be detected output by the second boost circuit reaching a target voltage value;

[0064] The high-voltage detection control circuit is further used to receive a high-voltage under-voltage lockout signal output by the high-voltage under-voltage detection circuit, and trigger the first boost circuit and the second boost circuit to start working.

[0065] Preferably, the high voltage circuit further includes a leakage compensation circuit;

[0066] The leakage compensation circuit is connected to the P well and source of the transmission power NMOS tube and the load circuit;

[0067] The leakage compensation circuit is used to compensate for the channel leakage current of the transmission power NMOS tube.

[0068] According to a third aspect of the present disclosure, a chip is provided, wherein the chip comprises the high-voltage undervoltage detection circuit described in the first aspect of the present disclosure, or the high-voltage circuit described in the second aspect of the present disclosure.

[0069] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0070] The positive and progressive effect of the present disclosure is that the high-voltage undervoltage detection circuit has no power consumption on the power supply voltage during the standby undervoltage detection stage, the standby current is smaller, and the reliability of each component in the high-voltage undervoltage detection circuit is ensured, ensuring that the high-voltage circuit operates stably and reliably. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1 It is a schematic diagram of a first circuit module of the high voltage undervoltage detection circuit disclosed in the present invention;

[0072] Figure 2 This is a schematic diagram of a first circuit structure of a high voltage undervoltage detection circuit disclosed in the present invention;

[0073] Figure 3 It is a schematic diagram of a second circuit module of the high voltage undervoltage detection circuit disclosed in the present invention;

[0074] Figure 4 It is a schematic diagram of a second circuit structure of the high voltage undervoltage detection circuit disclosed in the present invention;

[0075] Figure 5 It is a schematic diagram of a third circuit module of the high voltage undervoltage detection circuit disclosed in the present invention;

[0076] Figure 6 Schematic diagram of the third circuit structure of the high voltage undervoltage detection circuit disclosed in the present invention;

[0077] Figure 7 It is a schematic diagram of a fourth circuit module of the high voltage undervoltage detection circuit disclosed in the present invention;

[0078] Figure 8 Schematic diagram of a fourth circuit structure of the high-voltage undervoltage detection circuit disclosed in the present invention;

[0079] Fig. 9 is a fifth circuit structure schematic diagram of the high voltage undervoltage detection circuit disclosed in the present invention;

[0080] Fig.10 Schematic diagram of the circuit structure of the high voltage circuit disclosed in the present invention;

[0081] Fig.11 Schematic diagram of voltage signal waveform of the high voltage circuit in the standby mode of the present disclosure. DETAILED DESCRIPTION

[0082] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0083] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0084] In the embodiments of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0085] Example 1

[0086] In a specific embodiment of the present disclosure, a high voltage undervoltage detection circuit is provided, such as Figure 1 As shown, the high voltage undervoltage detection circuit includes a voltage division sampling circuit 1, a pull-up current control circuit 2, a pull-down current control circuit 3, a voltage comparison circuit 4 and an output circuit 5 connected with electrical signals;

[0087] The voltage-dividing sampling circuit 1 is used to access the high-voltage signal VHD to be detected, and generate a sampling voltage signal under the drive of the high-voltage signal VHD to be detected, and transmit the sampling voltage signal to the pull-up current control circuit 2;

[0088] The pull-up current control circuit 2 is used to generate a pull-up current and transmit it to the pull-down current control circuit 3 under the drive of the sampling voltage signal and the preset high voltage signal VHG;

[0089] The pull-down current control circuit 3 is used to generate a detection voltage signal under the drive of the pull-up current and transmit it to the voltage comparison circuit 4;

[0090] The voltage comparison circuit 4 is used for generating a driving signal in response to the detection voltage signal being less than the rated voltage signal, and transmitting the driving signal to the output circuit 5 to drive the output circuit 5 to output the high voltage under-voltage lockout signal HVUVLO.

[0091] Among them, Figure 2 As shown, the pull-up current control circuit 2 includes a first PMOS transistor P1 and a first NMOS transistor N1, and the first NMOS transistor N1 is a deep N-well high-voltage thick-gate NMOS transistor;

[0092] The pull-down current control circuit 3 includes a depletion-type MOS transistor and a second NMOS transistor N2;

[0093] The voltage comparison circuit 4 includes a second PMOS transistor P2 and a third NMOS transistor N3;

[0094] The drain and deep N-well of the first NMOS tube N1 are both used to access the high-voltage signal VHD to be detected, the gate of the first NMOS tube N1 is used to access the preset high-voltage signal VHG, the P-well and source of the first NMOS tube N1 are both connected to the well and source of the first PMOS tube P1, the gate of the first PMOS tube P1 is connected to the voltage-dividing sampling circuit 1, and the drain of the first PMOS tube P1 is connected to the drain of the depletion-type MOS tube;

[0095] The source of the depletion-type MOS tube is connected to the drain of the second NMOS tube N2, the gate of the second PMOS tube P2, and the gate of the third NMOS tube N3; the gate of the depletion-type MOS tube is connected to the gate of the second NMOS tube N2, the drain of the second PMOS tube P2, the drain of the third NMOS tube N3, and the output circuit 5; the source of the second NMOS tube N2 is grounded;

[0096] The source of the second PMOS transistor P2 is connected to the power supply voltage, and the source of the third NMOS transistor N3 is grounded.

[0097] Specifically, a high-voltage undervoltage detection circuit is usually arranged in a high-voltage circuit. Since the high-voltage circuit has two modes, namely a normal working mode and a standby mode: in the normal working mode, the high-voltage circuit is always in a high-voltage state, so the high-voltage undervoltage detection circuit may work or not work; and the standby mode is divided into a standby undervoltage detection stage and a standby high-voltage boost stage. When the high-voltage circuit is boosted to reach the target voltage value in the standby high-voltage boost stage, it will enter the standby undervoltage detection stage. The high-voltage undervoltage detection circuit needs to perform high-voltage undervoltage detection on the high-voltage circuit, and outputs a high-voltage undervoltage lockout signal HVUVLO when the high-voltage signal VHD to be detected reaches the threshold flip point, so that the high-voltage circuit enters the standby high-voltage boost stage, and the cycle continues.

[0098] In the high voltage undervoltage detection circuit of this specific embodiment, the voltage division sampling circuit 1, the pull-up current control circuit 2, the pull-down current control circuit 3, the voltage comparison circuit 4 and the output circuit 5 are connected in sequence.

[0099] The voltage-dividing sampling circuit 1 can divide the high-voltage signal VHD to be detected by using resistor voltage division or other voltage division methods (for example, MOS diode voltage division, etc.), and generate a sampling voltage signal which is sent to the gate of the first PMOS tube P1 in the pull-up current control circuit 2 through the Net1 node.

[0100] The pull-up current control circuit 2 is provided with a first NMOS tube N1 of a deep N-well high-voltage thick-gate NMOS tube, and a preset high-voltage signal VHG is connected to the gate of the first NMOS tube N1 to clamp the voltage of the Net5 node. The well potential of the first PMOS tube P1 is connected to the Net5 node, and a pull-up current is generated under the joint action of the sampled voltage signal and the preset high-voltage signal VHG, and is transmitted to the pull-down current control circuit 3 via the drain of the first PMOS tube P1. When the high-voltage undervoltage detection circuit is provided in a high-voltage circuit, the preset high-voltage signal VHG may be a high-voltage signal generated in the high-voltage circuit.

[0101] The depletion-type MOS tube in the pull-down current control circuit 3 is a high-voltage Native (a special electronic component) tube, and the drain of the depletion-type MOS tube is connected to the drain of the first PMOS tube P1 to access the pull-up current. Under the joint action of the depletion-type MOS tube and the second NMOS tube N2, the pull-up current is transmitted to the voltage comparison circuit 4 through the Net9 node output detection voltage signal. Among them, the second NMOS tube N2 can be a high-voltage tube or a low-voltage tube. In the standby undervoltage detection stage, the depletion-type MOS tube and the second NMOS tube N2 both work in the strong inversion region.

[0102] The voltage comparison circuit 4 is composed of a second PMOS tube P2 and a third NMOS tube N3, wherein the second PMOS tube P2 and the third NMOS tube N3 can be low-voltage tubes, and the depletion-type MOS tube in the pull-down current control circuit 3 can protect the second PMOS tube P2 and the third NMOS tube N3 to ensure the reliability of the device. The voltage comparison circuit 4 is used to determine whether the voltage of the Net9 node is greater than the threshold flip point (i.e., greater than the rated voltage signal). When the threshold flip point is exceeded, the push-pull amplifier composed of the second PMOS tube P2 and the third NMOS tube N3 will amplify the signal and output it to the output circuit 5 via the Net10 node to drive the inverter in the output circuit 5 to generate a high-voltage undervoltage lockout signal HVUVLO. The high-voltage undervoltage lockout signal HVUVLO is sent to the high-voltage circuit to drive the high-voltage circuit to enter the standby high-voltage boost stage.

[0103] In a specific embodiment, Figure 3As shown, the high voltage undervoltage detection circuit also includes a reset circuit 6;

[0104] The reset circuit 6 is connected to the voltage comparison circuit 4;

[0105] The reset circuit 6 is used to generate a reset drive signal based on the first external trigger signal to drive the voltage comparison circuit 4 to reset.

[0106] like Figure 4 As shown, the reset circuit 6 includes a fourth NMOS tube N4;

[0107] The drain of the fourth NMOS tube N4 is connected to the source of the depletion-type MOS tube, the drain of the second NMOS tube N2, the gate of the second PMOS tube P2, and the gate of the third NMOS tube N3. The gate of the fourth NMOS tube N4 is used to receive the first external trigger signal. The source of the fourth NMOS tube N4 is grounded.

[0108] Specifically, when the high-voltage circuit enters the standby high-voltage boost stage, it will output a first external trigger signal, wherein the first external trigger signal includes an Rst signal and an RstN signal. In order to enable the high-voltage undervoltage detection circuit to perform cyclic high-voltage undervoltage detection on the standby undervoltage detection stage of the high-voltage circuit, a reset circuit 6 including a fourth NMOS tube N4 is provided in the high-voltage undervoltage detection circuit. The gate of the fourth NMOS tube N4 is used to receive the Rst signal in the first external trigger signal. The drain of the fourth NMOS tube N4 is connected to the Net9 node and the gate of the second PMOS tube P2 and the gate of the third NMOS tube N3, so as to reset the Net9 node based on the Rst signal and enter the next round of high-voltage undervoltage detection.

[0109] In a specific embodiment, Figure 5 As shown, the high voltage undervoltage detection circuit also includes a node initialization circuit 7 and a level conversion circuit 8;

[0110] The node initialization circuit 7 is connected to the pull-up current control circuit 2, the voltage comparison circuit 4 and the level conversion circuit 8 respectively, and the level conversion circuit 8 is also connected to the voltage comparison circuit 4, the pull-up current control circuit 2 and the voltage division sampling circuit 1;

[0111] The node initialization circuit 7 is used to generate a first initialization signal under the drive of the second external trigger signal CP2EN and the driving signal, and transmit the first initialization signal to the pull-up current control circuit 2;

[0112] The level conversion circuit 8 is used to generate a gate voltage control signal under the drive of the second external trigger signal CP2EN and the driving signal, and transmit the gate voltage control signal to the pull-up current control circuit 2;

[0113] The pull-up current control circuit 2 is also used for resetting under the drive of the first initialization signal and the gate voltage control signal;

[0114] The node initialization circuit 7 is further configured to generate a second initialization signal based on the first external trigger signal, and transmit the second initialization signal to the voltage comparison circuit 4, so that the voltage comparison circuit 4 is reset under the driving of the reset drive signal and the second initialization signal.

[0115] Among them, Figure 6 As shown, the pull-up current control circuit 2 further includes a fifth NMOS transistor N5; wherein the fifth NMOS transistor N5 is a deep N-well high-voltage thick-gate NMOS transistor;

[0116] The voltage comparison circuit 4 also includes a third PMOS tube P3 and a fourth PMOS tube P4;

[0117] The node initialization circuit 7 includes a first inverter inv1, a first NAND gate nand1, a sixth NMOS transistor N6 and a fifth PMOS transistor P5;

[0118] Level conversion circuit 8 second inverter inv2, third inverter inv3, second NAND gate nand2, seventh NMOS tube N7, eighth NMOS tube N8, ninth NMOS tube N9, sixth PMOS tube P6, seventh PMOS tube P7 and eighth PMOS tube P8;

[0119] The P well and source of the first NMOS tube N1 are connected to the drain of the fifth NMOS tube N5 and the well of the first PMOS tube P1, the P well and source of the fifth NMOS tube N5 are connected to the source of the first PMOS tube P1 and the drain of the sixth NMOS tube N6, the gate of the fifth NMOS tube N5 is connected to the drain of the eighth PMOS tube P8 and the drain of the ninth NMOS tube N9, and the deep N well of the fifth NMOS tube N5 is used to access the high voltage signal VHD to be detected;

[0120] The input end of the first inverter inv1 and the input end of the second inverter inv2 are both used to receive the second external trigger signal CP2EN, the output end of the first inverter inv1 is connected to the first input end of the first NAND gate nand1, the second input end of the first NAND gate nand1, the second input end of the second NAND gate nand2, the gate of the third PMOS tube P3, the drain of the second PMOS tube P2, the drain of the third NMOS tube N3, the gate of the fourth PMOS tube P4, the drain of the fifth PMOS tube P5, the gate of the second NMOS tube N2, and the gate of the depletion-type MOS tube are connected to each other, the output end of the first NAND gate nand1 is connected to the gate of the sixth NMOS tube N6, the source of the sixth NMOS tube N6 is grounded, the source of the fifth PMOS tube P5 is connected to the power supply voltage and the source of the fourth PMOS tube P4, and the gate of the fifth PMOS tube P5 is used to receive the first external trigger signal;

[0121] The drain of the fourth PMOS tube P4 is connected to the drain of the first PMOS tube P1 and the drain of the depletion-type MOS tube, the drain of the third PMOS tube P3 is connected to the source of the depletion-type MOS tube, the drain of the second NMOS tube N2, the drain of the fourth NMOS tube N4, the gate of the second PMOS tube P2, and the gate of the fifth PMOS tube P5, and the source of the third PMOS tube P3 is connected to the power supply voltage;

[0122] The first input end of the second NAND gate nand2 is connected to the output end of the second inverter inv2, the output end of the second NAND gate nand2 is connected to the gate of the seventh NMOS tube N7 and the input end of the third inverter inv3, the output end of the third inverter inv3 is connected to the gate of the eighth NMOS tube N8, the drain of the ninth NMOS is connected to the drain of the sixth PMOS tube P6 and the gate of the seventh PMOS tube P7, the gate of the sixth PMOS tube P6, the drain of the seventh PMOS tube P7, the drain of the eighth NMOS tube N8, the gate of the eighth PMOS tube P8, and the gate of the ninth NMOS tube N9 are connected to each other, the source of the sixth PMOS tube P6, the source of the seventh PMOS tube P7, and the source of the eighth PMOS tube P8 are all used to access the high-voltage signal VHD to be detected, and the source of the seventh NMOS tube N7, the source of the eighth NMOS tube N8, and the source of the ninth NMOS tube N9 are all grounded.

[0123] Specifically, the pull-up current control circuit 2 also includes a fifth NMOS tube N5 of a deep N-well high-voltage thick-gate NMOS tube, the gate of the fifth NMOS tube N5 is connected to the output end of the level conversion circuit 8, the level conversion circuit 8 controls the gate voltage of the fifth NMOS tube N5 based on the second external trigger signal CP2EN and the output voltage of the Net10 node, and the fifth NMOS tube N5 is arranged between the first NMOS tube N1 and the first PMOS tube P1, for isolating the Net2 node from the Net5 node. When the high-voltage undervoltage detection circuit is arranged in the high-voltage circuit, the high-voltage circuit enters the standby high-voltage boost stage to generate the second external trigger signal CP2EN input to the level conversion circuit 8, driving the fifth NMOS tube N5 to turn off, so that the Net5 node is isolated from the Net2 node, avoiding the forward conduction current of the parasitic PN junction formed by the drain of the first PMOS tube P1 to the well potential and the channel conduction current formed by the first NMOS tube N1 and the sixth NMOS tube N6 in the standby high-voltage boost stage.

[0124] The voltage comparison circuit 4 also includes a third PMOS transistor P3 and a fourth PMOS transistor P4. The Net10 node controls the gate voltages of the third PMOS transistor P3 and the fourth PMOS transistor P4 to form a positive feedback loop, and quickly pulls the Net9 node and the Net0 node up to the power supply voltage VDD.

[0125] The node initialization circuit 7 is composed of a first inverter inv1, a first NAND gate nand1, a sixth NMOS tube N6 and a fifth PMOS tube P5. The fifth NMOS tube N5 is used to initialize the Net10 node based on the RstN signal in the first external trigger signal, and the eighth NMOS tube N8 is used to initialize the high-voltage node Net2 node. The gate circuit composed of the first inverter inv1 and the first NAND gate nand1 is used to jointly control the gate voltage of the eighth NMOS tube N8 based on the second external trigger signal CP2EN and the output voltage of the Net10 node.

[0126] In a specific embodiment, Figure 7 As shown, the high voltage undervoltage detection circuit also includes a buffer circuit 9;

[0127] The voltage comparison circuit 4 is connected to the output circuit 5, the node initialization circuit 7, and the level conversion circuit 8 via the buffer circuit 9;

[0128] The buffer circuit 9 is used to shape and buffer the driving signal.

[0129] In a specific example, if Figure 8 As shown, the high voltage undervoltage detection circuit further includes a buffer circuit 9 arranged between the voltage comparison circuit 4 and the output circuit 5;

[0130] The buffer circuit 9 includes a ninth PMOS transistor P9, a tenth PMOS transistor P10, a tenth NMOS transistor N10 and an eleventh NMOS transistor N11;

[0131] The source of the ninth PMOS tube P9 and the source of the tenth PMOS tube P10 are both connected to the power supply voltage, the gate of the ninth PMOS tube P9, the gate of the tenth NMOS tube N10, the gate of the third PMOS tube P3, the drain of the second PMOS tube P2, the drain of the third NMOS tube N3, the gate of the fourth PMOS tube P4, and the drain of the fifth PMOS tube P5 are connected to each other, the drain of the ninth PMOS tube P9, the gate of the tenth PMOS tube P10, the drain of the tenth NMOS tube N10, and the gate of the eleventh NMOS tube N11 are connected to each other, the drain of the tenth PMOS tube P10, the drain of the eleventh NMOS tube N11, the second input end of the first NAND gate nand1, the second input end of the second NAND gate nand2, the gate of the depletion-type MOS tube, the gate of the second NMOS tube N2, and the output circuit 5 are connected to each other, and the source of the tenth NMOS tube N10 and the source of the eleventh NMOS tube N11 are both grounded.

[0132] In a specific embodiment, Figure 8 As shown, the pull-up current control circuit 2 further includes a twelfth NMOS transistor N12; wherein the twelfth NMOS transistor N12 is a deep N-well high-voltage thick-gate NMOS transistor;

[0133] The pull-down current control circuit 3 further includes a thirteenth NMOS transistor N13;

[0134] The drain, gate and deep N-well of the twelfth NMOS transistor N12 are all used to access the high-voltage signal VHD to be detected, and the drain of the first NMOS transistor N1 is connected to the P-well and source of the twelfth NMOS transistor N12;

[0135] The source of the second NMOS transistor N2 is connected to the drain of the thirteenth NMOS transistor N13, the gate of the thirteenth NMOS transistor N13 is connected to the gate of the depletion-type MOS transistor, the gate of the second NMOS transistor N2, and the output circuit 5, and the source of the thirteenth NMOS transistor N13 is grounded.

[0136] Specifically, the pull-up current control circuit 2 is also provided with a twelfth NMOS tube N12 of a deep N-well high-voltage thick-gate NMOS tube, and the gate of the twelfth NMOS tube N12 is connected to the high-voltage signal VHD to be detected to form a MOS diode. The buffer circuit 9 is used to shape and buffer the output voltage of the Net10 node of the front-stage voltage comparison circuit 4, and output the voltage of the Net12 node. The pull-down current control circuit 3 also includes a thirteenth NMOS tube N13, and the gate of the second NMOS tube N2 and the gate of the thirteenth NMOS tube N13 are connected to the Net12 node voltage output by the buffer circuit 9. Among them, the output Net12 node voltage is also connected to the node initialization circuit 7 and the level conversion circuit 8, and the voltage output by the Net12 node generates a high-voltage undervoltage lockout signal HVUVLO through the inverter INV.

[0137] In a specific embodiment, Figure 8 As shown, the voltage-dividing sampling circuit 1 includes a resistor voltage-dividing sampling circuit;

[0138] The resistor voltage-dividing sampling circuit includes a first voltage-dividing resistor R0 and a second voltage-dividing resistor R1. One end of the first voltage-dividing resistor R0 is used to connect to the high-voltage signal VHD to be detected. The other end of the first voltage-dividing resistor R0 is connected to one end of the second voltage-dividing resistor R1 and connected to the pull-up current control circuit 2. The other end of the second voltage-dividing resistor R1 is grounded.

[0139] Specifically, the voltage-dividing sampling circuit 1 divides the high-voltage signal VHD to be detected through the first voltage-dividing resistor R0 and the second voltage-dividing resistor R1 to generate a sampling voltage signal, which is sent to the gate of the first PMOS tube P1 in the pull-up current control circuit 2 through the Net1 node. The resistance values ​​of the first voltage-dividing resistor R0 and the second voltage-dividing resistor R1 can be set according to the actual voltage-dividing requirements.

[0140] In another specific embodiment, Fig. 9 As shown, the voltage-dividing sampling circuit 1 includes a MOS diode voltage-dividing sampling circuit;

[0141] The MOS diode voltage division sampling circuit comprises a first voltage division sampling unit 11 and a second voltage division sampling unit 12 connected in sequence;

[0142] The first voltage division sampling unit 11 includes a first number of deep N-well high-voltage thick-gate NMOS transistors connected in sequence, and the second voltage division sampling unit 12 includes a second number of deep N-well high-voltage thick-gate NMOS transistors connected in sequence;

[0143] The connection method of the sequentially connected deep N-well high-voltage thick-gate NMOS tubes includes connecting the P-well and source of the previous deep N-well high-voltage thick-gate NMOS tube to the gate and drain of the next deep N-well high-voltage thick-gate NMOS tube;

[0144] The gate and drain of the first deep N-well high-voltage thick-gate NMOS tube of the first voltage-dividing sampling unit 11 are used to access the high-voltage signal VHD to be detected, the p-well and source of the last deep N-well high-voltage thick-gate NMOS tube of the first voltage-dividing sampling unit 11 are connected to the gate and drain of the first deep N-well high-voltage thick-gate NMOS tube of the second voltage-dividing sampling unit 12 and are connected to the pull-up current control circuit 2, and the p-well and source of the last deep N-well high-voltage thick-gate NMOS tube of the second voltage-dividing sampling unit 12 are grounded.

[0145] Specifically, the first voltage-dividing sampling unit 11 and the second voltage-dividing sampling unit 12 composed of a plurality of deep N-well high-voltage thick-gate NMOS tubes form a MOS diode voltage-dividing sampling circuit, which divides the high-voltage signal VHD to be detected to generate a sampling voltage signal, which is sent to the gate of the first PMOS tube P1 in the pull-up current control circuit 2 through the Net1 node. The number of deep N-well high-voltage thick-gate NMOS tubes in the first voltage-dividing sampling unit 11 and the second voltage-dividing sampling unit 12 can be set according to the actual voltage-dividing requirements.

[0146] Of course, the first voltage-dividing sampling unit 11 and the second voltage-dividing sampling unit 12 in the MOS diode voltage-dividing sampling circuit may also be composed of high-voltage PMOS, which is not limited in this specific implementation.

[0147] In a specific example, if Figure 8 As shown, the working principle of the high-voltage undervoltage detection circuit is as follows: when the high-voltage circuit is converted from the standby high-voltage boost stage to the initial stage of the standby undervoltage detection, the first external trigger signal Rst and the second external trigger signal CP2EN change from high to low. At this time, the voltage value of the Net1 node is the sampling voltage signal VNet1=VHD*R0 / (R0+R1) of R0 and R1, and the voltages of the Net10 node and the Net12 node are both the power supply voltage VDD; the voltage of the Net9 node is 0V, the Net2 node is initially 0, and then rises under the action of the pull-up current path; the gate voltages of N0, N2, and N13 in the pull-down current control circuit 3 are all VDD, and are all in the strong inversion region.

[0148] Looking down from the Net0 node, there is a pull-down path to the ground. At this time, the voltage of the Net0 node is equal to the voltage of the Net9 node, which is equal to 0V; N5 is turned on, so the voltage of the Net2 node is equal to the voltage of the Net5 node, both equal to VHG-VTHN (where VTHN is the threshold voltage of N1). At this time, the gate-source voltage of P1 is VSG_P1=VNet2-VNet1. When VHD is high enough, VSG<|VTHP|(VTHP is the threshold voltage of P1), P1 is in the cut-off state, and the voltage of the Net0 node remains at 0V.

[0149] Due to the existence of leakage current and resistor voltage-divided DC current in the high-voltage circuit, the VHD voltage will gradually decrease, and thus the voltage of the Net1 node will also gradually decrease. Under the clamping action of N1, the voltage of the Net2 node remains basically unchanged, so the gate voltage VSG_P1 of P1 gradually increases. As the VHD voltage decreases, the working area of ​​P1 changes from the cut-off area to the weak inversion area and then to the strong inversion area, generating a charging current for the Net0 node. Since the pull-down current control circuit 3 always has a leakage current for the Net0 node, the charging current gradually increases, causing the Net0 node and the Net9 node to gradually increase from 0V, and finally reaching the threshold flip of the voltage comparison circuit 4. point, due to the amplification of the voltage comparison circuit 4, the voltage of the Net10 node will become 0V, and the voltages of the Net0 node and the Net9 node are raised to the VDD voltage through the positive feedback loop control P3 and P4, and at the same time, the voltage of the Net12 node output by the buffer circuit 9 becomes a low level, and N5 is turned off by controlling the level conversion circuit 8 to cut off the pull-up current control circuit 2. The Net12 node simultaneously controls the gate of the node initialization circuit 7N8 to discharge the Net2 node to 0V, and the Net12 node also generates a high-voltage under-voltage lockout signal HVUVLO through the inverter INV, which is sent to the high-voltage circuit to trigger the high-voltage circuit to enter the standby high-voltage boost stage.

[0150] The high-voltage undervoltage detection circuit of this embodiment consumes no power to the power supply voltage during the standby undervoltage detection stage, has a smaller standby current, and can ensure the reliability of each component in the high-voltage undervoltage detection circuit, thereby ensuring that the high-voltage circuit operates stably and reliably.

[0151] Example 2

[0152] In a specific embodiment of the present disclosure, a high voltage circuit is provided, such as Fig.10 As shown, the high voltage circuit includes the high voltage undervoltage detection circuit described in any of the above embodiments.

[0153] In a specific embodiment, the high-voltage circuit further includes a first boost circuit CP1, a second boost circuit CP2, a high-voltage detection control circuit, a transmission power NMOS tube HVN1, a first high-voltage switch S0, a second high-voltage switch S1, a first voltage stabilizing capacitor C0, a second voltage stabilizing capacitor C1 and a load circuit;

[0154] The output end of the first boost circuit CP1 is connected to the first voltage stabilizing capacitor C0, the high voltage undervoltage detection circuit, and the gate of the transmission power NMOS tube HVN1 via the first high voltage switch S0;

[0155] The output end of the second boost circuit CP2 is connected to the high voltage detection control circuit, and the output end of the second boost circuit CP2 is also connected to the second voltage stabilizing capacitor C1, the high voltage undervoltage detection circuit, and the drain of the transmission power NMOS tube HVN1 via the second high voltage switch S1;

[0156] The P-well and source of the transmission power NMOS tube HVN1 are connected to the load circuit, and the deep N-well is connected to VHD;

[0157] The high voltage detection control circuit is connected to the high voltage undervoltage detection circuit, the first boost circuit CP1, and the second boost circuit CP2;

[0158] The high voltage detection control circuit is used for triggering the first boost circuit CP1 and the second boost circuit CP2 to stop working in response to the high voltage signal VHD to be detected output by the second boost circuit CP2 reaching a target voltage value;

[0159] The high voltage detection control circuit is further used to receive a high voltage under-voltage lockout signal HVUVLO output by the high voltage under-voltage detection circuit, and trigger the first boost circuit CP1 and the second boost circuit CP2 to start working.

[0160] Wherein, the high voltage circuit also includes a leakage compensation circuit;

[0161] The leakage compensation circuit is connected to the P well and source of the transmission power NMOS tube HVN1 and the load circuit;

[0162] The leakage compensation circuit is used to compensate for the channel leakage current of the transmission power NMOS tube HVN1.

[0163] Specifically, the first boost circuit CP1 in the high-voltage circuit includes a charge pump and a voltage regulator circuit, which is used to generate a high voltage VCP1; the second boost circuit CP2 includes a charge pump and a voltage regulator circuit, which is used to generate a high voltage VCP2; the high-voltage detection control circuit is used to detect the high-voltage signal to be detected VHD, and generate a high-voltage undervoltage lockout signal HVUVLO; the high-voltage detection control circuit is used to detect whether the high voltage VCP2 output by CP2 reaches the target voltage value, and generate an enable control signal CP1EN of CP1 and an enable control signal CP2EN of CP2, wherein CP1EN and CP2EN is collectively referred to as the enable signal EN; the first high-voltage switch S0 is used to control the connection and disconnection of the two nodes VCP1 and VHG; the second high-voltage switch S1 is used to control the connection and disconnection of the two nodes VCP2 and VHD; the first voltage-stabilizing capacitor C0 is used to store charge to ensure that the high-voltage signal VHG remains stable in the standby stage; the second voltage-stabilizing capacitor C1 is used to store charge to control the discharge speed of the high-voltage signal VHD to be detected; the transmission power tube HVN1, HVN1 is a deep N-well high-voltage NMOS tube, used to clamp the standby voltage VHS roughly equivalent to VHG (where VHS= VHG-Vth, Vth is the threshold voltage of HVN1); the leakage compensation circuit is used to compensate for the channel leakage current of the power transmission NMOS tube HVN1; the load circuit is generally the X-direction decoding and Y-direction decoding circuits of the flash memory array.

[0164] Among them, the high-voltage circuit has two modes: normal working mode and standby mode. In the normal working mode, EN is high, CP1, CP2 remain in the enabled state, output two high voltages VCP1 and VCP2, S0, S1 are in the on state, at this time VHG = VCP1, VHD = VCP2, where VCP2 must be guaranteed to be greater than VCP1, for example, it can be set to VCP2 = VCP1 + 3.5V. Due to the clamping effect of HVN1, VHS = VHG-VTHN (VTHN is the threshold voltage of HVN1), at this time the high-voltage undervoltage detection circuit can be enabled or not.

[0165] like Figure 10-11As shown, the standby mode of the high-voltage circuit is divided into the standby undervoltage detection stage T0 and the standby high-voltage boost stage T1. In the standby undervoltage detection stage, the EN signal is low, CP1 and CP2 are in a non-enabled state, S0 and S1 are turned off, and the high-voltage undervoltage detection circuit is enabled. At this time, due to the leakage current in the load circuit and the high-voltage undervoltage detection circuit, the DC static current or the switch dynamic current in the high-voltage undervoltage detection circuit, the VHD voltage will slowly decrease from the target voltage VCP2targ in the working mode, and the speed of decrease depends on the size of the C1 capacitor and the sum of the current and the leakage current in the high-voltage undervoltage detection circuit. The VHG voltage will also slowly decrease from the target voltage VCP1targ in the working mode, and the reduction amplitude is less than the reduction amplitude of VHD. When VHD is lower than a certain voltage value VHDmin, the high-voltage undervoltage detection circuit will pull up HVUVLO and activate the high-voltage detection control circuit. At the same time, the control enable signal EN of CP1 and CP2 will be pulled up to enable CP1 and CP2, and then the high-voltage circuit will enter the standby high-voltage boost stage.

[0166] In the standby high-voltage boost stage, CP1, CP2, and the high-voltage detection control circuit remain in working state, S0 and S1 are turned on, and when the high-voltage detection control circuit detects that VCP1 and VCP2 have reached the target voltage (VCP1targ and VCP2targ), a pulse reset signal (Rst and RstN) is sent through the high-voltage detection control circuit as the first external trigger signal to input the high-voltage undervoltage detection circuit to initialize the high-voltage undervoltage detection circuit, and EN is pulled low through the high-voltage detection control circuit, S0 and S1 are turned off, and the high-voltage detection control circuit is turned off after the above operations are completed, and then the high-voltage system enters the standby undervoltage detection stage again.

[0167] Since the high voltage undervoltage detection circuit has no power consumption on the power supply voltage during the standby undervoltage detection phase, that is, the standby undervoltage detection phase (corresponding to Fig.11 The current I in the T0 phase is 0, so the total standby average current I of the high voltage circuit is avg =(I T1 *T1) / (T0+T1), making the overall standby current of the high voltage circuit smaller.

[0168] The high-voltage undervoltage detection circuit in the high-voltage circuit of this embodiment consumes no power to the power supply voltage during the standby undervoltage detection stage, has a smaller standby current, and can ensure the reliability of each component in the high-voltage undervoltage detection circuit, thereby ensuring that the high-voltage circuit operates stably and reliably.

[0169] Example 3

[0170] In a specific embodiment of the present disclosure, a chip is provided, and the chip includes the high-voltage undervoltage detection circuit described in any of the above embodiments, or the high-voltage circuit described in any of the above embodiments.

[0171] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A high voltage undervoltage detection circuit, characterized in that: The high voltage undervoltage detection circuit comprises a voltage division sampling circuit, a pull-up current control circuit, a pull-down current control circuit, a voltage comparison circuit and an output circuit connected with electrical signals; The voltage-dividing sampling circuit is used to access the high-voltage signal to be detected, and generate a sampling voltage signal under the drive of the high-voltage signal to be detected, and transmit the sampling voltage signal to the pull-up current control circuit; The pull-up current control circuit is used to generate a pull-up current and transmit it to the pull-down current control circuit under the drive of the sampling voltage signal and the preset high voltage signal; The pull-down current control circuit is used to form a detection voltage signal under the drive of the pull-up current and transmit it to the voltage comparison circuit; The voltage comparison circuit is used for generating a driving signal and transmitting it to the output circuit in response to the detection voltage signal being less than the rated voltage signal, so as to drive the output circuit to output a high-voltage under-voltage lockout signal.

2. The high voltage undervoltage detection circuit according to claim 1, characterized in that: The high voltage undervoltage detection circuit also includes a reset circuit; The reset circuit is connected to the voltage comparison circuit; The reset circuit is used to generate a reset drive signal based on a first external trigger signal to drive the voltage comparison circuit to reset.

3. The high voltage undervoltage detection circuit according to claim 2, characterized in that: The high voltage undervoltage detection circuit also includes a node initialization circuit and a level conversion circuit; The node initialization circuit is connected to the pull-up current control circuit, the voltage comparison circuit and the level conversion circuit respectively, and the level conversion circuit is also connected to the voltage comparison circuit, the pull-up current control circuit and the voltage division sampling circuit; The node initialization circuit is used to generate a first initialization signal under the drive of the second external trigger signal and the driving signal, and transmit the first initialization signal to the pull-up current control circuit; The level conversion circuit is used to generate a gate voltage control signal under the drive of the second external trigger signal and the drive signal, and transmit the gate voltage control signal to the pull-up current control circuit; The pull-up current control circuit is also used for resetting under the driving of the first initialization signal and the gate voltage control signal; The node initialization circuit is further configured to generate a second initialization signal based on the first external trigger signal, and transmit the second initialization signal to the voltage comparison circuit, so that the voltage comparison circuit is reset under the drive of the reset drive signal and the second initialization signal.

4. The high voltage undervoltage detection circuit according to claim 3, characterized in that: The high voltage undervoltage detection circuit also includes a buffer circuit; The voltage comparison circuit is connected to the output circuit, the node initialization circuit, and the level conversion circuit via the buffer circuit; The buffer circuit is used for shaping and buffering the driving signal.

5. The high voltage undervoltage detection circuit according to claim 1, characterized in that: The pull-up current control circuit comprises a first PMOS tube and a first NMOS tube, wherein the first NMOS tube is a deep N-well high-voltage thick-gate NMOS tube; The pull-down current control circuit includes a depletion-type MOS tube and a second NMOS tube; The voltage comparison circuit includes a second PMOS tube and a third NMOS tube; The drain and deep N-well of the first NMOS tube are both used to access the high-voltage signal to be detected, the gate of the first NMOS tube is used to access the preset high-voltage signal, the P-well and source of the first NMOS tube are both connected to the well and source of the first PMOS tube, the gate of the first PMOS tube is connected to the voltage-dividing sampling circuit, and the drain of the first PMOS tube is connected to the drain of the depletion-type MOS tube; The source of the depletion-type MOS tube is connected to the drain of the second NMOS tube, the gate of the second PMOS tube, and the gate of the third NMOS tube; the gate of the depletion-type MOS tube is connected to the gate of the second NMOS tube, the drain of the second PMOS tube, the drain of the third NMOS tube, and the output circuit; and the source of the second NMOS tube is grounded; The source of the second PMOS tube is connected to the power supply voltage, and the source of the third NMOS tube is grounded.

6. The high voltage undervoltage detection circuit according to claim 5, characterized in that: The high voltage undervoltage detection circuit also includes a reset circuit; The reset circuit includes a fourth NMOS tube; The drain of the fourth NMOS tube is connected to the source of the depletion-type MOS tube, the drain of the second NMOS tube, the gate of the second PMOS tube, and the gate of the third NMOS tube. The gate of the fourth NMOS tube is used to receive a first external trigger signal. The source of the fourth NMOS tube is grounded.

7. The high voltage undervoltage detection circuit according to claim 6, characterized in that: The high voltage undervoltage detection circuit also includes a node initialization circuit and a level conversion circuit; The pull-up current control circuit further includes a fifth NMOS tube; wherein the fifth NMOS tube is a deep N-well high-voltage thick-gate NMOS tube; The voltage comparison circuit also includes a third PMOS tube and a fourth PMOS tube; The node initialization circuit includes a first inverter, a first NAND gate, a sixth NMOS transistor and a fifth PMOS transistor; The level conversion circuit comprises a second inverter, a third inverter, a second NAND gate, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube; The P well and source of the first NMOS tube are connected to the drain of the fifth NMOS tube and the well of the first PMOS tube, the P well and source of the fifth NMOS tube are connected to the source of the first PMOS tube and the drain of the sixth NMOS tube, the gate of the fifth NMOS tube is connected to the drain of the eighth PMOS tube and the drain of the ninth NMOS tube, and the deep N well of the fifth NMOS tube is used to access the high voltage signal to be detected; The input end of the first inverter and the input end of the second inverter are both used to receive a second external trigger signal, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate, the second input end of the second NAND gate, the gate of the third PMOS tube, the drain of the second PMOS tube, the drain of the third NMOS tube, the gate of the fourth PMOS tube, the drain of the fifth PMOS tube, the gate of the second NMOS tube, and the gate of the depletion-type MOS tube are connected to each other, the output end of the first NAND gate is connected to the gate of the sixth NMOS tube, the source of the sixth NMOS tube is grounded, the source of the fifth PMOS tube is connected to the power supply voltage and the source of the fourth PMOS tube, and the gate of the fifth PMOS tube is used to receive the first external trigger signal; The drain of the fourth PMOS tube is connected to the drain of the first PMOS tube and the drain of the depletion-type MOS tube, the drain of the third PMOS tube is connected to the source of the depletion-type MOS tube, the drain of the second NMOS tube, the drain of the fourth NMOS tube, the gate of the second PMOS tube, and the gate of the fifth PMOS tube, and the source of the third PMOS tube is connected to the power supply voltage; The first input end of the second NAND gate is connected to the output end of the second inverter, the output end of the second NAND gate is connected to the gate of the seventh NMOS tube and the input end of the third inverter, the output end of the third inverter is connected to the gate of the eighth NMOS tube, the drain of the ninth NMOS is connected to the drain of the sixth PMOS tube and the gate of the seventh PMOS tube, the gate of the sixth PMOS tube, the drain of the seventh PMOS tube, the drain of the eighth NMOS tube, the gate of the eighth PMOS tube, and the gate of the ninth NMOS tube are connected to each other, the source of the sixth PMOS tube, the source of the seventh PMOS tube, and the source of the eighth PMOS tube are all used to access the high-voltage signal to be detected, and the source of the seventh NMOS tube, the source of the eighth NMOS tube, and the source of the ninth NMOS tube are all grounded.

8. The high voltage undervoltage detection circuit according to claim 7, characterized in that: The high voltage undervoltage detection circuit also includes a buffer circuit provided between the voltage comparison circuit and the output circuit; The buffer circuit includes a ninth PMOS tube, a tenth PMOS tube, a tenth NMOS tube and an eleventh NMOS tube; The source of the ninth PMOS tube and the source of the tenth PMOS tube are both connected to the power supply voltage, the gate of the ninth PMOS tube, the gate of the tenth NMOS tube, the gate of the third PMOS tube, the drain of the second PMOS tube, the drain of the third NMOS tube, the gate of the fourth PMOS tube, and the drain of the fifth PMOS tube are connected to each other, the drain of the ninth PMOS tube, the gate of the tenth PMOS tube, the drain of the tenth NMOS tube, and the gate of the eleventh NMOS tube are connected to each other, the drain of the tenth PMOS tube, the drain of the eleventh NMOS tube, the second input end of the first NAND gate, the second input end of the second NAND gate, the gate of the depletion-type MOS tube, the gate of the second NMOS tube, and the output circuit are connected to each other, and the source of the tenth NMOS tube and the source of the eleventh NMOS tube are both grounded.

9. The high voltage undervoltage detection circuit according to claim 5, characterized in that: The pull-up current control circuit further includes a twelfth NMOS tube; wherein the twelfth NMOS tube is a deep N-well high-voltage thick-gate NMOS tube; The pull-down current control circuit also includes a thirteenth NMOS tube; The drain, gate and deep N-well of the twelfth NMOS tube are all used to access the high-voltage signal to be detected, and the drain of the first NMOS tube is connected to the P-well and source of the twelfth NMOS tube; The source of the second NMOS tube is connected to the drain of the thirteenth NMOS tube, the gate of the thirteenth NMOS tube is connected to the gate of the depletion-type MOS tube, the gate of the second NMOS tube, and the output circuit, and the source of the thirteenth NMOS tube is grounded.

10. The high voltage undervoltage detection circuit according to any one of claims 5 to 9, characterized in that: The voltage-dividing sampling circuit comprises a resistance voltage-dividing sampling circuit; The resistor voltage-dividing sampling circuit comprises a first voltage-dividing resistor and a second voltage-dividing resistor, one end of the first voltage-dividing resistor is used to access the high-voltage signal to be detected, the other end of the first voltage-dividing resistor is connected to one end of the second voltage-dividing resistor and is connected to the pull-up current control circuit, and the other end of the second voltage-dividing resistor is grounded; or, The voltage-dividing sampling circuit comprises a MOS diode voltage-dividing sampling circuit; The MOS diode voltage division sampling circuit comprises a first voltage division sampling unit and a second voltage division sampling unit connected in sequence; The first voltage division sampling unit includes a first number of deep N-well high-voltage thick-gate NMOS transistors connected in sequence, and the second voltage division sampling unit includes a second number of deep N-well high-voltage thick-gate NMOS transistors connected in sequence; The connection method of the sequentially connected deep N-well high-voltage thick-gate NMOS tubes includes connecting the P-well and source of the previous deep N-well high-voltage thick-gate NMOS tube to the gate and drain of the next deep N-well high-voltage thick-gate NMOS tube; The gate and drain of the first deep N-well high-voltage thick-gate NMOS tube of the first voltage-dividing sampling unit are used to access the high-voltage signal to be detected, the p-well and source of the last deep N-well high-voltage thick-gate NMOS tube of the first voltage-dividing sampling unit are connected to the gate and drain of the first deep N-well high-voltage thick-gate NMOS tube of the second voltage-dividing sampling unit and are accessed to the pull-up current control circuit, and the p-well and source of the last deep N-well high-voltage thick-gate NMOS tube of the second voltage-dividing sampling unit are grounded.

11. A high voltage circuit, characterized in that: The high voltage circuit comprises the high voltage undervoltage detection circuit according to any one of claims 1 to 10.

12. The high voltage circuit according to claim 11, characterized in that: The high-voltage circuit also includes a first boost circuit, a second boost circuit, a high-voltage detection control circuit, a transmission power NMOS tube, a first high-voltage switch, a second high-voltage switch, a first voltage stabilizing capacitor, a second voltage stabilizing capacitor and a load circuit; The output end of the first boost circuit is connected to the first voltage stabilizing capacitor, the high voltage undervoltage detection circuit, and the gate of the transmission power NMOS tube via the first high voltage switch; The output end of the second boost circuit is connected to the high-voltage detection control circuit, and the output end of the second boost circuit is also connected to the second voltage stabilizing capacitor, the high-voltage undervoltage detection circuit, and the drain of the transmission power NMOS tube via the second high-voltage switch; The P well and source of the transmission power NMOS tube are connected to the load circuit; The high voltage detection control circuit is connected to the high voltage undervoltage detection circuit, the first boost circuit, and the second boost circuit; The high-voltage detection control circuit is used for triggering the first boost circuit and the second boost circuit to stop working in response to the high-voltage signal to be detected output by the second boost circuit reaching a target voltage value; The high-voltage detection control circuit is further used to receive a high-voltage under-voltage lockout signal output by the high-voltage under-voltage detection circuit, and trigger the first boost circuit and the second boost circuit to start working.

13. The high voltage circuit according to claim 12, characterized in that: The high voltage circuit also includes a leakage compensation circuit; The leakage compensation circuit is connected to the P well and source of the transmission power NMOS tube and the load circuit; The leakage compensation circuit is used to compensate for the channel leakage current of the transmission power NMOS tube.

14. A chip, characterized in that: The chip includes the high-voltage undervoltage detection circuit according to any one of claims 1-10, or the high-voltage circuit according to any one of claims 11-13.

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