Data transmission exception handling system based on AXI bus

Abstract

The invention provides a data transmission exception handling system based on an AXI bus, which comprises a master device and a slave device, and is characterized in that an upper software program runs on the master device; wherein the master device is used for sending an AXI write address and AXI write data to the slave device under the control of a data sending thread of an upper software program; the slave device writes AXI write data into the AXI write address, and an AXI write response is sent to the master device after the AXI write data of one data packet is processed every time; the AXI write response comprises error interrupt indication information; the main device is further used for interrupting a data sending thread of the upper-layer software program after receiving the error interruption indication information, and controlling the upper-layer software program to enter an interruption processing thread to respond to the error interruption indication information. According to the data transmission exception handling system based on the AXI bus provided by the invention, response can be carried out after one data packet fails to be written in, and the handling timeliness when the slave equipment returns the exception response is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data transmission exception processing system based on an AXI bus. Background Art

[0002] When transmitting data based on the AXI bus, the master device writes data to the slave device, and the slave device returns a write response signal. When the master device writes data to the slave device, it first sends the AXI write address and related control accompanying signals, and then sends the AXI write data and related control accompanying signals. According to the predetermined data length, after receiving multiple data packets, the slave device sends an AXI write response to the master device, indicating that the data is written successfully or unsuccessfully. In other words, the slave device checks whether the data is written successfully only after the overall data is written. The overall data consists of multiple data packets. When the amount of written data is large, it will delay the processing of abnormal situations. Summary of the invention

[0003] The present invention provides a data transmission exception processing system based on an AXI bus, which is used to solve the defect in the prior art that a slave device checks whether data is written successfully only after the entire data is written, and the entire data is composed of multiple data packets. When the amount of written data is large, the processing of the abnormal situation will be delayed, so as to improve the processing timeliness when the slave device returns an abnormal response.

[0004] The present invention provides a data transmission exception processing system based on an AXI bus, comprising: a master device and a slave device, wherein an upper-layer software program is running on the master device; wherein: the master device is used to send an AXI write address and AXI write data to the slave device under the control of a data sending thread of the upper-layer software program; the slave device is used to receive the AXI write address and the AXI write data, write the AXI write data to the AXI write address, and send an AXI write response to the master device after processing the AXI write data of each data packet; wherein the AXI write response includes error interrupt indication information; the master device is also used to interrupt the data sending thread of the upper-layer software program after receiving the error interrupt indication information, and control the upper-layer software program to enter an interrupt processing thread to respond to the error interrupt indication information.

[0005] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the error interrupt indication information includes an error interrupt type; when the interrupt processing thread is used to respond according to the error interrupt indication information, it is specifically used to: repeatedly send the data packet containing the error interrupt indication information, and count the distribution and occurrence frequency of the error interrupt type in the AXI write response received when the data packet is repeatedly sent.

[0006] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the interrupt processing thread is also used to provide corresponding solution prompt information according to the error interrupt type when the number of occurrences of the same error interrupt type is greater than a preset value.

[0007] According to a data transmission exception processing system based on an AXI bus provided by the present invention, the error interrupt types include slave device exception interrupts and slave device decoding exception interrupts; corresponding to the slave device exception interrupts, the solution prompt information includes resetting the slave device and / or increasing the bandwidth; corresponding to the slave device decoding exception interrupt, the solution prompt information includes detecting whether the slave device is in a working state and / or whether it is powered on.

[0008] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the interrupt processing thread is also used to provide prompt information of the alternating error interrupt types and the corresponding occurrence times when different error interrupt types appear alternately.

[0009] According to a data transmission exception handling system based on an AXI bus provided by the present invention, after receiving the AXI write response, the master device is also used to store the error interrupt indication information in a preset storage area; when the interrupt processing thread is used to respond to the error interrupt indication information, it is specifically used to: obtain the error interrupt indication information by querying the preset storage area, and respond according to the error interrupt indication information.

[0010] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the master device is further used to: determine the error interrupt enable status before interrupting the data sending thread of the upper-level software program, and interrupt the data sending thread of the upper-level software program when it is determined that the error interrupt is enabled.

[0011] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the master device is also used to: after receiving the AXI write response and when determining that the error interrupt is not enabled, continue the execution of the data sending thread of the upper-level software program.

[0012] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the AXI write response includes write success indication information; the master device is also used to continue the execution of the data sending thread of the upper-level software program after receiving the write success indication information.

[0013] According to a data transmission exception handling system based on an AXI bus provided by the present invention, after the master device is used to control the upper-layer software program to enter the interrupt processing thread to respond to the error interrupt indication information, it is also used to: control the upper-layer software program to jump out of the interrupt processing thread and continue the execution of the data sending thread.

[0014] The data transmission exception processing system based on AXI bus provided by the present invention comprises a master device and a slave device, an upper-layer software program is run on the master device, the master device is used to send AXI write address and AXI write data to the slave device under the control of the data sending thread of the upper-layer software program, the slave device is used to receive the AXI write address and AXI write data, write the AXI write data to the AXI write address, and send an AXI write response to the master device after processing the AXI write data of each data packet; wherein the AXI write response comprises error interrupt indication information, the master device is further used to interrupt the data sending thread of the upper-layer software program after receiving the error interrupt indication information, and control the upper-layer software program to enter the interrupt processing thread to respond to the error interrupt indication information, so as to realize responding after a data packet fails to be written, thereby improving the processing timeliness when the slave device returns an exception response. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 It is a structural schematic diagram of a data transmission exception processing system based on an AXI bus provided by the present invention.

[0017] Figure 2 It is a principle architecture diagram of the data transmission exception handling system based on AXI bus provided by the present invention.

[0018] Figure 3 The present invention provides a schematic diagram of the processing flow of the data transmission exception processing system based on the AXI bus. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] Figure 1 Schematic diagram of the structure of the data transmission exception handling system based on AXI bus provided by the present invention. Figure 1 As shown, the system includes: a master device 1 and a slave device 2, and an upper-layer software program is running on the master device 1; wherein: the master device 1 is used to send an AXI write address and an AXI write data to the slave device 2 under the control of the data sending thread of the upper-layer software program; the slave device 2 is used to receive the AXI write address and the AXI write data, write the AXI write data to the AXI write address, and send an AXI write response to the master device after processing the AXI write data of each data packet; wherein the AXI write response includes error interrupt indication information; the master device 1 is also used to interrupt the data sending thread of the upper-layer software program after receiving the error interrupt indication information, and control the upper-layer software program to enter the interrupt processing thread to respond to the error interrupt indication information.

[0021] AXI (Advanced eXtensible Interface) bus is a bus protocol and a new high-performance protocol in the Advanced Microcontroller Bus Architecture (AMBA). AXI technology enriches the existing AMBA standard content to meet the needs of ultra-high performance and complex system-on-chip (SoC) design.

[0022] The data transmission exception handling system based on AXI bus provided by the present invention comprises a master device 1 and a slave device 2, and the master device 1 and the slave device 2 perform data transmission based on the AXI bus. An upper-layer software program runs on the master device 1, and the upper-layer software program can realize a user interaction function. An implementation structure of the master device 1 can include a CPU and an AXI module, wherein the upper-layer software program runs on the CPU.

[0023] The master device 1 is used to send the AXI write address and AXI write data to the slave device under the control of the data sending thread of the upper-level software program. When the AXI master device initiates a write data request to the AXI slave device, it first sends the AXI write address, then sends the AXI write data, and then waits to receive the AXI write response signal returned by the slave device 2. Among them, the AXI write address refers to the data write address, and the AXI write data refers to the specific data to be written. AXI write data is transmitted and written in data packets. Slave device 2 is used to receive the AXI write address and AXI write data, write the AXI write data to the AXI write address, and send an AXI write response to the master device after processing the AXI write data of each data packet; wherein, the AXI write response includes error interrupt indication information, and the error interrupt indication information indicates that an error interrupt has occurred, that is, the data packet write fails.

[0024] The master device 1 is also used to generate an error interrupt signal after receiving the error interrupt indication information, and initiate an interrupt signal to the upper-level software program to interrupt the data sending thread of the upper-level software program, and control the upper-level software program to enter the interrupt processing thread to respond to the error interrupt indication information, thereby realizing a timely response to the write failure.

[0025] In addition to the upper-layer software program, the functional modules of the master device 1 and the slave device 2 can be implemented as hardware modules converted from the Verilog descriptive language. Verilog is a hardware description language that describes the structure and behavior of digital system hardware in text form. It can be used to represent logic circuit diagrams, logic expressions, and logic functions performed by digital logic systems. By using the Verilog language to independently design relevant functional codes and convert them into hardware circuits, security and flexibility are improved.

[0026] The data transmission exception processing system based on AXI bus provided by the present invention comprises a master device and a slave device, an upper-layer software program is run on the master device, the master device is used to send AXI write address and AXI write data to the slave device under the control of the data sending thread of the upper-layer software program, the slave device is used to receive the AXI write address and AXI write data, write the AXI write data to the AXI write address, and send an AXI write response to the master device after processing the AXI write data of each data packet; wherein the AXI write response comprises error interrupt indication information, the master device is further used to interrupt the data sending thread of the upper-layer software program after receiving the error interrupt indication information, and control the upper-layer software program to enter the interrupt processing thread to respond to the error interrupt indication information, so as to realize responding after a data packet fails to be written, thereby improving the processing timeliness when the slave device returns an exception response.

[0027] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the error interrupt indication information includes an error interrupt type; when the interrupt processing thread is used to respond according to the error interrupt indication information, it is specifically used to: repeatedly send the data packet containing the error interrupt indication information, and count the distribution and occurrence frequency of the error interrupt type in the AXI write response received when the data packet is repeatedly sent.

[0028] The error interrupt indication information includes an error interrupt type, and the error interrupt type indicates the error type of the write failure. When the interrupt processing thread is used to respond according to the error interrupt indication information, it is specifically used to: repeatedly send data packets with error interrupt indication information, and count the distribution and occurrence times of error interrupt types in the AXI write responses received when the data packets are repeatedly sent. Among them, when the data packets with error interrupt indication information are repeatedly sent, the received AXI write response may contain error interrupt indication information, and the error interrupt indication information may include the same error interrupt type or different error interrupt types; it may also be written normally, and the AXI write response does not contain the error interrupt indication information. When writing normally, subsequent data packets can continue to be sent. According to the error interrupt types in the AXI write responses received when the data packets with error interrupt indication information are repeatedly sent, the distribution and occurrence times of the error interrupt types are obtained, that is, the types of error interrupt types that appear and the occurrence times of each error interrupt type.

[0029] The data transmission exception processing system based on the AXI bus provided by the present invention improves the reliability of exception identification and facilitates the provision of targeted solutions by repeatedly sending data packets with error interrupt indication information and counting the distribution and occurrence times of error interrupt types in AXI write responses received when the data packets are repeatedly sent.

[0030] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the interrupt processing thread is also used to provide corresponding solution prompt information according to the error interrupt type when the number of occurrences of the same error interrupt type is greater than a preset value.

[0031] According to the distribution and occurrence frequency of the obtained error interrupt types, if the occurrence frequency of the same error interrupt type is greater than the preset value, it means that the error interrupt type is repeated and occurs frequently, and the error interrupt type needs to be processed, and the corresponding solution prompt information is given according to the error interrupt type.

[0032] The data transmission exception processing system based on the AXI bus provided by the present invention improves the reliability of exception processing and the accuracy of the solution by giving corresponding solution prompt information according to the error interrupt type when the number of occurrences of the same error interrupt type is greater than a preset value.

[0033] According to a data transmission exception processing system based on an AXI bus provided by the present invention, the error interrupt types include slave device exception interrupts and slave device decoding exception interrupts; corresponding to the slave device exception interrupts, the solution prompt information includes resetting the slave device and / or increasing the bandwidth; corresponding to the slave device decoding exception interrupt, the solution prompt information includes detecting whether the slave device is in a working state and / or whether it is powered on.

[0034] The error interrupt type can be represented by a binary number. For example, when the AXI write response signal is binary 10, it indicates a slave device exception, such as cache out-of-bounds, timeout, and other exceptions; when the AXI write response signal is binary 11, it indicates a decoder exception, indicating that the accessed slave device does not exist.

[0035] Therefore, the error interrupt type includes slave device abnormal interrupt and slave device decoding abnormal interrupt. For slave device abnormal interrupt, the solution prompt information may include resetting the slave device and / or increasing the bandwidth. You can try to reset the slave, or analyze whether the abnormality is caused by bandwidth limitation, and increase the bandwidth; for slave device decoding abnormal interrupt, the solution prompt information may include checking whether the slave device is in working state and whether it is powered on.

[0036] The types of interrupts can be expanded and corresponding solution prompt information can be set according to the actual application scenarios.

[0037] The data transmission exception processing system based on the AXI bus provided by the present invention further improves the reliability of exception processing and the accuracy of the solution by corresponding to the abnormal interruption of the slave device, and the solution prompt information includes resetting the slave device and / or increasing the bandwidth, and corresponding to the abnormal interruption of the slave device decoding, and the solution prompt information includes detecting whether the slave device is in a working state and / or whether it is powered on.

[0038] According to a data transmission exception processing system based on an AXI bus provided by the present invention, the interrupt processing thread is also used to provide prompt information of the alternating error interrupt types and the corresponding occurrence times when different error interrupt types appear alternately.

[0039] If after repeatedly sending data packets, different error interrupt types are found to appear alternately based on the obtained AXI write response, the interrupt processing thread provides prompt information of the alternating error interrupt types and the corresponding number of occurrences to the user, so that the user can specifically analyze the complex scenario and troubleshoot the unstable factors and abnormal causes.

[0040] The data transmission exception processing system based on the AXI bus provided by the present invention further improves the reliability of exception processing by providing prompt information of the alternating error interrupt types and the corresponding occurrence times when different error interrupt types alternately occur.

[0041] According to a data transmission exception handling system based on an AXI bus provided by the present invention, after receiving the AXI write response, the master device 1 is also used to store the error interrupt indication information in a preset storage area; when the interrupt processing thread is used to respond to the error interrupt indication information, it is specifically used to: obtain the error interrupt indication information by querying the preset storage area, and respond according to the error interrupt indication information.

[0042] After receiving the AXI write response, the master device 1 is also used to store the error interrupt indication information in a preset storage area. The preset storage area can be a register or an external memory. When the interrupt processing thread is used to respond to the error interrupt indication information, it obtains the error interrupt indication information by querying the preset storage area and responds according to the error interrupt indication information.

[0043] The data transmission exception processing system based on the AXI bus provided by the present invention facilitates the acquisition of the error interrupt indication information by storing the error interrupt indication information in a preset storage area, obtaining the error interrupt indication information by querying the preset storage area, and responding according to the error interrupt indication information.

[0044] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the master device 1 is further used to: determine the error interrupt enable status before interrupting the data sending thread of the upper-layer software program, and interrupt the data sending thread of the upper-layer software program when it is determined that the error interrupt is enabled.

[0045] The error interrupt enable configuration function can be set, and the upper-layer software program can configure the error interrupt enable status, so that the error interrupt corresponding to the master device 1 is enabled or disabled. The error interrupt corresponding to the master device 1 is enabled, which means that if the write response sent by the slave device 2 connected to the master device 1 includes the error interrupt indication information, the data sending thread of the upper-layer software program is interrupted and the interrupt processing flow is entered. The error interrupt corresponding to the master device 1 is not enabled, which means that if the write response sent by the slave device 2 connected to the master device 1 includes the error interrupt indication information, the data sending thread of the upper-layer software program is not interrupted and the interrupt processing flow is not entered.

[0046] Before interrupting the data sending thread of the upper-layer software program, the master device 1 determines whether the error interrupt is enabled, and interrupts the data sending thread of the upper-layer software program if it is determined that the error interrupt is enabled.

[0047] The data transmission exception processing system based on AXI bus provided by the present invention judges the error interrupt enable status before interrupting the data sending thread of the upper software program, and interrupts the data sending thread of the upper software program when it is determined that the error interrupt is enabled, and improves the control flexibility by setting the error interrupt enable configuration function.

[0048] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the master device is also used to: after receiving the AXI write response and when determining that the error interrupt is not enabled, continue the execution of the data sending thread of the upper-level software program.

[0049] After receiving the AXI write response, the master device 1 determines whether the error interrupt is enabled. If it is determined that the error interrupt is not enabled, it does not interrupt the data sending thread of the upper-level software program, nor does it enter the interrupt processing thread, and continues the execution of the data sending thread of the upper-level software program.

[0050] The data transmission exception processing system based on the AXI bus provided by the present invention improves flexibility by continuing the execution of the data sending thread of the upper-layer software program after receiving the AXI write response and determining that the error interrupt is not enabled.

[0051] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the AXI write response includes write success indication information; the master device is also used to continue the execution of the data sending thread of the upper-level software program after receiving the write success indication information.

[0052] The AXI write response includes write success indication information, for example, when the AXI write response is binary 00, it indicates that the host successfully writes data to the slave; when the AXI write response signal is binary 01, it indicates that the exclusive access is successful. Master device 1 is also used to continue the execution of the data transmission thread of the upper-layer software program after receiving the write success indication information, that is, to perform normal data packet transmission.

[0053] The data transmission exception processing system based on the AXI bus provided by the present invention ensures smooth data transmission by continuing the execution of the data sending thread of the upper-layer software program after receiving the write success indication information.

[0054] According to a data transmission exception handling system based on an AXI bus provided by the present invention, the master device 1 is used to control the upper-layer software program to enter the interrupt processing thread to respond to the error interrupt indication information, and is also used to: control the upper-layer software program to jump out of the interrupt processing thread and continue the execution of the data sending thread.

[0055] After the master device 1 controls the upper-layer software program to enter the interrupt processing thread to respond to the error interrupt indication information, it indicates that the response to the write failure of the current data packet is completed, and the subsequent data packet sending process can be performed. Therefore, after the master device 1 controls the upper-layer software program to enter the interrupt processing thread to respond to the error interrupt indication information, it jumps out of the interrupt processing thread and continues the execution of the data sending thread of the upper-layer software program.

[0056] The data transmission exception processing system based on the AXI bus provided by the present invention ensures smooth data transmission by jumping out of the interrupt processing thread and continuing the execution of the data sending thread of the upper-layer software program after the upper-layer software program is controlled to enter the interrupt processing thread to respond to the error interrupt indication information.

[0057] Figure 2 It is a principle architecture diagram of the data transmission exception handling system based on AXI bus provided by the present invention.

[0058] Figure 3 The present invention provides a schematic diagram of the processing flow of the data transmission exception processing system based on the AXI bus.

[0059] Combine the following Figure 2 and Figure 3 The functions of the data transmission exception processing system based on the AXI bus provided by the present invention are further introduced.

[0060] 1. Communication method between master device and slave device

[0061] Data is transmitted between the master device and the slave device via the AXI bus. When the data is ready, the master device sends the AXI write address and AXI write data to the slave device. After receiving the data, the slave device returns an AXI write response signal.

[0062] 2. AXI write response judgment

[0063] (1) After receiving the AXI write response signal, the master device judges the signal content. If the AXI write response is binary 00, indicating that the data is written successfully, then the data communication continues; if the AXI write response signal is binary 10, indicating that the slave device is abnormal, then an exception interrupt is sent to the upper-level software program, and the exception information is sent to the upper-level software program; if the AXI write response signal is binary 11, indicating that the decoder is abnormal, indicating that the accessed slave device does not exist, then an exception interrupt is sent to the upper-level software program, and the exception information is sent to the upper-level software program.

[0064] (2) Set the error interrupt type, error interrupt enable, and error interrupt signal. Set the error interrupt type according to the exception type of the AXI write response signal. When the AXI write response signal is binary 10, the slave device exception indicates a slave device exception error interrupt. When the AXI write response signal is binary 11, the decoder exception indicates a slave device decoding exception interrupt. In addition, the types of interrupts can be expanded according to the actual application scenarios. 3. Upper-level software program

[0065] After the upper-level software program reads the error interrupt type, it gives different solutions for different error interrupts. On the one hand, the software will automatically try to resend the data packet. If the retransmission is successful, it will continue to transmit. If the transmission fails, the error interrupt will be received again. The software counts the number of interrupts and presents each error type to the user. The user can observe whether the error interrupt type has changed. If the interrupt type has not changed, after retransmitting the data many times, if a certain error interrupt is always generated and its count is greater than a certain set value, the user can try various solutions based on the result. For example, for the abnormal error interrupt of the slave device, you can try to reset the slave, or analyze whether the abnormality is caused by bandwidth limitation, and increase the bandwidth. If it indicates an abnormal decoding interrupt of the slave device, you need to check whether the slave is in working state and whether it is powered on. If the interrupt type changes during repeated transmission, it is necessary to analyze the complex scenario in detail to troubleshoot the unstable factors and the causes of the abnormality.

[0066] The data transmission exception processing system based on AXI bus provided by the present invention, in the data transmission process based on AXI bus protocol, the master device writes data to the slave device, and the slave device returns an AXI write response signal. When the master device receives the AXI write response signal, the signal is immediately judged. If an abnormal situation is indicated, an abnormal interrupt is sent to the upper software program, and data transmission is suspended. The AXI write response includes an error interrupt type, and the upper software program provides an abnormal solution according to the error interrupt type. The method avoids the situation where the abnormal response is not processed in time when the slave device returns it, and provides the error interrupt type, so that the upper software program provides a more targeted solution. In addition, when the write response signal returned by the slave device indicates that the data is not successfully written, the write response signal indicating the abnormality is processed according to the situation, and a solution is provided in time.

[0067] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0068] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data transmission exception handling system based on AXI bus, characterized in that: include: A master device and a slave device, wherein an upper layer software program is running on the master device; wherein: The master device is used to send the AXI write address and AXI write data to the slave device under the control of the data sending thread of the upper-layer software program; The slave device is used to receive the AXI write address and the AXI write data, write the AXI write data to the AXI write address, and send an AXI write response to the master device after processing the AXI write data of each data packet; wherein the AXI write response includes error interrupt indication information; The master device is further configured to interrupt the data sending thread of the upper-layer software program after receiving the error interrupt indication information, and control the upper-layer software program to enter an interrupt processing thread to respond to the error interrupt indication information.

2. The data transmission exception handling system based on AXI bus according to claim 1, characterized in that: The error interrupt indication information includes an error interrupt type; when the interrupt processing thread is used to respond according to the error interrupt indication information, it is specifically used to: Repeatingly sending the data packet with error interrupt indication information, and counting the distribution and occurrence times of the error interrupt type in the AXI write response received when repeatedly sending the data packet.

3. The data transmission exception handling system based on AXI bus according to claim 2 is characterized in that: The interrupt processing thread is further used to provide corresponding solution prompt information according to the error interrupt type when the number of occurrences of the same error interrupt type is greater than a preset value.

4. The data transmission exception handling system based on AXI bus according to claim 3 is characterized in that: The error interrupt type includes a slave device abnormal interrupt and a slave device decoding abnormal interrupt; In response to the abnormal interruption of the slave device, the solution prompt information includes resetting the slave device and / or increasing the bandwidth; Corresponding to the abnormal decoding interruption of the slave device, the solution prompt information includes detecting whether the slave device is in a working state and / or is powered on.

5. The data transmission exception handling system based on AXI bus according to claim 2, characterized in that: The interrupt processing thread is also used to provide prompt information of the alternating erroneous interrupt types and the corresponding occurrence times when different erroneous interrupt types appear alternately.

6. The data transmission exception handling system based on AXI bus according to claim 1, characterized in that: After receiving the AXI write response, the master device is further used to store the error interrupt indication information in a preset storage area; When the interrupt processing thread is used to respond to the error interrupt indication information, it is specifically used to: obtain the error interrupt indication information by querying the preset storage area, and respond according to the error interrupt indication information.

7. The data transmission exception handling system based on AXI bus according to claim 1, characterized in that: Before being used to interrupt the data sending thread of the upper-layer software program, the master device is further used to: determine whether the error interrupt is enabled, and interrupt the data sending thread of the upper-layer software program if it is determined that the error interrupt is enabled.

8. The data transmission exception handling system based on AXI bus according to claim 7, characterized in that: The master device is further configured to: after receiving the AXI write response and in the case where it is determined that the error interrupt is not enabled, continue the execution of the data sending thread of the upper-layer software program.

9. The data transmission exception handling system based on AXI bus according to claim 1, characterized in that: The AXI write response includes write success indication information; The master device is further configured to continue execution of the data sending thread of the upper-layer software program after receiving the write success indication information.

10. The data transmission exception handling system based on AXI bus according to claim 1, characterized in that: After being used to control the upper layer software program to enter the interrupt processing thread to respond to the error interrupt indication information, the master device is further used to: The upper-layer software program is controlled to exit the interrupt processing thread and continue the execution of the data sending thread.

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