A Channel Synchronous Switching Method for Large-Scale Matrix Switches Based on Asynchronous Bus

Abstract

The present invention relates to a channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus. An OR-NOT gate is added to the control circuit of the matrix board to construct an RS422 bus and an SPI hardware bus circuit including synchronous switching control enabling. The matrix device sends I / O data to the matrix board through the RS422 bus, and the matrix board receives the I / O data. The matrix device sends a "switching preparation" / "synchronous switching" instruction through the RS422 bus, and the matrix board turns on the synchronous switching control enabling or the matrix board turns off the synchronous switching control enabling. By adding special logic control and using the rising edge of the start bit of the serial RS422 bus data in cooperation with the synchronous switching control enabling, the synchronous switching of the switches of multiple matrix boards under multiple asynchronous microprocessors is realized, the routing switching time of the large-scale matrix is increased from the microsecond level to the nanosecond level, and when the large-scale matrix switch performs channel routing switching, the signal reception and demodulation are not affected, and the channels are lossless and insensitive.

Description

Technical Field

[0001] The present invention belongs to the technical field of large-scale radio frequency signal splitting and switching and synchronous control of microwave switch circuits, and particularly relates to a method for synchronous channel switching in a large-scale matrix switch based on an asynchronous bus. Background Art

[0002] A large-scale radio frequency switch matrix is composed of dozens of small and medium-sized matrix boards. Each matrix board includes multiple switches and power splitting units that can absorb and turn off. There are a large number of switch circuits, and each switch requires one or more I / O controls. For an M×N matrix board, at least 2*M×N I / O controls are required. If a 16×16 board is used to build the matrix, the number of boards and I / O is as shown in the following table:

[0003] Serial number Matrix scale Number of boards Number of I / O 1 64×64 12 3072 2 128×128 24 6144 3 256×256 48 9216

[0004] Since the I / O of a single-chip microcomputer is limited, in the prior art, a serial-to-parallel chip needs to be extended for SPI serial control, which only requires 3 control lines, namely data DATA, clock CLK, and enable EN. Through serial data input, after the data input is completed, the enable is triggered once to flip and latch simultaneously.

[0005] Inside the matrix board, through the serial data DATA and the clock CLK, the I / O data is shifted bit by bit into the memories of all serial-to-parallel chips. The enable EN is set to high level, and at the same time, the I / O data in the memories is flipped and output to achieve synchronous switching of each switch. For a large-scale matrix, multiple matrix boards are required, and RS422 bus is used for control. The main microprocessor of the whole machine sends the I / O data of all boards to each board respectively through the RS422 bus. The microprocessor of the board sends the I / O data of this board to the serial-to-parallel memory through SPI in sequence, but does not flip immediately. After receiving the synchronous switching instruction sent by the matrix main control microprocessor, the enable EN is flipped to achieve synchronous switching of all switches in the whole machine.

[0006] In the above synchronous switching method, due to the asynchronous clocks of the microprocessors of each board, the interrupts received by the serial port RX and the timing of executing the interrupts are different, and the synchronous error is about 5 us ~10 us . For the complete channels of a plug-in radio frequency matrix, when the routing changes, multiple boards are involved. The switching synchronous time error causes a signal interruption of 5 us ~10 us , which will cause the loss of one or more code elements or even signal unlocking when receiving high-speed modulated signals on this channel.

[0007] Therefore, how to improve the large-scale radio frequency signal splitting and switching and the synchronous switching method of microwave switch circuits in the prior art, to achieve the synchronous switching of switches of multiple matrix boards under multiple asynchronous microprocessors, and to increase the routing switching time of a large-scale matrix from the microsecond level to the nanosecond level. Thus, to achieve the routing switching of established channels, and the signal reception and demodulation channels are lossless and insensitive, is a technical problem that urgently needs to be solved at present. Summary of the Invention

[0008] The purpose of the present invention is to provide a channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus, which improves the large-scale radio frequency signal splitting and switching and the synchronous switching method of microwave switch circuits in the prior art, realizes the synchronous switching of switches of multiple matrix boards under multiple asynchronous microprocessors, increases the routing switching time of a large-scale matrix from the microsecond level to the nanosecond level. Thus, to achieve the routing switching of established channels, and the signal reception and demodulation channels are lossless and insensitive.

[0009] To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0010] A channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus includes the following steps:

[0011] S1: In the control circuit of the matrix board, add a NOR logic control unit to construct an RS422 bus and an SPI hardware bus circuit including synchronous switching control enabling.

[0012] S2: The matrix device sends I / O data to the matrix board through the RS422 bus. The matrix board receives the I / O data and forwards it to the serial-to-parallel conversion chip for storage through the SPI.

[0013] S3: The matrix device sends a "switching preparation" instruction through the RS422 bus. After receiving the command, the matrix board turns on the synchronous switching control enabling switch.

[0014] S4: The matrix device sends a "synchronous switching" instruction through the RS422 bus. By using the rising edge of the start bit of the serial RS422 bus data, the I / O of all HC595 chips of all boards is synchronously flipped. After receiving the command, the matrix board turns off the synchronous switching control enabling switch.

[0015] Preferably, the control circuit of the matrix board with an added NOR gate in step S1 includes a board microprocessor, a serial-to-parallel converter chip, a serial port chip, and an RS422 bus. There are several serial-to-parallel converter chips. The board microprocessor is connected to several serial-to-parallel converter chips, and the board microprocessor is also connected to the serial port chip. The NOR gate is respectively connected to the board microprocessor, the serial-to-parallel converter chip, and the serial port chip. The RS422 bus is connected to the serial port chip. The model of the serial-to-parallel converter chip is HC595.

[0016] Preferably, in the control circuit of the matrix board, when the enable EN’ = 1, the RX change generated by the RS422 bus data occurs, and the enable EN is always 0, which will not cause the stored data of the HC595 chip to flip to the output. When the enable EN’ = 0, for the RX generated by the RS422 bus data, as long as RX = 0, then the enable EN = 1, and the stored data of the serial-to-parallel converter chip HC595 chip flips to the output.

[0017] Preferably, when the matrix is a large-scale matrix, its plug-in card matrix bus control circuit includes a matrix board, a serial port chip, a whole machine microprocessor, and a network port chip. The network port chip is connected to the whole machine microprocessor, the whole machine microprocessor is connected to the serial port chip. There are several matrix boards, and the serial port chip is respectively connected to several matrix boards through the RS422 bus.

[0018] Preferably, the specific process of step S2 is as follows:

[0019] S21: When the matrix needs to perform a routing switch, screen and find the matrix boards that need to change the I / O. Through the RS422 bus, sequentially send I / O control data to the matrix boards that need to change the I / O, and determine whether I / O control data has been sent to all matrix boards. If so, execute step S22; if not, continue to send I / O control data to the remaining matrix boards that need to change the I / O through the RS422 bus in sequence;

[0020] S22: Send a "switch preparation" instruction to all matrix boards, and after a specified delay, send a "synchronous switch" instruction to all matrix boards again.

[0021] Preferably, step S3 includes the following specific process:

[0022] S31: Start the matrix board program, set the enable EN’ = 1, and loop to receive the instructions of the RS422 bus, and determine the type of the instructions received by the matrix board. If the type of the instructions received by the matrix board is an "I / O data" instruction, execute step S32; if the type of the instructions received by the matrix board is a "switch preparation" instruction, execute step S33; if the type of the instructions received by the matrix board is a "synchronous switch" instruction, execute step S34;

[0023] S32: Send I / O data to the serial-to-parallel conversion chip via SPI;

[0024] S33: Set the enable EN' to 0;

[0025] S34: Set the enable EN' to 1.

[0026] Preferably, during the period when the enable EN' of the matrix board is 0, when the first 0 of RX appears, which is the start bit in the serial protocol, the stored I / O data of the serial-to-parallel conversion chip HC595 immediately flips and outputs. When the I / O data has no change, the switch has no switching action, and the signal is not interrupted;

[0027] When the I / O data has a change and the switch has a switching action, all the switches that need to be switched on all matrix boards synchronously act, and the channel signal has a process of gradually disappearing and then gradually reappearing. The time of this process depends on the switching time of the RF switch chip and is 50 - 150 ns.

[0028] Preferably, the NOR gate logic control unit is a multi-input NOR gate logic control unit, including multiple input terminals and 1 output terminal.

[0029] Preferably, when all the inputs of multiple input terminals are low level, the output terminal outputs high level 1; when the input of one of the multiple input terminals is high level, the output terminal outputs low level 0.

[0030] The beneficial effects of the present invention include:

[0031] The channel synchronous switching method based on the asynchronous bus in the large-scale matrix switch provided by the present invention first adds a NOR gate logic control unit in the control circuit of the matrix board to construct an RS422 bus and an SPI hardware bus circuit including synchronous switching control enable; the matrix device sends I / O data to the matrix board via the RS422 bus, the matrix board receives the I / O data and forwards it to the serial-to-parallel conversion chip for storage via SPI; the matrix device sends a "switching preparation" instruction via the RS422 bus, and after receiving the command, the matrix board turns on the synchronous switching control enable switch; the matrix device sends a "synchronous switching" instruction via the RS422 bus, and uses the rising edge of the start bit of the serial RS422 bus data to realize the synchronous flipping of the I / O of all HC595 chips on all boards. After receiving the command, the matrix board turns off the synchronous switching control enable switch.

[0032] By adding special logic control, the rising edge of the start bit of the serial RS422 bus data and the synchronization switching instruction are used to enable collaborative control, realizing the synchronous switching of the switches of multiple matrix boards under multiple asynchronous microprocessors, improving the routing switching time of the large-scale matrix from the microsecond level to the nanosecond level, and further realizing the routing switching of the established channels, with the signal receiving and demodulating channels being lossless and insensitive. Description of the Drawings

[0033] Figure 1 Schematic diagram of the internal I / O expansion control circuit of the matrix board in the prior art of the present invention.

[0034] Figure 2 Schematic diagram of the plug-in card matrix bus control circuit in the prior art of the present invention.

[0035] Figure 3 Schematic diagram of the internal I / O expansion control circuit of the matrix board with added NOR gate logic control of the present invention.

[0036] Figure 4 Schematic diagram of the plug-in card matrix synchronous switching process of the present invention.

[0037] Figure 5 Schematic diagram of the matrix board synchronous switching process of the present invention. Detailed Description of the Invention

[0038] The following will further elaborate on the present invention in conjunction with the attached Figures 1 - 5 For a more detailed description of the present invention:

[0039] Embodiment 1

[0040] A method for channel synchronous switching in a large-scale matrix switch based on an asynchronous bus, characterized by comprising the following steps:

[0041] S1: In the control circuit of the matrix board, add a NOR gate logic control unit, that is, add special logic control to the control circuit of the matrix board, construct a serial RS422 bus and an SPI hardware bus circuit including synchronous switching control enabling, and use the rising edge of the start bit of the serial RS422 bus data and the synchronous switching instruction to enable collaborative control;

[0042] S2: When the matrix device needs to perform routing switching, screen and find the matrix boards that need to change I / O data. The matrix device sequentially sends I / O data to all matrix boards through the RS422 bus. The matrix boards receive the I / O data and forward it to the serial-to-parallel conversion chip through the SPI for storage;

[0043] S3: After the I / O data is sent, the matrix device sends a "switching preparation" command through the RS422 bus. After receiving the command, the matrix board turns on the synchronous switching control enable switch;

[0044] S4: The matrix device sends a "synchronous switching" command through the RS422 bus, and uses the rising edge of the start bit of the serial RS422 bus data to achieve synchronous flipping of the I / O of all HC595 chips on all boards, and realize the synchronous switching of multiple matrix boards under multiple asynchronous microprocessors, which increases the routing switching time of large-scale matrices from the us level to the ns level, thereby achieving routing switching of established channels, and signal reception and demodulation channels are lossless and insensitive. After receiving the command, the matrix board turns off the synchronous switching control enable switch.

[0045] Since in the prior art, see Figure 1 , inside the matrix board, through the serial data DATA and the clock CLK, the I / O data is shifted to the memory of all serial-to-parallel chips one by one, and the enable EN is controlled to be high level, and the I / O data in the memory is flipped and output at the same time, so as to realize the synchronous switching of each switch. The whole machine microprocessor sends the I / O data of all boards to each board through the RS422 bus. The board microprocessor sends the I / O data of the board to the serial-to-parallel memory through SPI in sequence, but does not flip it immediately. After receiving the synchronous switching instruction sent by the matrix master microprocessor, the enable EN is controlled to flip, so as to realize the synchronous switching of all switches of the whole machine. This synchronous switching mode has a synchronization error of about 5us to 10us because the clocks of the microprocessors of each board are not synchronized, and the timing of receiving the interrupt of the serial port RX and executing the interrupt is different. When the routing of the complete channel of the plug-in RF matrix is changed, multiple boards are involved. The switching synchronization time error causes the signal to be interrupted by 5us to 10us, which will cause the channel to lose one or more code elements when receiving high-speed modulation signals, or even signal lock. For example, when the signal modulation rate is R(Bd), the symbol time T(s) is:

[0046]

[0047] The symbol time of different modulation rates is as follows:

[0048] Modulation rate (MBd) 0.1 1 10 20 Symbol time T (ns) 10000 1000 100 50 Symbol time T (us) 10 1 0.1 0.05

[0049] The signal interruption time causes the number of lost symbols of signals with different modulation rates to be as follows:

[0050]

[0051] It can be seen from the above table that for signals with a rate above 1MBd, hundreds of code elements are lost, which may even cause demodulation lock loss.

[0052] Therefore, in this embodiment, by adding special NOR gate logic control to the control circuit of the matrix board, and using the rising edge of the start bit of the serial RS422 bus data and the synchronization switching instruction to enable collaborative control, the synchronous switching of the switches of multiple matrix boards under multiple asynchronous microprocessors is realized. The routing switching time of the large-scale matrix is increased from the microsecond level to the nanosecond level. When realizing the routing switching of the large-scale matrix, the signal interruption time is about 50 ns to 150 ns, and the specific time depends on the switching time of the RF switch chip, which is increased by about 100 times. Thus, it is possible to achieve that there is no loss of 0 symbols of the modulated signal below 10 M baud in the reception demodulation during the routing switching, and to realize the routing switching of the established channels, and the signal reception demodulation channel is lossless and insensitive.

[0053] Among them, the NOR gate logic control unit is a multi-input NOR gate logic control unit, including multiple input terminals and 1 output terminal. When all the inputs of the multiple input terminals are low levels, the output terminal outputs a high level 1; when the input of one of the multiple input terminals is a high level, the output terminal outputs a low level 0.

[0054] Embodiment 2

[0055] Refer to Figure 3 , on the basis of Embodiment 1, in the control circuit of the matrix board in step S1, a control circuit of the matrix board with NOR gate logic control is added. The control circuit of the matrix board includes a board microprocessor, a serial-to-parallel converter chip, a serial port chip, and an RS422 bus. There are several serial-to-parallel converter chips, and the model of the serial-to-parallel converter chip is HC595. The board microprocessor is connected to several serial-to-parallel converter chips through serial data DATA and clock CLK. The signal input terminal of the board microprocessor is connected to the signal output terminal of the serial port chip. The logic control unit of the NOR gate is respectively connected to the board microprocessor, the serial-to-parallel converter chip, and the serial port chip. The RS422 bus is connected to the serial port chip. Inside the matrix board, through the serial data DATA and the clock CLK, the I / O data is successively shifted into the memories of all the serial-to-parallel converter chips, the control enable EN is set to a high level, and at the same time, the I / O data in the memory is inverted and output. By adding special logic control to the control circuit of the matrix board, and using the rising edge of the start bit of the serial RS422 bus data and the synchronization switching instruction to enable collaborative control, the synchronous switching of the switches of multiple matrix boards under multiple asynchronous microprocessors is realized, and the synchronous switching of each switch is realized.

[0056] In the control circuit of the matrix board, when the enable EN’ = 1, the change of RX generated by the RS422 bus data makes the enable EN always 0, and the stored data of the HC595 chip will not be flipped to the output; when the enable EN’ = 0, for the RX generated by the RS422 bus data, as long as RX = 0, then the enable EN = 1, and the stored data of the serial-to-parallel chip HC595 is flipped to the output.

[0057] The logical relationship of the control circuit of the matrix board is shown in the following table:

[0058] Serial number EN’ RX EN 1 1 x 0 2 0 1 0 3 0 0 1

[0059] It can be seen from the above table that when EN’ = 1, regardless of whether RX is 0 or 1, the value of EN is 0; when EN’ = 0, EN = / RX. The function realized by the control circuit of this matrix board is: when EN’ = 1, for the change of RX generated by the RS422 bus data, EN is always 0, and the stored data of the HC595 chip will not be flipped to the output; when EN’ = 0, for the RX generated by the RS422 bus data, as long as RX = 0, then EN = 1, and the stored data of the HC595 chip is flipped to the output.

[0060] When the matrix is a large-scale matrix, refer to Figure 2 , its plug-in card matrix bus control circuit includes a matrix board, a serial port chip, a whole machine microprocessor, and a network port chip. The network port chip is connected to the whole machine microprocessor, the whole machine microprocessor is connected to the serial port chip, there are several matrix boards, and the serial port chip is respectively connected to several matrix boards through the RS422 bus.

[0061] Embodiment 3

[0062] Refer to Figure 4 , on the basis of Embodiment 1, the specific process of step S2 is as follows:

[0063] S21: When the matrix needs to perform routing switching, screen and find the matrix boards that need to change I / O, and sequentially send I / O control data to the matrix boards that need to change I / O through the RS422 bus, and determine whether I / O control data has been sent to all matrix boards. If so, execute step S22; if not, continue to sequentially send I / O control data to the remaining matrix boards that need to change I / O through the RS422 bus;

[0064] S22: Send a "switching preparation" instruction to all matrix boards, and then, after delaying for a specified time, further send a "synchronous switching" preparation instruction to all matrix boards.

[0065] Embodiment 4

[0066] Refer to Figure 5, based on Embodiment 1, step S3 includes the following specific processes:

[0067] S31: Start the matrix board card program, set the enable EN' = 1, loop to receive instructions from the RS422 bus, determine the type of instruction received by the matrix board card. If the type of instruction received by the matrix board card is an "I / O data" instruction, execute step S32. If the type of instruction received by the matrix board card is a "switching preparation" instruction, execute step S33. If the type of instruction received by the matrix board card is a "synchronous switching" instruction, execute step S34;

[0068] S32: Send I / O data to the serial-to-parallel conversion chip through SPI;

[0069] S33: Set the enable EN' to 0;

[0070] S34: Set the enable EN' to 1.

[0071] In the above solution, after the matrix board card program is started, the enable EN' is set to 1, loop to receive instructions from the bus, determine the type of instruction received by the board card. If it is an "I / O data" instruction, send the I / O data to the serial-to-parallel conversion chip through SPI. If it is a "switching preparation" instruction, set the enable EN' to 0. If it is a "synchronous switching" instruction, set the enable EN' to 1.

[0072] During the period when the enable EN' of the matrix board card is 0, when the first 0 of RX appears, that is, the start bit in the serial protocol, the I / O data stored in the serial-to-parallel conversion chip HC595 immediately flips and outputs. When the I / O data has no change, the switch has no switching action, and the signal is not interrupted. When the I / O data has a change and the switch has a switching action, all the switches that need to be switched on all matrix board cards act synchronously, and the channel signal shows a process of gradually disappearing and then gradually reappearing. The time of this process depends on the switching time of the radio frequency switch chip and is 50 - 150 ns.

[0073] In this embodiment, the number of lost code elements of signals with different modulation rates caused by the signal interruption time is as follows in the table:

[0074]

[0075] As can be seen from the above table, for signals with a rate below 1 MBd, the number of lost symbols is less than 1. For signals with a rate below 20 MBd, the maximum number of lost symbols is only 3, and the signal will not lose lock. The lost symbols can also be recovered through the error correction mechanism of the signal. Therefore, the technical problem in the prior art that for signals with a rate above 1 MBd, the number of lost symbols reaches hundreds, even leading to demodulation lock loss, is solved. By adding special logic control and using the rising edge of the start bit of the serial RS422 bus data and the enable of the synchronous switching instruction for cooperative control, the synchronous switching of multiple matrix cards under multiple asynchronous microprocessors is realized, and the routing switching time of the large-scale matrix is increased from the microsecond level to the nanosecond level. Furthermore, the routing switching of the established channels is realized, and the signal reception and demodulation channels are lossless and insensitive.

[0076] In summary, the channel synchronous switching method based on the asynchronous bus in the large-scale matrix switch provided by the present invention first adds a NOR gate logic control unit in the control circuit of the matrix card to construct an RS422 bus and an SPI hardware bus circuit including synchronous switching control enable; the matrix device sends I / O data to the matrix card through the RS422 bus, the matrix card receives the I / O data, and forwards it to the serial-to-parallel conversion chip for storage through the SPI; the matrix device sends a synchronous switching preparation instruction through the RS422 bus, and the matrix card turns on the synchronous switching control enable switch; the matrix device sends a synchronous switching instruction through the RS422 bus, and the matrix card turns off the synchronous switching control enable switch. By adding special logic control and using the rising edge of the start bit of the serial RS422 bus data and the enable of the synchronous switching instruction for cooperative control, the synchronous switching of multiple matrix cards under multiple asynchronous microprocessors is realized, and the routing switching time of the large-scale matrix is increased from the microsecond level to the nanosecond level. Furthermore, the routing switching of the established channels is realized, and the signal reception and demodulation channels are lossless and insensitive.

[0077] The above embodiments only represent the specific implementation methods of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation to the protection scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the technical solution of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application.

Claims

1. A channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus, characterized in that, It includes the following steps: S1: In the control circuit of the matrix board, add a NOR gate logic control unit to construct an RS422 bus and an SPI hardware bus circuit including synchronous switching control enabling; S2: When the matrix device needs to perform a routing switch, the matrix device sends I / O data to the matrix board through the RS422 bus. The matrix board receives the I / O data and forwards it to the serial-to-parallel conversion chip through the SPI for storage; S3: The matrix device sends a "switching preparation" instruction through the RS422 bus. The matrix board receives the command and turns on the synchronous switching control enabling switch; S4: The matrix device sends a "synchronous switching" instruction through the RS422 bus. Utilizing the rising edge of the start bit of the serial RS422 bus data, achieve synchronous flipping of the I / O of all 595 chips on all boards. The matrix board receives the command and turns off the synchronous switching control enabling switch.

2. The channel synchronous switching method based on an asynchronous bus in a large-scale matrix switch according to claim 1, wherein The control circuit of the matrix board with the addition of a NOR gate in step S1 includes a board microprocessor, a serial-to-parallel conversion chip, a serial port chip, and an RS422 bus. There are several serial-to-parallel conversion chips. The board microprocessor is connected to several serial-to-parallel conversion chips. The board microprocessor is also connected to the serial port chip. The NOR gate is respectively connected to the board microprocessor, the serial-to-parallel conversion chip, and the serial port chip. The RS422 bus is connected to the serial port chip. The model of the serial-to-parallel conversion chip is HC595.

3. A channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus according to claim 2, characterized in that In the control circuit of the matrix board, when the enabling EN’ = 1, the RX change generated by the RS422 bus data makes the enabling EN always 0, and it will not cause the stored data of the HC595 chip to flip to the output; when the enabling EN’ = 0, for the RX generated by the RS422 bus data, as long as RX = 0, then the enabling EN = 1, and the stored data of the serial-to-parallel conversion chip HC595 chip flips to the output.

4. A channel synchronous switching method based on an asynchronous bus in a large-scale matrix switch according to claim 2, characterized in that When the matrix is a large-scale matrix, its plug-in card matrix bus control circuit includes a matrix board, a serial port chip, an overall machine microprocessor, and a network port chip. The network port chip is connected to the overall machine microprocessor. The overall machine microprocessor is connected to the serial port chip. There are several matrix boards. The serial port chip is respectively connected to several matrix boards through the RS422 bus.

5. A channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus according to claim 1, characterized in that, The specific process of step S2 is as follows: S21: When the matrix needs to perform a routing switch, screen and find the matrix boards that need to change the I / O. Through the RS422 bus, sequentially send I / O control data to the matrix boards that need to change the I / O, and determine whether I / O control data has been sent to all matrix boards. If so, execute step S22. If not, continue to sequentially send I / O control data to the remaining matrix boards that need to change the I / O through the RS422 bus; S22: Send a "switching preparation" instruction to all matrix boards, and after a specified delay time, send a "synchronous switching" instruction to all matrix boards again; S23: Forward it to the serial-to-parallel conversion chip through the SPI for storage.

6. A channel synchronous switching method based on an asynchronous bus in a large-scale matrix switch according to claim 5, characterized in that, Step S3 includes the following specific process: S31: Start the matrix board card program, set the enable EN' = 1, loop to receive instructions from the RS422 bus, and determine the type of instruction received by the matrix board card. If the type of instruction received by the matrix board card is an "I / O data" instruction, execute step S32. If the type of instruction received by the matrix board card is a "switching preparation" instruction, execute step S33. If the type of instruction received by the matrix board card is a "synchronous switching" instruction, execute step S34; S32: Send I / O data to the serial-to-parallel conversion chip through SPI; S33: Set the enable EN' to 0; S34: Set the enable EN' to 1.

7. A channel synchronous switching method based on an asynchronous bus in a large-scale matrix switch according to claim 1, characterized in that During the period when the enable EN' of the matrix board card is 0, when the first 0 of RX appears, that is, the start bit in the serial protocol, the I / O data stored in the serial-to-parallel conversion chip HC595 is immediately inverted and output. When there is no change in the I / O data, no switching action of the switch, and the signal is not interrupted; When there is a change in the I / O data and a switching action of the switch, all the switches that need to be switched on all matrix board cards act synchronously, and the channel signal shows a process of gradually disappearing and then gradually reappearing. The time of this process depends on the switching time of the radio frequency switch chip and is 50 - 150 ns.

8. A channel synchronous switching method based on an asynchronous bus in a large-scale matrix switch according to claim 1, characterized in that, The NOR gate logic control unit is a multi-input NOR gate logic control unit, including multiple input terminals and 1 output terminal.

9. A channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus according to claim 8, characterized in that When all the inputs of multiple input terminals are low level, the output terminal outputs a high level 1; when the input of one of the multiple input terminals is high level, the output terminal outputs a low level 0.

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