Method for reducing gate-source reverse leakage current

Abstract

The invention provides a method for reducing gate-source reverse leakage current, which comprises the following steps: providing a substrate, forming a groove on the substrate, and forming an ONO layer on the groove, the ONO layer being composed of a first oxide layer, a nitride layer and a second oxide layer which are sequentially stacked from bottom to top; forming a first polycrystalline silicon layer with a preset thickness in the trench, then forming an isolation dielectric layer on the first polycrystalline silicon layer, and exposing the second oxide layer on the upper side of the isolation dielectric layer; removing the exposed second oxide layer and nitride layer; forming a third oxide layer on the first oxide layer, wherein the total thickness of the first oxide layer and the third oxide layer is the target thickness; and forming a second polycrystalline silicon layer for filling the residual groove, so that the bottom of the second polycrystalline silicon layer is in a smooth shape. While the reference process structure is matched, the gate-source reverse leakage current parameter is reduced by at least one order of magnitude.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for reducing gate-source reverse leakage current. Background Art

[0002] The SGT (trench gate) product showed a high IGSSR (gate-source reverse leakage current) phenomenon, and failure analysis found that sharp corners appeared at the bottom of the gate polysilicon.

[0003] The gate polysilicon has a large corner curvature and a large electric field strength. Based on the Poole-Frenkel effect, the conductivity of the insulating material is proportional to the electric field strength. Electrons can easily flow through the oxide layer from the gate polysilicon corner, resulting in a high IGSSR.

[0004] In order to solve the above problems, a new method for reducing gate-source reverse leakage current needs to be proposed. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for reducing the gate-source reverse leakage current, which is used to solve the problem in the prior art that the gate polysilicon corner has a large curvature, the electric field strength is large, and electrons easily flow through the oxide layer from the gate polysilicon corner, resulting in a high gate-source reverse leakage current.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for reducing gate-source reverse leakage current, comprising:

[0007] Step 1, providing a substrate, forming a groove on the substrate, and forming an ONO layer on the groove, wherein the ONO layer consists of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top;

[0008] Step 2, forming a first polysilicon layer of a preset thickness in the trench, and then forming an isolation dielectric layer on the first polysilicon layer, with the second oxide layer on the upper side of the isolation dielectric layer exposed;

[0009] Step 3, removing the exposed second oxide layer and the nitride layer;

[0010] Step 4: forming a third oxide layer on the first oxide layer, wherein the total thickness of the first and third oxide layers is a target thickness;

[0011] Step 5: forming a second polysilicon layer filling the remaining trenches, so that the bottom of the second polysilicon layer has a smooth morphology.

[0012] Preferably, in step one, the first oxide layer is formed by thermal oxidation.

[0013] Preferably, in step one, the nitride layer is formed by low pressure chemical vapor deposition.

[0014] Preferably, in step one, the second oxide layer is formed by chemical vapor deposition.

[0015] Preferably, in step one, the thickness of the first oxide layer is reduced and the thickness of the second oxide layer is increased, so that the thicknesses of the first and second oxide layers are consistent with the reference process.

[0016] Preferably, in step 2, the first polysilicon layer is formed by a deposition and polysilicon back etching method.

[0017] Preferably, the isolation dielectric layer in step 2 is an oxide layer formed by thermal oxidation.

[0018] Preferably, in step three, the second oxide layer and the nitride layer are removed in sequence by wet etching.

[0019] Preferably, in step four, the third oxide layer is formed by low pressure chemical vapor deposition.

[0020] Preferably, in step five, the second polysilicon layer is formed by a deposition and polysilicon back etching method.

[0021] As described above, the method for reducing gate-source reverse leakage current of the present invention has the following beneficial effects:

[0022] The present invention reduces the gate-source reverse leakage current parameter by at least one order of magnitude while matching the reference process structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0024] Figure 2 Shown is a schematic diagram of forming an ONO layer according to the present invention;

[0025] Figure 3 It is a schematic diagram showing the formation of a first polysilicon layer according to the present invention;

[0026] Figure 4 It is a schematic diagram showing the formation of an isolation dielectric layer according to the present invention;

[0027] Figure 5 It is a schematic diagram showing the removal of the exposed second oxide layer and nitride layer according to the present invention;

[0028] Figure 6 It is a schematic diagram showing the formation of a third oxide layer according to the present invention;

[0029] Figure 7 It is a schematic diagram of forming a second polysilicon layer according to the present invention. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] See also Figure 1 The present invention provides a method for reducing gate-source reverse leakage current, comprising:

[0032] Step 1: Provide a substrate 101, form a groove on the substrate 101, and form an ONO layer on the groove. The ONO layer is composed of a first oxide layer 102, a nitride layer 103, and a second oxide layer 104 stacked in sequence from bottom to top to form a substrate 101. Figure 2 The structure shown; usually the material of the first and second oxide layers is silicon dioxide, and the material of the nitride layer 103 is silicon nitride;

[0033] In some embodiments, in step 1, the grooves are formed by photolithography and dry etching.

[0034] In some embodiments, in step 1, the first oxide layer 102 is formed by thermal oxidation.

[0035] In some embodiments, in step 1, the nitride layer 103 is formed by low pressure chemical vapor deposition.

[0036] In some embodiments, the second oxide layer 104 is formed by chemical vapor deposition in step 1.

[0037] In some embodiments, in step 1, the thickness of the first oxide layer 102 is reduced, and the thickness of the second oxide layer 104 is increased, so that the thickness of the first and second oxide layers is consistent with the thickness of the field oxide layer of the reference process. For example, the thickness of the first oxide layer 102 in the reference process is 400 angstroms, the thickness of the nitride layer 103 is 200 angstroms, and the thickness of the second oxide layer 104 is 800 angstroms. In the embodiment of the present invention, the thickness of the first oxide layer 102 is 100 angstroms, the thickness of the nitride layer 103 is 200 angstroms, and the thickness of the second oxide layer 104 is 1100 angstroms.

[0038] Step 2: forming a first polysilicon layer 105 of a preset thickness in the trench, forming Figure 3 The structure shown in FIG. 1 is then formed on the first polysilicon layer 105 to form an isolation dielectric layer 106. Figure 4 In the structure shown, the second oxide layer 104 on the upper side of the isolation dielectric layer 106 is exposed;

[0039] In some embodiments, in step 2, the first polysilicon layer 105 is formed by deposition and polysilicon etch-back.

[0040] In some embodiments, the isolation dielectric layer 106 in step 2 is an oxide layer formed by thermal oxidation.

[0041] Step 3: remove the exposed second oxide layer 104 and the nitride layer 103 to form Figure 5 The structure shown;

[0042] In some embodiments, in step three, the second oxide layer 104 and the nitride layer 103 are removed in sequence by wet etching, that is, the second oxide layer 104 is first removed by wet etching with a high selectivity of the oxide layer to the nitride layer 103, and then the nitride layer 103 is removed by wet etching with a high selectivity of the nitride layer 103 to the oxide layer. This can reduce the loss of the first oxide layer 102 on the side wall and avoid the appearance of sharp corners there.

[0043] Step 4: forming a third oxide layer 107 on the first oxide layer 102, forming Figure 6 In the structure shown, the total thickness of the first and third oxide layers is the target thickness, ensuring that the gate oxide layer is consistent with the benchmark process structure (consistent with the benchmark process threshold voltage), and also improving the bottom morphology of the second polysilicon layer 108; for example, the thickness of the first oxide layer 102 in the benchmark process is 400 angstroms, the thickness of the nitride layer 103 is 200 angstroms, and the thickness of the second oxide layer 104 is 800 angstroms. Then, in the embodiment of the present invention, the thickness of the first oxide layer 102 is 100 angstroms, the thickness of the nitride layer 103 is 200 angstroms, the thickness of the second oxide layer 104 is 1100 angstroms, and the thickness of the third oxide layer 107 is 300 angstroms.

[0044] In some embodiments, in step 4, the third oxide layer 107 is formed by low pressure chemical vapor deposition.

[0045] Step 5: forming a second polysilicon layer 108 filling the remaining trenches, so that the bottom of the second polysilicon layer 108 has a smooth morphology, forming a Figure 7 The structure shown.

[0046] In some embodiments, in step five, the second polysilicon layer 108 is formed by deposition and polysilicon etch-back methods.

[0047] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] In summary, the present invention reduces the gate-source reverse leakage current parameter by at least one order of magnitude while matching the reference process structure. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for reducing gate-source reverse leakage current, characterized in that: At least: Step 1, providing a substrate, forming a groove on the substrate, and forming an ONO layer on the groove, wherein the ONO layer consists of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top; Step 2, forming a first polysilicon layer of a preset thickness in the trench, and then forming an isolation dielectric layer on the first polysilicon layer, with the second oxide layer on the upper side of the isolation dielectric layer exposed; Step 3, removing the exposed second oxide layer and the nitride layer; Step 4: forming a third oxide layer on the first oxide layer, wherein the total thickness of the first and third oxide layers is a target thickness; Step 5: forming a second polysilicon layer filling the remaining trenches, so that the bottom of the second polysilicon layer has a smooth morphology.

2. The method for reducing gate-source reverse leakage current according to claim 1, characterized in that: In step one, the first oxide layer is formed by thermal oxidation.

3. The method for reducing gate-source reverse leakage current according to claim 1, characterized in that: In step 1, the nitride layer is formed by using a low pressure chemical vapor deposition method.

4. The method for reducing gate-source reverse leakage current according to claim 1, characterized in that: In step one, the second oxide layer is formed by chemical vapor deposition.

5. The method for reducing gate-source reverse leakage current according to claim 1, characterized in that: In step one, the thickness of the first oxide layer is reduced, and the thickness of the second oxide layer is increased, so that the thicknesses of the first and second oxide layers are consistent with the reference process.

6. The method for reducing gate-source reverse leakage current according to claim 1, characterized in that: In step 2, the first polysilicon layer is formed by deposition and polysilicon back etching.

7. The method for reducing gate-source reverse leakage current according to claim 1, characterized in that: The isolation dielectric layer in step 2 is an oxide layer formed by thermal oxidation.

8. The method for reducing gate-source reverse leakage current according to claim 1, characterized in that: In step three, the second oxide layer and the nitride layer are removed in sequence by wet etching.

9. The method for reducing gate-source reverse leakage current according to claim 1, characterized in that: In step 4, the third oxide layer is formed by low pressure chemical vapor deposition.

10. The method for reducing gate-source reverse leakage current according to claim 1, characterized in that: In step five, the second polysilicon layer is formed by deposition and polysilicon back etching.

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