Semiconductor process chamber and semiconductor process equipment

Abstract

The invention discloses a semiconductor process chamber, the disclosed semiconductor process chamber comprises a chamber body, a base and a first lining, the base is arranged in the chamber body, the first lining is movably arranged in the chamber body, the first lining is arranged around the base, and the first lining is arranged in the chamber body. The cavity body is arranged on the base and is positioned between the base and the cavity body; when a deposition process is carried out in the semiconductor process chamber, the first lining moves to a first position, and at least part of the first lining is higher than the bearing surface of the base; and when an etching process is carried out in the semiconductor process chamber, the first lining moves to a second position, and the first lining is lower than the bearing surface or is flush with the bearing surface. According to the technical scheme, the problem that the wafer is polluted due to the fact that the film layer deposited on the inner wall of the chamber easily falls on the wafer in the etching process of the process chamber in the related technology can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor equipment, and in particular to a semiconductor process chamber and semiconductor process equipment. Background Art

[0002] With the rapid development of the semiconductor industry, etcher is widely used in the manufacturing process of IC (integrated circuit). With the update and iteration of semiconductor process, the process requirements for etcher are also increasing. As the thickness of the wafer becomes higher and higher, the thickness of the wafer to be etched is also correspondingly thicker. In the process of etching the wafer to form an etched hole, due to the incomplete anisotropy in the etching, the etching process will also produce a certain amount of lateral etching on the sidewall of the etched hole, resulting in the sidewall hollowing out. Under the premise of protecting the sidewall from excessive lateral etching, the high aspect ratio etched hole etching process has a very important impact on the etcher and semiconductor equipment.

[0003] In order to obtain etched holes with high aspect ratios when etching wafers, the current method mainly uses a combination of etching process and atomic layer deposition process. During the atomic layer deposition process, the deposits are easily attached to the inner wall of the chamber and the components in the chamber. After alternating multiple etching and atomic layer deposition processes, during the etching process, the film layer deposited on the inner wall of the chamber is easily dropped onto the wafer due to the etching effect, thereby contaminating the wafer. Summary of the invention

[0004] The invention discloses a semiconductor process chamber to solve the problem that during an etching process in the process chamber in the related art, a film layer deposited on the inner wall of the chamber is easily dropped onto a wafer, thereby causing contamination to the wafer.

[0005] In order to solve the above-mentioned technical problems, the present invention is achieved as follows: The present application discloses a semiconductor process chamber, which includes a chamber body, a base and a first liner, wherein the base is arranged in the chamber body, the first liner is movably arranged in the chamber body, the first liner is arranged around the base, and is located between the base and the chamber body; when the semiconductor process chamber performs a deposition process, the first liner moves to a first position, and at least a part of the first liner is higher than the supporting surface of the base; when the semiconductor process chamber performs an etching process, the first liner moves to a second position, and the first liner is lower than the supporting surface or flush with the supporting surface.

[0006] The technical solution adopted by the present invention can achieve the following technical effects: The semiconductor process chamber disclosed in the embodiment of the present application is provided with a first liner, so that the first liner is movably arranged in the chamber body and is arranged around the base, so that when the semiconductor process chamber performs a deposition process, the first liner moves to a bearing surface that is at least partially higher than the base, so as to avoid the film layer from being deposited on the area corresponding to the chamber body blocked by the first liner. When the semiconductor process chamber performs an etching process, the first liner moves to a position lower than the bearing surface or flush with the bearing surface, and at the same time, the film layer deposited on the first liner is carried to the bottom of the bearing surface or flush with the bearing surface. Since the area corresponding to the side wall of the chamber body and the first liner at the first position has no film layer or only has a small amount of film layer (which can be ignored), therefore, when the semiconductor process chamber performs an etching process, there will be no phenomenon of etching the film layer on the area corresponding to the first liner at the first position of the side wall, thereby avoiding or reducing the film layer from falling on the wafer, thereby alleviating the contamination caused to the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A cross-sectional view of a semiconductor process chamber disclosed in an embodiment of the present invention when a first liner moves to a second position; Figure 2 A cross-sectional view of a semiconductor process chamber disclosed in an embodiment of the present invention when a first liner moves to a first position; Figure 3 It is an enlarged schematic diagram of the driving mechanism disclosed in the embodiment of the present invention; Figure 4 A schematic diagram of the cooperation between the connecting block and the guide rod disclosed in an embodiment of the present invention; Figure 5 It is a partially enlarged schematic diagram of the semiconductor process chamber disclosed in an embodiment of the present invention when the first liner moves to the first position; Figure 6 It is a partially enlarged schematic diagram of the semiconductor process chamber disclosed in an embodiment of the present invention when the first liner moves to the second position; Figure 7 It is a schematic structural diagram of a first liner disclosed in an embodiment of the present invention; Figure 8 A schematic diagram of the structure of a semiconductor process equipment disclosed in an embodiment of the present invention; Fig. 9 A schematic diagram of a semiconductor process chamber disclosed in an embodiment of the present invention performing an etching process; Fig.10 A schematic diagram of a semiconductor process chamber disclosed in an embodiment of the present invention performing a deposition process; Fig.11 is a schematic diagram of purging the second sub-tube; Fig.12 A schematic diagram of replenishing source liquid to the first source liquid device 740; Fig.13 A schematic diagram of a semiconductor process equipment disclosed in an embodiment of the present invention in a first sub-state; Fig.14 A schematic diagram of a semiconductor process equipment disclosed in an embodiment of the present invention in a second sub-state; Fig.15 A schematic diagram of a semiconductor process device disclosed in an embodiment of the present invention in a third sub-state; Fig.16 A schematic diagram of a semiconductor process equipment disclosed in an embodiment of the present invention in a fourth sub-state; Fig.17 A schematic diagram of a semiconductor process equipment disclosed in an embodiment of the present invention in a fifth sub-state; Fig.18 A schematic diagram of a semiconductor process equipment disclosed in an embodiment of the present invention in a sixth sub-state; Fig.19 A schematic diagram of the bottom of the splash-proof box disclosed in an embodiment of the present invention being in an open state; Fig. 20 This is a schematic diagram of the bottom of the splash-proof box disclosed in an embodiment of the present invention being in an unopened state.

[0008] Description of reference numerals: 100-chamber body, 101-first gap, 102-second gap, 103-third gap, 110-top wall, 120-side wall, 130-exhaust device, 200-base, 201-bearing surface, 210-base body, 220-flow equalizer, 230-cantilever, 300-first lining, 301-first avoidance hole, 310-main body, 311-strip hole, 320-inclined portion, 330-extension portion, 340-connecting block, 341-limiting protrusion, 350-bolt, 360-buffer pad, 400-Gas Launcher, 500-driving mechanism, 510-driving body, 520-guide rod, 521-threaded hole, 522-limiting groove, 600-second lining, 601-second avoidance hole, 710-first gas source device, 720-second gas source device, 730-third gas source device, 740-first source liquid device, 750-vaporizer, 760-second source liquid device, 761-exhaust port, 770-fifth gas source device, 780-first flow controller, 790-second flow controller, 810-condenser, 820-pressure detection device, 840-splash box, 841-inner shell, 841a-first filter hole, 842-outer shell, 842a-second filter hole, 843-splash liquid level sensor, 844-liquid storage space, 901-first pipeline, 902-second pipeline, 902a-third sub-pipe, 902b-fourth sub-pipe, 903-third pipeline, 903a-fifth sub-pipe, 903b-sixth sub-pipe, 904-fourth pipeline, 905-fifth pipeline, 905a-first sub-pipe, 905b-second sub-pipe, 906-sixth pipeline, 907-seventh pipeline, 908-eighth pipeline, 909-ninth pipeline, 9010-tenth pipeline, 9011-eleventh pipeline, 9012-twelfth pipeline, 9013-thirteenth pipeline, 9014-fourteenth pipeline, 9020-first exhaust pipeline, 9021-second exhaust pipeline. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0010] In order to facilitate the understanding of the technical solution of the present application, the present application first describes the relevant contents of the semiconductor process chamber, as follows: In the process of etching the wafer to form an etched hole in the semiconductor process chamber, due to the incomplete anisotropy in the etching, the etching process will also produce a certain amount of lateral etching on the sidewall of the etched hole, resulting in the sidewall hollowing out. Under the premise of protecting the sidewall from excessive lateral etching, the high aspect ratio etched hole etching process has a very important impact on the etcher and semiconductor equipment.

[0011] In order to obtain etched holes with a high aspect ratio when etching the wafer, a method combining etching process and atomic layer deposition process is used. The wafer is first etched, and a protective film layer is deposited on the side wall of the wafer before the etched hole is etched to a certain depth and no sidewall indentation occurs. Since the longitudinal etching speed is greater than the lateral etching when etching the etched hole, the etched hole can be etched deeper in the longitudinal direction while etching the film layer on the side wall. The etching process and atomic layer deposition process are repeated until an etched hole with a specific high aspect ratio is formed on the wafer.

[0012] In order to obtain etched holes with a high aspect ratio, the related technology uses a process chamber that can perform both etching and atomic layer deposition processes. Since during the atomic layer deposition process, the sediment is easily attached to the inner wall of the chamber and the components in the chamber, after alternating multiple etching and atomic layer deposition processes, during the etching process, the film layer deposited on the inner wall of the chamber is easily dropped on the wafer due to the etching effect, thereby causing contamination to the wafer. The technical solution disclosed in the present application can alleviate the problem that during the etching process in the process chamber, the film layer deposited on the inner wall of the chamber is easily dropped on the wafer and causes contamination to the wafer.

[0013] The technical solutions disclosed in various embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0014] Please refer to Figures 1 to 20 An embodiment of the present invention discloses a semiconductor process chamber. The disclosed semiconductor process chamber includes a chamber body 100 , a base 200 and a first liner 300 .

[0015] The pedestal 200 is disposed in the chamber body 100 and is used to carry the wafer. The first liner 300 is movably disposed in the chamber body 100 and is disposed around the pedestal 200 and is located between the pedestal 200 and the chamber body 100. The first liner 300 may be a cylindrical body.

[0016] When the semiconductor process chamber performs a deposition process, the first liner 300 moves to the first position, and at least a portion of the first liner 300 is higher than the supporting surface 201 of the susceptor 200. The first liner 300 can protect the area of ​​the chamber body 100 opposite thereto to reduce the thickness of the film layer deposited on the inner wall of the chamber body 100.

[0017] When an etching process is performed in a semiconductor process chamber, the first liner 300 moves to a second position, where the first liner 300 is lower than the carrying surface 201 or flush with the carrying surface 201, thereby carrying the film layer deposited on the first liner 300 to the bottom of the carrying surface 201 of the base 200 or flush with the carrying surface 201. After the first liner 300 moves to a position lower than the carrying surface 201 or flush with the carrying surface 201, even if more film layers are deposited on the first liner 300, they will not fall onto the wafer located on the carrying surface 201.

[0018] The semiconductor process chamber disclosed in the embodiment of the present application is provided with a first liner 300, so that the first liner 300 is movably arranged in the chamber body 100 and is arranged around the base 200. Therefore, when a deposition process is performed in the semiconductor process chamber, the first liner 300 moves to a supporting surface 201 that is at least partially higher than the base 200, thereby preventing the film layer from being deposited on the area of ​​the chamber body 100 corresponding to the area blocked by the first liner 300. When an etching process is performed in a semiconductor process chamber, the first liner 300 moves to a position lower than the carrying surface 201 or flush with the carrying surface 201, and at the same time, the film layer deposited on the first liner 300 is also carried to the bottom of the carrying surface 201 or flush with the carrying surface 201. Since there is no film layer or only a small amount of film layer (which can be ignored) in the area corresponding to the side wall 120 of the chamber body 100 and the first liner 300 at the first position, when an etching process is performed in the semiconductor process chamber, there will be no etching of the film layer in the area corresponding to the first liner 300 at the first position of the side wall 120, thereby avoiding or reducing the film layer from falling onto the wafer, thereby alleviating the contamination of the wafer.

[0019] When the semiconductor process chamber is performing a deposition process, in order to prevent the first precursor and the second precursor introduced into the chamber body 100 from undergoing a deposition reaction at the air inlet before entering the chamber body 100 and blocking the air inlet, optionally, the top wall 110 of the chamber body 100 is provided with a first air inlet, the side wall 120 of the chamber body 100 is provided with a second air inlet higher than the bearing surface 201, and the first liner 300 is provided with a first avoidance hole 301. When the semiconductor process chamber is performing a deposition process, the second air inlet is opposite to the first avoidance hole 301, the first air inlet is used to introduce the first precursor, the second air inlet is used to introduce the second precursor, and the first precursor and the second precursor are deposited in the chamber body 100, so that the semiconductor process chamber is subjected to a deposition process. When the semiconductor process chamber is performing an etching process, the first liner 300 is located below the second air inlet, and the first air inlet is used to introduce etching gas, so that the semiconductor process chamber is subjected to an etching process.

[0020] The semiconductor process chamber disclosed in the embodiment of the present application is provided with a first air inlet hole on the top wall 110 of the chamber body 100, and a second air inlet hole higher than the supporting surface 201 is provided on the side wall 120 of the chamber body 100, so that when a deposition process is performed in the semiconductor process chamber, the second air inlet hole is opposite to the first avoidance hole 301, the first air inlet hole allows the first precursor to pass through, and the second air inlet hole allows the second precursor to pass through, thereby preventing the first precursor and the second precursor from undergoing a deposition reaction at the air inlet before entering the chamber body 100 and thereby clogging the air inlet holes.

[0021] Optionally, the semiconductor process chamber may further include a gas emitter 400, and both the first gas inlet and the second gas inlet may be provided with a gas emitter 400, and the first precursor, the second precursor and the etching gas may be delivered into the chamber body 100 through the corresponding gas emitters 400. When the semiconductor process chamber performs a deposition process, the first liner 300 moves to the first position, and a first gap 101 is formed between the gas emitter 400 located at the second gas inlet and the opening of the first avoidance hole 301 facing the side wall 120.

[0022] The semiconductor process chamber disclosed in the embodiment of the present application can avoid friction between the first liner 300 and the gas emitter 400 located at the second air inlet hole when the first liner 300 moves between the first position and the second position, thereby preventing particles generated by friction from contaminating the wafer.

[0023] In an optional embodiment, the first liner 300 may include a body portion 310, an inclined portion 320 and an extension portion 330. The body portion 310 may be a cylindrical structure, the inclined portion 320 and the extension portion 330 may both be annular structures, the body portion 310 may be sleeved on the base 200, the first end of the inclined portion 320 may be connected to the first port of the body portion 310, the second end of the inclined portion 320 may be connected to the first end of the extension portion 330, the second end of the inclined portion 320 may be inclined toward one side of the central axis of the cylindrical structure, the second end of the extension portion 330 may extend toward the side where the central axis of the cylindrical structure is located, and the extension portion 330 is parallel to the bearing surface 201. Specifically, the angle between the inclined portion 320 and the extension portion 330 may be between 100° and 110°, including 100° and 110°, so that the ability to attach the film layer at the angle between the inclined portion 320 and the extension portion 330 can be reduced. If the angle is too small, the film layer is more likely to adhere to the angle between the inclined portion 320 and the extended portion 330 (since the air flow is poor at the location with significant edges and corners, the film layer is more likely to adhere to the angle).

[0024] The semiconductor process chamber disclosed in the embodiment of the present application sets the first liner 300 to include a body portion 310, an inclined portion 320 and an extension portion 330, so that the body portion 310 can protect the side wall 120 of the chamber body 100, and the extension portion 330 can protect the edge area of ​​the top wall 110 of the chamber body 100, so as to reduce the thickness of the film layer deposited in the edge area of ​​the side wall 120 and the top wall 110. The body portion 310 and the extension portion 330 are transitionally connected through the inclined portion 320, which can alleviate the situation where a thicker film layer is easily deposited due to the small angle formed at the connection between the body portion 310 and the extension portion 330.

[0025] Optionally, when the semiconductor process chamber performs a deposition process, a second gap 102 may be provided between the extension portion 330 and the top wall 110 of the chamber body 100. For example, the second gap 102 may be between 0.3 mm and 0.8 mm, including 0.3 mm and 0.8 mm. When the semiconductor process chamber performs an etching process, the extension portion 330 may be located below the carrying surface 201 or flush with the carrying surface 201.

[0026] The embodiment of the present application configures the semiconductor process chamber so that when a deposition process is performed in the semiconductor process chamber, a second gap 102 is provided between the extension portion 330 and the top wall 110 of the chamber body 100, thereby preventing particles from falling due to friction between the extension portion 330 and the top wall 110 of the chamber body 100.

[0027] Specifically, when maintaining the second gap 102 between the extension portion 330 and the top wall 110, the control can be performed by controlling the stroke of the first lining 300, or by detecting the distance through a distance sensor. The specific technology for maintaining the second gap 102 between the extension portion 330 and the top wall 110 belongs to the prior art and will not be repeated in the embodiments of the present application.

[0028] In order to make the airflow distribution in the chamber body 100 relatively uniform, optionally, the base 200 may include a base body 210 and a flow equalizer 220. The base body 210 may include a bearing surface 201 for bearing a wafer. The flow equalizer 220 may be arranged around the base body 210 and located below the bearing surface 201. The flow equalizer 220 may be provided with a plurality of flow equalizer holes distributed around the base body 210, and the flow equalizer holes may be strip-shaped grid holes. The chamber body 100 may be provided with an exhaust hole, and the exhaust hole is located below the flow equalizer 220. When an etching process is performed in the semiconductor process chamber, a third gap 103 may be provided between the extension portion 330 and the flow equalizer 220.

[0029] The semiconductor process chamber disclosed in the embodiment of the present application is provided with a flow equalizer 220, so that the flow equalizer 220 is arranged around the base body 210 and is located below the bearing surface 201, and the flow equalizer 220 is provided with a plurality of flow equalizer holes distributed around the base body 210, so that the gas in the chamber body 100 can pass through the plurality of flow equalizer holes evenly and be discharged from the exhaust hole. Since the plurality of flow equalizer holes are evenly distributed around the base body 210, the exhaust of each area in the chamber body 100 is relatively uniform, thereby improving the uniformity of the gas flow distribution in the chamber body 100. When the etching process is performed in the semiconductor process chamber, the third gap 103 is retained between the extension part 330 and the flow equalizer 220, so as to avoid the situation where there are more particles caused by friction between the extension part 330 and the flow equalizer 220.

[0030] Optionally, the extension portion 330 may cover the edge region of the uniform flow hole in the radial direction of the bearing surface 201. Since the extension portion 330 covers the edge region of the uniform flow hole, the gas in the chamber body 100 may converge toward the central region of the chamber body 100 when it is discharged through the uniform flow hole, so that the gas in the chamber body 100 may converge toward the position of the bearing surface 201, which is beneficial to improving the efficiency of the semiconductor process chamber when performing deposition and etching processes.

[0031] Specifically, the movement of the first liner 300 between the first position and the second position can be controlled manually. In order to improve the automation of the semiconductor process chamber, the semiconductor process chamber can optionally further include a drive mechanism 500, which can be disposed in the chamber body 100 and connected to the first liner 300. The drive mechanism 500 can be used to drive the first liner 300 to switch between the first position and the second position, thereby improving the automation of the semiconductor process chamber.

[0032] Optionally, there may be a plurality of driving mechanisms 500, and the base 200 may include a base body 210 and a plurality of cantilevers 230, the plurality of cantilevers 230 may be circumferentially arranged on the base body 210, and may correspond to the plurality of driving mechanisms 500 one by one, at least one cantilever 230 may be connected to the chamber body 100, one end of the other cantilevers 230 may be connected to the base body 210, and the other end may be suspended and may be spaced apart from the chamber body 100, and the driving mechanism 500 may be arranged on the cantilever 230. The first liner 300 may be provided with a strip hole 311, the strip hole 311 may extend along the direction in which the first liner 300 moves between the first position and the second position, the cantilever 230 connected to the chamber body 100 may penetrate the strip hole 311, and in the process in which the first liner 300 moves between the first position and the second position, the strip hole 311 may avoid the cantilever 230 corresponding thereto. Each driving mechanism 500 is provided on a corresponding cantilever 230 and connected to a corresponding portion of the first liner 300. When the number of the cantilever 230 is an even number, the cantilever 230 may be symmetrically arranged. When the number of the cantilever 230 is an odd number, in the direction surrounding the base body 210, the angles between any two adjacent cantilever 230 are equal.

[0033] The semiconductor process chamber disclosed in the embodiment of the present application is configured such that the base 200 is configured to include a base body 210 and a plurality of cantilevers 230, so that the plurality of cantilevers 230 are disposed around the base body 210, and a plurality of driving mechanisms 500 are disposed such that the plurality of driving mechanisms 500 correspond to the plurality of cantilevers 230 one by one, and the driving mechanisms 500 are disposed on the cantilevers 230, so that the first liner 300 is driven to move between the first position and the second position by the plurality of driving mechanisms 500, so that the movement of the first liner 300 is more stable. The cantilever 230 connected to the chamber body 100 can play a role in fixing and installing the entire base 200. By providing a strip hole 311, the cantilever 230 connected to the chamber body 100 is disposed in the strip hole 311, so that during the movement of the first liner 300 between the first position and the second position, the strip hole 311 can avoid the corresponding cantilever 230.

[0034] It should be noted that one end of the multiple cantilevers 230 is connected to the base body 210, and the other end of the cantilever 230 is suspended and spaced apart from the chamber body 100. The space between the cantilever 230 and the chamber body 100 allows the first lining 300 to extend into, and neither the cantilever 230 nor the chamber body 100 will contact the first lining 300.

[0035] Specifically, one of the multiple cantilevers 230 may be connected to the chamber body 100 , and the other cantilevers 230 may be spaced apart relative to the chamber body 100 , thereby eliminating the need to open more strip holes 311 on the first liner 300 , thereby facilitating the first liner 300 to protect the side wall 120 of the chamber body 100 to avoid deposition of a thicker film layer on the side wall 120 .

[0036] Of course, two or three of the multiple cantilevers 230 may be connected to the chamber body 100 , and this embodiment of the present application does not impose any specific limitation on this.

[0037] Specifically, the driving mechanism 500 may include a driving body 510 and a guide rod 520. The driving body 510 may be arranged on the cantilever 230. The driving body 510 may be connected to the first end of the guide rod 520. The second end of the guide rod 520 may be provided with a threaded hole 521 and a limiting groove 522 or a limiting protrusion 341 surrounding the threaded hole 521. The first lining 300 may have a connecting block 340 and a bolt 350. The connecting block 340 may have a limiting protrusion 341 or a limiting groove 522 that cooperates with the limiting groove 522 or the limiting protrusion 341 of the guide rod 520. The limiting protrusion 341 and the limiting groove 522 can cooperate in the upper limit in a moving direction perpendicular to the guide rod 520. The connecting block 340 may be provided with a connecting hole. The bolt 350 can pass through the connecting hole and threadably cooperate with the threaded hole 521 to connect the second end of the guide rod 520 to the connecting block 340.

[0038] The semiconductor process chamber disclosed in the embodiment of the present application is configured such that the driving mechanism 500 is configured to include a driving body 510 and a guide rod 520, so that the driving body 510 is disposed on the cantilever 230, the driving body 510 is connected to the first end of the guide rod 520, the second end of the guide rod 520 is connected to the connecting block 340 of the first liner 300 by a bolt 350, and the limiting groove 522 or the limiting protrusion 341 at the second end of the guide rod 520 cooperates with the limiting protrusion 341 or the limiting groove 522 of the connecting block 340 in an upper limit direction perpendicular to the moving direction of the first liner 300, so that the connection between the first liner 300 and the guide rod 520 is more stable.

[0039] Optionally, a buffer pad 360 may be connected between the second end of the guide rod 520 and the connecting block 340, so that when the driving mechanism 500 drives the first liner 300 to move, the impact between the first liner 300 and the guide rod 520 can be reduced, thereby protecting the first liner 300.

[0040] Optionally, the cantilever 230 may be provided with a protective space, and part of the driving body 510 may be located in the protective space, so that the driving body 510 can be protected and deposition of a thick film layer on the driving body 510 can be avoided.

[0041] The first lining 300 may be composed of a plurality of first sub-linings, and there may be gaps between the plurality of first sub-linings. For example, the gaps may be between 0.3 mm and 0.8 mm, and may include 0.3 mm and 0.8 mm, so as to absorb processing errors and avoid interference fit, thereby facilitating the first lining 300 to be arranged in the chamber body 100.

[0042] In order to further protect the side wall 120 of the chamber body 100, the semiconductor process chamber may optionally further include a second liner 600, which is disposed in the chamber body 100 and is detachably disposed on the side wall 120. The second liner 600 may be provided with a second avoidance hole 601, and when the first liner 300 is moved to the first position, the second liner 600 may be located between the first liner 300 and the chamber body 100, and the central axis of the second air inlet hole, the central axis of the first avoidance hole 301, and the central axis of the second avoidance hole 601 coincide with each other.

[0043] The semiconductor process chamber disclosed in the embodiment of the present application is provided with a second liner 600, so that the second liner 600 can be detachably provided on the side wall 120, so that the second liner 600 can protect the side wall 120 to prevent the film layer from being directly deposited on the side wall 120. Therefore, when a large number of film layers are deposited on the second liner 600, the second liner 600 can be directly removed for cleaning or replacement without disassembling the chamber body 100, thereby avoiding the risk of damaging the chamber body 100 when disassembling the chamber body 100.

[0044] Specifically, the second lining 600 may be composed of a plurality of second sub-linings, thereby facilitating the installation of the second lining 600 .

[0045] In order to reduce the rate of film layer deposition at the two orifices of the first avoidance hole 301 and the two orifices of the second avoidance hole 601, optionally, the two orifices of the first avoidance hole 301 can be a circular chamfered structure, and the two orifices of the second avoidance hole 601 can be a circular chamfered structure, thereby reducing the rate of film layer deposition at the two orifices of the first avoidance hole 301 and the two orifices of the second avoidance hole 601, thereby facilitating reducing the thickness of the film layer deposited at the two orifices of the first avoidance hole 301 and the two orifices of the second avoidance hole 601.

[0046] Please refer to Figure 8The present application also discloses a semiconductor process equipment, which includes the semiconductor process chamber disclosed in the above embodiment, a first pipeline 901 connected to the first air inlet, and a fifth pipeline 905 connected to the second air inlet, wherein the first pipeline 901 is used to selectively pass the first precursor or etching gas to the first air inlet, and the fifth pipeline 905 is used to pass the second precursor. When the semiconductor process chamber performs a deposition process, the first pipeline 901 and the fifth pipeline 905 alternately pass the first precursor and the second precursor. When the semiconductor process chamber performs an etching process, the first pipeline 901 passes the etching gas. First precursor and etching gas process first pipeline 901.

[0047] The semiconductor process equipment disclosed in the embodiment of the present application is provided with the semiconductor process chamber disclosed in the above embodiment, so that when the semiconductor process chamber performs a deposition process, the first liner 300 moves to a position at least partially higher than the bearing surface 201 of the base 200, thereby preventing the film layer from being deposited on the area corresponding to the chamber body 100 blocked by the first liner 300. When the semiconductor process chamber performs an etching process, the first liner 300 moves to a position lower than the bearing surface 201, and at the same time, the film layer deposited on the first liner 300 is also carried to the lower side of the bearing surface 201. Since there is no film layer or only a small amount of film layer (negligible) in the area corresponding to the side wall 120 of the chamber body 100 and the first liner 300 at the first position, when the semiconductor process chamber performs an etching process, there will be no phenomenon of etching the film layer on the area corresponding to the first liner 300 at the first position of the side wall 120, thereby preventing or reducing the film layer from falling on the wafer, thereby alleviating the contamination of the wafer.

[0048] Specifically, the semiconductor process equipment may further include a first gas source device 710, a second gas source device 720, a third gas source device 730, a fourth gas source device, a first source liquid device 740, and a vaporizer 750. The second gas source device 720 may be connected to the first source liquid device 740 through a second pipeline 902, the first source liquid device 740 may be connected to the vaporizer 750 through a third pipeline 903, the third gas source device 730 may be connected to the vaporizer 750 through a fourth pipeline 904, and the vaporizer 750 may be connected to the second gas inlet through a fifth pipeline 905. When the semiconductor process chamber performs a deposition process, the first gas source device 710 can be connected to the first gas inlet through the first pipeline 901, the first pipeline 901 and the fifth pipeline 905 can be alternately opened and closed, the second pipeline 902, the third pipeline 903 and the fourth pipeline 904 are all in an open state, and the first pipeline 901 and the fifth pipeline 905 can alternately pass the first precursor and the second precursor into the chamber body 100. When the semiconductor process chamber performs an etching process, the fourth gas source device can be connected to the first gas inlet through the first pipeline 901, the first pipeline 901 is in an open state, the fifth pipeline 905 is in a closed state, and the fourth gas source device can pass the etching gas into the chamber body 100 through the first pipeline 901.

[0049] Please refer to Fig. 9 and Fig.10 In order to improve the process efficiency of the semiconductor process equipment, the semiconductor process equipment may further include a first source liquid device 740, a vaporizer 750, a second source liquid device 760 and a condenser 810. The first source liquid device 740 may be connected to the vaporizer 750, and the first source liquid device 740 is vaporized into gas after passing through the vaporizer 750. The vaporizer 750 and the second source liquid device 760 are connected in parallel to the fifth pipeline 905, and the condenser 810 is disposed between the vaporizer 750 and the second source liquid device 760.

[0050] When the semiconductor process chamber performs a deposition process, the vaporizer 750 is connected to the fifth pipeline 905, and the vaporizer 750 is disconnected from the second source liquid device 760. The first pipeline 901 is used to transport the first precursor into the chamber body 100. The first source liquid device 740 is vaporized into gas after passing through the vaporizer 750 and enters the chamber body 100 through the fifth pipeline 905. The first source liquid device 740 is at least part of the gas that constitutes the second precursor.

[0051] When an etching process is performed in a semiconductor process chamber, the vaporizer 750 is disconnected from the fifth pipeline 905, and the vaporizer 750 is connected to the second source liquid device 760. The first pipeline 901 is used to transport etching gas into the chamber body 100. The first source liquid device 740 is vaporized into gas after passing through the vaporizer 750, and is liquefied into liquid after passing through the condenser 810 and stored in the second source liquid device 760.

[0052] The semiconductor process equipment disclosed in the embodiment of the present application is provided with a first source liquid device 740, a vaporizer 750, a second source liquid device 760 and a condenser 810, so that when a deposition process is performed in a semiconductor process chamber, the first pipeline 901 transports a first precursor into the chamber body 100, the first source liquid device 740 is vaporized into gas after passing through the vaporizer 750, and enters the chamber body 100 through the fifth pipeline 905, so that a deposition process is performed in the chamber body 100. When an etching process is performed in the semiconductor process chamber, the vaporizer 750 is disconnected from the fifth pipeline 905, the vaporizer 750 is connected to the second source liquid device 760, and the first pipeline 901 transports an etching gas into the chamber body 100, so that an etching process is performed in the chamber body 100. When the etching process is carried out in the semiconductor process chamber, the first source liquid device 740 is vaporized into gas after passing through the vaporizer 750, and is liquefied into liquid after passing through the condenser 810 and is stored in the second source liquid device 760. Therefore, the first source liquid device 740 is always in a conveying state. Therefore, when the deposition process begins after the etching process is completed, the time for the first source liquid device 740 to start conveying the source liquid can be reduced, thereby improving the process efficiency of the semiconductor process equipment. In addition, the second source liquid device 760 can also recycle the source liquid.

[0053] Specifically, the second source liquid device 760 is connected to the vaporizer 750 through the sixth pipeline 906, the condenser 810 is provided on the sixth pipeline 906, and the second source liquid device 760 is connected to the exhaust device 130 of the semiconductor process chamber through the second exhaust pipeline 9021. When the semiconductor process chamber performs a deposition process, the sixth pipeline 906, the first exhaust pipeline 9020, and the second exhaust pipeline 9021 are all in a closed state. When the semiconductor process chamber performs an etching process, the sixth pipeline 906 and the second exhaust pipeline 9021 are both in an open state, and the first exhaust pipeline 9020 is in a closed state.

[0054] Please refer to Fig.11 The semiconductor process equipment further includes a fifth gas source device 770, the fifth pipeline 905 includes a first sub-tube 905a and a second sub-tube 905b, the first end of the first sub-tube 905a is connected to the vaporizer 750, the second end of the first sub-tube 905a is connected to the first end of the second sub-tube 905b, the second end of the second sub-tube 905b is connected to the second gas inlet, and the fifth gas source device 770 is connected to the second sub-tube 905b through the seventh pipeline 907; When performing a deposition process or an etching process, the first pipeline 901 always has gas flowing into the chamber body 100, while the fifth pipeline only flows the second precursor during the deposition process. Since the second sub-tube 905b is close to the chamber body 100, the first precursor and the second precursor are easily deposited at the second sub-tube 905b, which causes the second precursor to be unable to flow into the chamber body 100, so the second sub-tube 905b needs to be purged. When the second sub-tube 905b is purged, the first pipeline 901 and the first exhaust pipeline 9020 are all in a closed state, the second pipeline 902, the third pipeline 903, the fourth pipeline 904, the sixth pipeline 906 and the second exhaust pipeline 9021 are all in an open state, the first sub-tube 905a is in a closed state, and the seventh pipeline 907 and the second sub-tube 905b are both in an open state.

[0055] Please refer to Fig.12 In order to replenish the source liquid to the first source liquid device 740 and prevent the second source liquid device 760 from being overfilled, the semiconductor process equipment may further include an eighth pipeline 908 and a ninth pipeline 909. The eighth pipeline 908 may be connected to the second source liquid device 760, and the second source liquid device 760 may be connected to the first source liquid device 740 through the ninth pipeline 909. When the semiconductor process equipment replenishes the first source liquid device 740, the eighth pipeline 908 may be used to pass gas into the second source liquid device 760 to drive the liquid in the second source liquid device 760 into the first source liquid device 740 through the ninth pipeline 909, so that the source liquid can be replenished to the first source liquid device 740 and the second source liquid device 760 can be prevented from being overfilled.

[0056] Optionally, both the first source liquid device 740 and the second source liquid device 760 may be provided with a high liquid level sensor and a low liquid level sensor. When the low liquid level sensor of the first source liquid device 740 is triggered or the high liquid level sensor of the second source liquid device 760 is triggered, the semiconductor process equipment enters a state of replenishing liquid to the first source liquid device 740.

[0057] Specifically, the semiconductor process equipment may also include a fifth gas source device 770, which can be connected to the second source liquid device 760 through an eighth pipeline 908. The fifth gas source device 770 can pass gas into the second source liquid device 760 through the eighth pipeline 908 to drive the liquid in the second source liquid device 760 into the first source liquid device 740 through the ninth pipeline 909.

[0058] Optionally, refer to Fig.13 and Fig.14The semiconductor process equipment may further include a first flow controller 780, which may be used to control the gas flow in the third pipeline 903. The inlet of the first flow controller 780 may be connected to the third pipeline 903, the outlet of the first flow controller 780 may be connected to the vaporizer 750 through the tenth pipeline 9010, the eighth pipeline 908 may be connected to the tenth pipeline 9010, the fifth gas source device 770 may be connected to the third pipeline 903 through the eleventh pipeline 9011, and the eighth pipeline 908 may be connected to the second source liquid device 760 through the tenth pipeline 9010 and the twelfth pipeline 9012; the semiconductor process equipment has a first sub-state and a second sub-state.

[0059] When the semiconductor process equipment is in the first sub-state, the eighth pipeline 908, the tenth pipeline 9010, the fourth pipeline 904, the sixth pipeline 906 and the second exhaust pipeline 9021 are all in an open state, and the other pipelines are all in a closed state. The purge gas blown out by the fifth gas source device 770 passes through the eighth pipeline 908 and the tenth pipeline 9010 in sequence and reaches the vaporizer 750. Then, together with the gas in the fourth pipeline 904, it enters the second source liquid device 760 through the sixth pipeline 906 and is discharged from the second exhaust pipeline 9021, so as to achieve the purge of the pipeline on the rear side of the first flow controller 780.

[0060] When the semiconductor process equipment is in the second sub-state, the eleventh pipeline 9011, the third pipeline 903 and the first exhaust pipeline 9020 are all in an open state, and the other pipelines are all in a closed state. The purge gas blown out by the fifth gas source device 770 passes through the eleventh pipeline 9011 and the third pipeline 903 in sequence into the first source liquid device 740 and is discharged from the first exhaust pipeline 9020 to purge the pipeline in front of the first flow controller 780.

[0061] It should be noted that when maintaining or replacing the first flow controller 780, it is necessary to purge the second precursor remaining in the pipelines on both sides of the first flow controller 780 to avoid harm to the human body. The first sub-state is to purge the rear pipeline of the first flow controller 780, and the second sub-state is to purge the front pipeline of the first flow controller 780.

[0062] Please refer to Fig.15 and Fig.16 In order to maintain and replace the vaporizer 750, it is necessary to purge the front and rear pipelines of the vaporizer 750 to prevent the residual gas from causing harm to the human body. Optionally, the fifth gas source device 770 can be connected to the sixth pipeline 906 through the thirteenth pipeline 9013, and the semiconductor process equipment has a third sub-state and a fourth sub-state.

[0063] When the semiconductor process equipment is in the third sub-state, the thirteenth pipeline 9013, the sixth pipeline 906 and the second exhaust pipeline 9021 are all in the open state, and the other pipelines are all in the closed state. The purge gas blown out by the fifth gas source device 770 passes through the thirteenth pipeline 9013, the sixth pipeline 906, the second source liquid device 760 and the second exhaust pipeline 9021 in sequence and then is discharged to purge the rear side pipeline of the vaporizer 750.

[0064] When the semiconductor process equipment is in the fourth sub-state, the eighth pipeline 908, the tenth pipeline 9010, the twelfth pipeline 9012 and the second exhaust pipeline 9021 are connected, and the other pipelines are in a closed state. The purge gas blown out by the fifth gas source device 770 passes through the eighth pipeline 908, the tenth pipeline 9010, the twelfth pipeline 9012, the second source liquid device 760 and the second exhaust pipeline 9021 in sequence and is then discharged to purge the front pipeline of the vaporizer 750.

[0065] Please refer to Fig.17 and Fig.18 When the first source liquid device 740 is replenished, replaced, or repaired, it is necessary to prevent the gas in the second gas source device 720 from entering the first source liquid device 740. In order to prevent the gas in the second gas source device 720 from entering the first source liquid device 740, optionally, the second pipeline 902 may include a third sub-tube 902a and a fourth sub-tube 902b, and the third pipeline 903 may include a fifth sub-tube 903a and a sixth sub-tube 903b. The second gas source device 720 may be connected to the first source liquid device 740 through the third sub-tube 902a and the fourth sub-tube 902b in sequence, and the first source liquid device 740 may be connected to the first flow controller through the fifth sub-tube 903a and the sixth sub-tube 903b in sequence. The third sub-tube 902a and the sixth sub-tube 903b may be connected through the fourteenth pipeline 9014, and the semiconductor process equipment has a fifth sub-state.

[0066] When the semiconductor process equipment is in the fifth sub-state, the third sub-tube 902a, the fourteenth pipeline 9014, the sixth sub-tube 903b, the tenth pipeline 9010, the twelfth pipeline 9012 and the second exhaust pipeline 9021 are all in the open state, and the other pipelines are in the closed state, thereby preventing the gas in the second gas source device 720 from entering the first source liquid device 740.

[0067] In another embodiment, when the semiconductor process equipment is in the sixth sub-state, the third sub-tube 902a, the fourteenth pipeline 9014, the sixth sub-tube 903b, the tenth pipeline 9010, the fourth pipeline 904, the sixth pipeline 906 and the second exhaust pipeline 9021 are all in an open state, and the other pipelines are all in a closed state, thereby preventing the gas in the second gas source device 720 from entering the first source liquid device 740.

[0068] Optionally, the fourth pipeline 904 may be provided with a second flow controller 790 , and the second flow controller 790 may control the flow of the gas in the fourth pipeline 904 .

[0069] Optionally, the second exhaust pipeline 9021 may be provided in the pressure detection device 820 , and the second exhaust pipeline 9021 is closed when the pressure of the second exhaust pipeline 9021 detected by the pressure detection device 820 is abnormal, thereby protecting the exhaust device 130 .

[0070] Optionally, the semiconductor process equipment may further include a heating element, which may be used to heat the fifth pipeline 905 , thereby preventing the gas from liquefying before entering the chamber body 100 and causing blockage of the fifth pipeline 905 .

[0071] Please refer to Fig.19 and Fig. 20 The semiconductor process equipment may include a splash-proof box 840 , which may be disposed in the second source liquid device 760 , and the top of the second source liquid device 760 may have an exhaust port 761 . The splash-proof box 840 may include an inner shell 841 and an outer shell 842. The inner shell 841 can be buckled on the exhaust port 761, and the outer shell 842 can be buckled on the inner shell 841, and a liquid storage space 844 is provided between the inner shell 841 and the inner shell 841. A first filter hole 841a is provided on the side wall of the inner shell 841 adjacent to the exhaust port 761, and a second filter hole 842a is provided on the side wall of the outer shell 842 adjacent to the exhaust port 761, and the second filter hole 842a is located on the side of the inner shell 841 away from the first filter hole 841a. The second exhaust pipeline 9021 is connected to the exhaust port 761, so that the first filter hole 841a, the liquid storage space 844 and the second filter hole 842a form a labyrinth channel, thereby better preventing the liquid in the second source liquid device 760 from entering the exhaust device 130, thereby protecting the exhaust device 130.

[0072] Furthermore, the bottom wall of the outer shell 842 opposite to the exhaust port 761 can be movably connected to the side wall of the outer shell 842, and a splash-proof liquid level sensor 843 can be set in the liquid storage space. When the liquid level in the liquid storage space triggers the splash-proof liquid level sensor 843, the bottom wall of the outer shell 842 can move relative to the side wall of the outer shell 842, so that the liquid in the liquid storage space 844 can flow back to the second source liquid device 760 through the side where the bottom wall of the outer shell 842 is located, thereby avoiding excessive liquid in the liquid storage space 844, which will cause the gas to be unable to be discharged through the channel of the liquid storage space 844.

[0073] It should be noted that the opening and closing of the pipelines involved in the semiconductor process equipment disclosed in the embodiments of the present application can be controlled by valves on the corresponding pipelines. The first precursor can be a Si-containing compound, and the second precursor can be oxygen. Of course, the first precursor and the second precursor can also be other types, which can be selected according to different process requirements.

[0074] It should be noted that the carrier gas and the gas vaporized by the first source liquid device 740 in the vaporizer 750 together form the second precursor. The fourth gas source device can be used to output etching gas. The fifth gas source device 770 is used to output purge gas, for example, the purge gas can be an inert gas such as nitrogen, which can be used to purge the pipeline.

[0075] The above embodiments of the present invention focus on the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. Considering the simplicity of the text, they will not be repeated here.

[0076] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A semiconductor process chamber, characterized in that: The chamber body (100) comprises a chamber body (100), a base (200) and a first liner (300), wherein the base (200) is arranged in the chamber body (100), the first liner (300) is movably arranged in the chamber body (100), and the first liner (300) is arranged around the base (200) and is located between the base (200) and the chamber body (100); When a deposition process is performed in the semiconductor process chamber, the first liner (300) moves to a first position, and at least a portion of the first liner (300) is higher than the supporting surface (201) of the base (200); When an etching process is performed in the semiconductor process chamber, the first liner (300) moves to a second position, and the first liner (300) is lower than the carrying surface (201) or flush with the carrying surface (201).

2. The semiconductor process chamber according to claim 1, characterized in that: The top wall (110) of the chamber body (100) is provided with a first air inlet hole, the side wall (120) of the chamber body (100) is provided with a second air inlet hole higher than the bearing surface (201), and the first liner (300) is provided with a first avoidance hole (301); When the semiconductor process chamber performs the deposition process, the second air inlet is opposite to the first avoidance hole (301), the first air inlet is used to introduce a first precursor, and the second air inlet is used to introduce a second precursor, and the first precursor and the second precursor perform the deposition process in the chamber body (100); When the etching process is performed in the semiconductor process chamber, the first liner (300) is located below the second gas inlet hole, and the first gas inlet hole is used to introduce etching gas.

3. The semiconductor process chamber according to claim 2, characterized in that: The semiconductor process chamber further comprises a gas emitter (400), and the first gas inlet hole and the second gas inlet hole are both provided with the gas emitter (400); When the deposition process is performed in the semiconductor process chamber, a first gap (101) is provided between the gas emitter (400) located at the second gas inlet hole and the opening of the first avoidance hole (301) facing the side wall (120).

4. The semiconductor process chamber according to claim 1, wherein: The first lining (300) comprises a main body (310), an inclined portion (320) and an extension portion (330), wherein the main body (310) is a cylindrical structure, the first end of the inclined portion (320) is connected to the first port of the main body (310), the second end of the inclined portion (320) is connected to the first end of the extension portion (330), the second end of the inclined portion (320) is inclined toward a side of a central axis of the cylindrical structure, the second end of the extension portion (330) extends toward a side where the central axis of the cylindrical structure is located, and the extension portion (330) is parallel to the bearing surface (201).

5. The semiconductor process chamber according to claim 4, characterized in that: When a deposition process is performed in the semiconductor process chamber, a second gap (102) is provided between the extension portion (330) and the top wall (110) of the chamber body (100); When the etching process is performed in the semiconductor process chamber, the extension portion (330) is located below the carrying surface (201) or is flush with the carrying surface (201).

6. The semiconductor process chamber according to claim 5, characterized in that: The base (200) comprises a base body (210) and a flow equalizer (220), the flow equalizer (220) being arranged around the base body (210) and located below the bearing surface (201), the flow equalizer (220) being provided with a plurality of flow equalizer holes distributed around the base body (210), and the chamber body (100) being provided with an exhaust hole, and the exhaust hole being located below the flow equalizer (220); When the etching process is performed in the semiconductor process chamber, a third gap (103) is provided between the extension portion (330) and the flow equalizer (220).

7. The semiconductor process chamber according to claim 5, characterized in that: In the radial direction of the bearing surface (201), the extension portion (330) covers the edge area of ​​the flow-uniform hole.

8. The semiconductor process chamber according to claim 1, wherein: The semiconductor process chamber further comprises a driving mechanism (500), wherein the driving mechanism (500) is arranged in the chamber body (100) and connected to the first liner (300), and is used for driving the first liner (300) to switch between the first position and the second position.

9. The semiconductor process chamber according to claim 8, characterized in that: There are a plurality of driving mechanisms (500), the base (200) comprises a base body (210) and a plurality of cantilevers (230), the plurality of cantilevers (230) are arranged around the base body (210) and correspond one to one with the plurality of driving mechanisms (500), at least one of the cantilevers (230) is connected to the chamber body (100), one end of the other cantilevers (230) is connected to the base body (210), and the other end is suspended and spaced apart from the chamber body (100), and the driving mechanism (500) is arranged on the cantilever (230); The first liner (300) is provided with a strip hole (311), the strip hole (311) extending along the direction in which the first liner (300) moves between the first position and the second position, and the cantilever (230) connected to the chamber body (100) passes through the strip hole (311).

10. The semiconductor process chamber according to claim 2, wherein: The semiconductor process chamber also includes a second liner (600), which is arranged in the chamber body (100) and is detachably arranged on the side wall (120). The second liner (600) is provided with a second avoidance hole (601). When the first liner (300) is moved to the first position, the second liner (600) is located between the first liner (300) and the chamber body (100), and the central axis of the second air inlet hole, the central axis of the first avoidance hole (301) and the central axis of the second avoidance hole (601) coincide with each other.

11. The semiconductor process chamber according to claim 2 or 10, characterized in that: The two openings of the first avoidance hole (301) are circular chamfered structures, and / or the two openings of the second avoidance hole (601) are circular chamfered structures.

12. A semiconductor process equipment, characterized in that: A semiconductor process chamber comprising the semiconductor process chamber according to any one of claims 1 to 11, a first pipeline (901) connected to the first gas inlet and a fifth pipeline (905) connected to the second gas inlet, wherein the first pipeline (901) is used to selectively pass a first precursor or an etching gas into the first gas inlet, and the fifth pipeline (905) is used to pass a second precursor; When the deposition process is performed in the semiconductor process chamber, the first pipeline (901) and the fifth pipeline (905) are alternately fed with the first precursor and the second precursor; When the etching process is performed in the semiconductor process chamber, the etching gas is introduced into the first pipeline (901).

13. The semiconductor process equipment according to claim 12, characterized in that: The semiconductor process equipment further comprises a first source liquid device (740), a vaporizer (750), a second source liquid device (760) and a condenser (810), wherein the first source liquid device (740) is connected to the vaporizer (750), the vaporizer (750) and the second source liquid device (760) are connected in parallel to the fifth pipeline (905), and the condenser (810) is arranged between the vaporizer (750) and the second source liquid device (760); When the deposition process is performed in the semiconductor process chamber, the vaporizer (750) is connected to the fifth pipeline (905), and the vaporizer (750) is disconnected from the second source liquid device (760); When the etching process is performed in the semiconductor process chamber, the vaporizer (750) is disconnected from the fifth pipeline (905), and the vaporizer (750) is connected to the second source liquid device (760).

14. The semiconductor process equipment according to claim 13, characterized in that: The semiconductor process equipment further comprises an eighth pipeline (908) and a ninth pipeline (909), wherein the eighth pipeline (908) is connected to the second source liquid device (760), and the second source liquid device (760) is connected to the first source liquid device (740) via the ninth pipeline (909); When the semiconductor process equipment replenishes the first source liquid device (740), the eighth pipeline (908) is used to introduce gas into the second source liquid device (760) to drive the liquid in the second source liquid device (760) into the first source liquid device (740) through the ninth pipeline (909).

15. The semiconductor process equipment according to claim 13, characterized in that: The semiconductor process equipment comprises a splash-proof box (840), the splash-proof box (840) is arranged in the second source liquid device (760), and the top of the second source liquid device (760) is provided with an exhaust port (761); The splash-proof box (840) comprises an inner shell (841) and an outer shell (842); the inner shell (841) is buckled on the exhaust port (761); the outer shell (842) is buckled on the inner shell (841) and has a liquid storage space (844) between the inner shell (841) and the outer shell (842); a first filter hole (841a) is provided on a side wall of the inner shell (841) adjacent to the exhaust port (761); a second filter hole (842a) is provided on a side wall of the outer shell (842) adjacent to the exhaust port (761); and the second filter hole (842a) is located on a side of the inner shell (841) away from the first filter hole (841a); and a second exhaust pipeline (9021) is connected to the exhaust port (761).

16. The semiconductor process equipment according to claim 15, characterized in that: The bottom wall of the outer shell (842) opposite to the exhaust port (761) is movably connected to the side wall of the outer shell (842), and a splash-proof liquid level sensor (843) is arranged in the liquid storage space. When the liquid level in the liquid storage space triggers the splash-proof liquid level sensor (843), the bottom wall of the outer shell (842) moves relative to the side wall of the outer shell (842), so that the liquid in the liquid storage space (844) flows back to the second source liquid device (760) through the side where the bottom wall of the outer shell (842) is located.

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