Wafer back alignment mark and manufacturing method thereof, and preparation method of semiconductor device
By making a tidal tract and insulating layer on the front of the wafer, and the deposition of thinning and metal layers on the back, the fabral backward marking is formed, which solves the lack of the position marking on the back. feasibility.
Patent Information
- Application Number
- CN202411461290.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-01-24
AI Technical Summary
When performing related process processes on the back of the wafer, the lack of effective wafer back face-to-position marking makes it difficult to achieve processes such as cutting and lithography.
By making a tunnel and insulating layer on the front of the wafer, and the thinning treatment of the wafer back, and the metal layer deposits, the insulation material in the edge area is revealed to form the position of the wafer back.
It provides the basis for performing processes such as cutting or photolithography on the back of the wafer, solves the problem of lack of alignment marks on the back, and improves the feasibility of the process.
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Figure CN119361577A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a wafer back side alignment mark and a manufacturing method thereof, a wafer back side cutting method, a wafer back side photolithography method, and a semiconductor device manufacturing method. Background Art
[0002] Wafer refers to the silicon chip used to make silicon semiconductor circuits. Its raw material is silicon. Silicon crystal rods are cut and polished into bare wafers with a thickness of about 1mm. The bare wafers are then made into wafers with chips through front-end and back-end processes and cut into dies in a certain way. The cut dies are packaged to form wafers, and finally the packaged chips are tested.
[0003] In wafer manufacturing processes, for example, wafer scribing or photolithography, corresponding alignment marks need to be set on the wafer.
[0004] Take wafer dicing as an example. In the chip packaging process, wafer dicing is an essential process. The whole wafer of the chip is divided into single dies according to the grain size and reserved dicing lanes. With the reduction of grain size and thickness and the reduction of wafer dicing lane width, the influence of dicing process on grain quality becomes more and more prominent.
[0005] Generally, the wafer is cut along the scribe line on the front side of the wafer to separate the chip from the wafer. However, in some special packaging processes, such as wafer level packaging (WLP), when the front side of the wafer is sealed with plastic or covered with other opaque materials, conventional scribe line on the front side of the wafer is very difficult; it is necessary to scribe from the back side of the wafer, but there is no scribe line on the back side of the wafer, so how to align the cutting knife on the back side of the wafer with the scribe line on the front side of the wafer becomes a difficult problem. Summary of the invention
[0006] In view of the above-mentioned deficiencies in the related technologies, the purpose of the present disclosure is to provide a wafer back side alignment mark and a method for making the same, a wafer back side cutting method, a wafer back side photolithography method, and a method for preparing a semiconductor device, so as to solve the problem in the related technologies of the lack of effective wafer back side alignment marks when performing related process technology on the back side of the wafer.
[0007] The first aspect of the present disclosure provides a method for manufacturing an alignment mark on the back side of a wafer, comprising the following steps:
[0008] Providing a wafer, wherein a die is arranged on the front side of the wafer;
[0009] Making a scribe line between the tube cores and an insulating layer covering the tube core and the scribe line on the front side of the wafer; wherein the depth of the scribe line is less than the first thickness;
[0010] Performing a first backside thinning process on the backside of the wafer to a first thickness, and forming a metal layer on the backside of the wafer after thinning; and
[0011] A second backside thinning process is performed on the edge area of the back side of the wafer to expose the insulating material in the scribe line in the edge area, so as to form a wafer backside alignment mark for wafer backside scribing or photolithography.
[0012] In some examples of the first aspect, the insulating material used for the insulating layer is resin, and the steps of making scribe lines between the tube cores and the insulating layer covering the tube cores and the scribe lines on the front side of the wafer include the following steps: making criss-cross scribe lines between the tube cores on the front side of the wafer, wherein the depth of the scribe lines is less than the first thickness; forming a resin layer covering the tube cores and the scribe lines on the front side of the wafer; and grinding the resin layer to expose the tube cores.
[0013] In certain examples of the first aspect, the insulating material used for the insulating layer is resin, and the steps of making scribe lines between the tube cores and the insulating layer covering the tube cores and the scribe lines on the front side of the wafer include the following steps: making conductive bumps on the bonding pads of the tube cores and making criss-cross scribe lines between the tube cores on the front side of the wafer, wherein the depth of the scribe lines is less than the first thickness; forming a resin layer covering the conductive bumps and the scribe lines on the front side of the wafer; and grinding the resin layer to expose the conductive bumps.
[0014] In some examples of the first aspect, the criss-crossing scribing streets between the tube cores are formed on the front side of the wafer by deep groove etching, laser scribing, or grinding wheel scribing.
[0015] In some examples of the first aspect, the edge region where the second back side thinning process is performed is a region within 4 mm from the outer edge of the wafer.
[0016] In some examples of the first aspect, forming a metal layer on the back side of the thinned wafer includes: depositing the metal layer on the back side of the wafer using a sputtering process or an evaporation process.
[0017] A second aspect of the present disclosure provides a wafer back side alignment mark, wherein the wafer back side alignment mark is manufactured on a wafer by the wafer back side alignment mark manufacturing method as described above.
[0018] A third aspect of the present disclosure provides a wafer cutting method, comprising the following steps:
[0019] Making a wafer back side alignment mark on the wafer by the wafer back side alignment mark making method as described above; and
[0020] The wafer back side alignment mark is used to perform dicing process from the back side of the wafer.
[0021] A fourth aspect of the present disclosure provides a wafer backside photolithography method, comprising the following steps:
[0022] Making a wafer back side alignment mark on the wafer by the wafer back side alignment mark making method as described above; and
[0023] The alignment mark on the back side of the wafer is used to perform photolithography processing from the back side of the wafer.
[0024] A fifth aspect of the present disclosure provides a method for preparing a semiconductor device, which comprises processing a wafer using the method for making a wafer back side alignment mark as described above.
[0025] The disclosed embodiment provides a wafer back side alignment mark with a front side covered with resin and a method for making the same, a wafer back side cutting method, a wafer back side photolithography method, and a method for preparing a semiconductor device. The method for making the wafer back side alignment mark includes: providing a wafer with a tube core arranged on the front side; making an insulating layer on the front side of the wafer that is connected to the scribe line and covers the tube core and the scribe line, and the depth of the scribe line is less than the first thickness; performing a first back side thinning process on the back side of the wafer to the first thickness, and making a metal layer on the back side of the thinned wafer; performing a second back side thinning process on the edge area of the back side of the wafer to expose the insulating material in the scribe line in the edge area, and forming a wafer back side alignment mark. In this way, the manufactured wafer back side alignment mark can be used to perform processes including wafer back side cutting or wafer back side photolithography on the back side of the wafer, thereby solving the problem of the lack of effective wafer back side alignment marks when performing related process technologies on the back side of the wafer in the related art. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a wafer back side alignment mark according to an embodiment of the present invention.
[0027] FIG. 2A to FIG. 11B Based on Figure 1 Schematic diagram of the structure of the method for making the alignment mark in each step.
[0028] Fig.12 Shown is a schematic flow chart of a wafer backside cutting method in one embodiment of the present invention.
[0029] Fig.13 Shown is a schematic flow chart of a wafer backside photolithography method in one embodiment of the present invention. DETAILED DESCRIPTION
[0030] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the information disclosed by the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in the present disclosure can also be modified or changed in various ways according to different viewpoints and application modules without departing from the spirit of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0031] The following is a detailed description of the embodiments of the present disclosure with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.
[0032] In the representations of the present disclosure, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or a group of embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present disclosure and the features of different embodiments or examples, unless they are mutually contradictory.
[0033] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of the present disclosure, "a group" means two or more, unless otherwise clearly and specifically defined.
[0034] In order to clearly describe the present disclosure, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.
[0035] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.
[0036] Although the terms first, second, etc. are used to represent various elements in this article in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate that there are the described features, steps, operations, elements, modules, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or a group of other features, steps, operations, elements, modules, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.
[0037] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present disclosure. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.
[0038] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with relevant technical literature and the message of the present disclosure, and shall not be overly interpreted as ideal or very formal meanings unless defined.
[0039] In the related art, alignment marks are mostly arranged on the front side of the wafer. When the front side of the wafer is sealed with plastic packaging material or covered with other opaque materials, conventional wafer front side scribing will be very difficult; it is necessary to scribing from the back side of the wafer, but there is no scribing track on the back side of the wafer, which makes it difficult to perform the corresponding process from the back side of the wafer.
[0040] The embodiments of the present disclosure provide a wafer back side alignment mark and a method for making the same, a wafer back side cutting method, a wafer back side photolithography method, and a method for preparing a semiconductor device. The method for making the wafer back side alignment mark comprises: providing a wafer with a tube core arranged on the front side; making a scribe line and an insulating layer covering the tube core and the scribe line on the front side of the wafer, wherein the depth of the scribe line is less than a first thickness; performing a first back side thinning treatment on the back side of the wafer to the first thickness, and making a metal layer on the back side of the thinned wafer; performing a second back side thinning treatment on the edge area of the back side of the wafer to expose the insulating material in the scribe line in the edge area, and forming a wafer back side alignment mark using the exposed insulating material. In this way, when the front side of the wafer is covered by, for example, an insulating layer or a dielectric layer, making it impossible to implement the manufacturing process from the front side of the wafer through the relevant front side alignment mark, the technical solution of the embodiment of the present invention is used to produce a back side alignment mark that can be visible on the back side of the wafer. The produced back side alignment mark can be used to perform processes including back side wafer cutting or back side wafer lithography on the back side of the wafer, thereby solving the problem of the lack of effective back side alignment marks on the back side of the wafer when performing relevant manufacturing processes.
[0041] On one hand, the present embodiment provides a method for manufacturing an alignment mark on the back side of a wafer, which is used to manufacture an alignment mark on a wafer that can be visible on the back side of the wafer.
[0042] See also Figure 1 , which is a schematic flow chart of a method for manufacturing a wafer back side alignment mark in one embodiment of the present invention.
[0043] like Figure 1 As shown, the method for making the wafer back side alignment mark in this embodiment may include the following steps:
[0044] Step S101, providing a wafer, with dies arranged on the front side of the wafer.
[0045] like Figure 2A and Figure 2B As shown, a wafer 100 is provided, and a die array is arranged on the front side of the wafer 100 , wherein the die array includes a plurality of regularly arranged dies 101 .
[0046] Step S103, forming scribe lines between the tube cores and an insulating layer covering the tube cores and the scribe lines on the front side of the wafer; wherein the depth of the scribe lines is less than the first thickness.
[0047] In some embodiments, the insulating material used for the insulating layer is resin, for example, epoxy resin.
[0048] In some embodiments, step S103 of forming scribe lines between the dies and an insulating layer covering the dies and the scribe lines on the front side of the wafer may further include the following steps:
[0049] Step S1031, making a scribe line 102 between the dies 101 on the front side of the wafer 100, forming a Figure 3A and Figure 3B The structure shown in FIG. 1 is a structure in which crisscrossing scribing lanes 102 are formed on the surface of the wafer 100 . Specifically, a horizontal scribing lane 102 can be formed between any two adjacent rows of tube cores 101 , and a vertical scribing lane 102 can be formed between any two adjacent columns of tube cores 101 .
[0050] In some embodiments, making crisscross scribing lanes between the dies on the front side of the wafer comprises the following steps: first, applying glue on the front side of the wafer, then performing deep groove etching to form scribing lanes on the front side of the wafer, or laser scribing or grinding wheel scribing.
[0051] In some embodiments, the depth of the dicing street 102 is less than the first thickness.
[0052] Step S1033, forming a resin layer 103 covering the die 101 and the dicing lanes 102 on the front side of the wafer 100, forming a Figure 4 The structure shown.
[0053] Step S1035, grinding the resin layer 103 until the tube core 101 is exposed, forming Figure 5 Thus, the resin filled in the dicing lane 102 can be used as a marker.
[0054] In some embodiments, a chemical mechanical polishing (CMP) process may be used to polish the wafer.
[0055] In some embodiments, step S103 of forming scribe lines between the dies and an insulating layer covering the dies and the scribe lines on the front side of the wafer may further include the following steps:
[0056] Step S1032, forming conductive bumps 104 on the bonding pads of the tube core 101 and forming scribe lines 102 between the tube cores 101 on the front side of the wafer 100, forming a Figure 6 The structure shown. Among them, making conductive bumps 104 on the bonding pads of the tube core 101 and making scribe lanes 102 between the tube cores 101 on the front side of the wafer 100 may include: first making conductive bumps 104 on the bonding pads of the tube core 101 and then making scribe lanes 102 between the tube cores 101 on the front side of the wafer 100, or first making scribe lanes 102 between the tube cores 101 on the front side of the wafer 100 and then making conductive bumps 104 on the bonding pads of the tube core 101.
[0057] In some embodiments, the conductive bumps 104 may be formed on the bonding pads of the die 101 by electroplating, chemical plating, or ball planting.
[0058] A crisscross scribe line 102 is formed on the surface of the wafer 100 . Specifically, a horizontal scribe line 102 can be formed between any two adjacent rows of dies 101 , and a vertical scribe line 102 can be formed between any two adjacent columns of dies 101 .
[0059] In some embodiments, the formation of criss-crossing scribing streets between the dies on the front side of the wafer may be achieved by processes such as deep groove etching, laser scribing, or grinding wheel scribing.
[0060] In some embodiments, the depth of the dicing street 102 is less than the first thickness.
[0061] Step S1034, forming a resin layer 103 covering the conductive bumps 104 and the scribe lines 102 on the front side of the wafer 100, forming a Figure 7 The structure shown.
[0062] Step S1035, grinding the resin layer 103 until the conductive bumps 104 are exposed, forming a Figure 8 Thus, the resin filled in the dicing lane 102 can be used as a marker.
[0063] In some embodiments, the resin layer may be polished by using a chemical mechanical polishing (CMP) process.
[0064] Conductive bumps 104 are formed on the tube core 101 and are used to protect the tube core 101 , so that when the resin layer 103 is subsequently ground, damage to the tube core 101 due to excessive grinding can be avoided.
[0065] Step S105 , performing a first backside thinning process on the backside of the wafer to a first thickness, and forming a metal layer on the backside of the thinned wafer.
[0066] In the following description, Figures 6 to 8 The structure in is used as an example to illustrate.
[0067] First, the back side of the wafer 100 is thinned to a first thickness to form a Fig. 9 The structure shown. Since the depth of the scribe line 102 is less than the first thickness, after the back side of the wafer 100 is thinned to the first thickness, the scribe line 102 will not be exposed. In some embodiments, a chemical mechanical polishing process (CMP) may be used to perform a first back side thinning process on the back side of the wafer. In some embodiments, an etching process may be used to perform a first back side thinning process on the back side of the wafer.
[0068] Next, a metal layer 105 is formed on the back of the thinned wafer 100 to form a Fig.10 In some embodiments, the metal layer may be formed on the surface of the back side of the wafer by using an evaporation process or a sputtering process.
[0069] Step S107 , performing a second backside thinning process on the edge region of the back side of the wafer to expose the insulating material in the scribe line in the edge region, and forming a wafer backside alignment mark.
[0070] The edge area is an area within 4 mm from the outer edge of the wafer.
[0071] The edge region of the back side of the wafer 100 is subjected to a second back side thinning process until the insulating material in the scribe line in the edge region is exposed, forming a wafer 100 having a back side thinning process. Fig.11A and Fig. 11B In some embodiments, a chemical mechanical polishing (CMP) process may be used to perform a second backside thinning process on the back side of the wafer. In some embodiments, an etching process may be used to perform a second backside thinning process on the back side of the wafer.
[0072] In this way, the lines formed by the insulating material in the dicing lanes exposed in the edge area on the back side of the wafer can be used as wafer back side alignment marks. Subsequently, the wafer can be subjected to back side dicing processing or back side photolithography processing and other processes based on the wafer back side alignment marks.
[0073] Taking the insulating material as resin as an example, the edge area on the back of the wafer 100 is subjected to a second back grinding until the resin layer 103 in the scribe line 102 in the edge area is exposed, and the resin texture formed by the resin in the scribe line in the edge area on the back of the wafer is used as a wafer back alignment mark.
[0074] The disclosed embodiment provides a method for making a back-side alignment mark of a wafer with a front-side covered resin, comprising: providing a wafer with a tube core arranged on the front side; making a scribe line and an insulating layer covering the tube core and the scribe line on the front side of the wafer, wherein the depth of the scribe line is less than a first thickness; performing a first back-side thinning process on the back side of the wafer to the first thickness, and making a metal layer on the back side of the thinned wafer; performing a second back-side thinning process on the edge area of the back side of the wafer to expose the insulating material in the scribe line in the edge area, and forming a back-side alignment mark of the wafer using the exposed insulating material. In this way, the manufactured back-side alignment mark of the wafer can be used to perform processes including back-side wafer cutting or back-side wafer lithography on the back side of the wafer, thereby solving the problem of the lack of effective back-side alignment marks of the wafer when performing related process technologies on the back side of the wafer in the related art.
[0075] On the other hand, the present embodiment provides a wafer back side alignment mark manufactured by the aforementioned wafer back side alignment mark manufacturing method. The wafer back side alignment mark can correspond to the dicing line on the front side of the wafer and can be visible on the back side of the wafer, so that it can be suitable for processes such as wafer back side cutting or wafer back side lithography performed from the back side of the wafer in the wafer-level packaging process.
[0076] Another aspect of this embodiment provides a wafer backside cutting method. Fig.12 , which is a schematic flow chart of the wafer backside cutting method in one embodiment.
[0077] like Fig.12 As shown, the wafer cutting method comprises the following steps:
[0078] Step S201, providing a wafer, with dies arranged on the front side of the wafer.
[0079] Step S203, forming scribe lines between the tube cores and an insulating layer covering the tube cores and the scribe lines on the front side of the wafer; wherein the depth of the scribe lines is less than the first thickness.
[0080] Step S205 , performing a first backside thinning process on the backside of the wafer to a first thickness, and forming a metal layer on the backside of the thinned wafer.
[0081] Step S207 , performing a second backside thinning process on the edge region of the back side of the wafer to expose the insulating material in the scribe line in the edge region, and forming a wafer backside alignment mark.
[0082] Step S209, using the alignment mark on the back side of the wafer, scribing is performed from the back side of the wafer.
[0083] The disclosed embodiment provides a method for cutting the back side of a wafer. First, a back side alignment mark that can be visible on the back side of the wafer is made on the wafer by the aforementioned method for making the back side alignment mark of the wafer. Subsequently, the back side alignment mark of the wafer can be used to perform a back side wafer slicing process from the back side of the wafer along the back side alignment mark of the wafer, thereby cutting and separating the individual tube cores on the wafer.
[0084] Another aspect of this embodiment provides a wafer backside photolithography method. Fig.13 , which is a schematic flow chart of the wafer backside photolithography method in one embodiment.
[0085] like Fig.13 As shown, the wafer cutting method comprises the following steps:
[0086] Step S301, providing a wafer, with dies arranged on the front side of the wafer.
[0087] Step S303, forming a scribe line between the tube cores and an insulating layer covering the tube cores and the scribe line on the front side of the wafer; wherein the depth of the scribe line is less than the first thickness.
[0088] Step S305 , performing a first backside thinning process on the backside of the wafer to a first thickness, and forming a metal layer on the backside of the thinned wafer.
[0089] Step S307 , performing a second backside thinning process on the edge region of the back side of the wafer to expose the insulating material in the scribe line in the edge region, and forming a wafer backside alignment mark.
[0090] Step S309 , using the alignment mark on the back side of the wafer, perform photolithography processing from the back side of the wafer.
[0091] The disclosed embodiment provides a wafer back side photolithography method, which firstly produces a wafer back side alignment mark visible on the back side of the wafer on the wafer by the aforementioned wafer back side alignment mark production method, and then the wafer back side alignment mark can be used to perform photolithography processing from the back side of the wafer.
[0092] Of course, the embodiments of the present disclosure may also provide a method for preparing a semiconductor device, wherein the method for preparing the semiconductor device includes the step of making a wafer back side alignment mark on the wafer using the aforementioned method for making a wafer back side alignment mark.
[0093] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the protection scope of the present disclosure.
Claims
1. A method for making a wafer back side alignment mark, characterized in that: The steps include: Providing a wafer, wherein a die is arranged on the front side of the wafer; Making a scribe line between the tube cores and an insulating layer covering the tube core and the scribe line on the front side of the wafer; wherein the depth of the scribe line is less than the first thickness; Performing a first backside thinning process on the backside of the wafer to a first thickness, and forming a metal layer on the backside of the wafer after thinning; and A second backside thinning process is performed on the edge area of the back side of the wafer to expose the insulating material in the scribe line in the edge area, so as to form a wafer backside alignment mark for wafer backside scribing or photolithography.
2. The method for manufacturing a wafer back side alignment mark according to claim 1, characterized in that: The insulating material used in the insulating layer is resin, and the steps of making a scribe line between the tube cores and an insulating layer covering the tube cores and the scribe line on the front side of the wafer include the following steps: Making crisscrossing scribing streets between the dies on the front side of the wafer, wherein the depth of the scribing streets is less than the first thickness; forming a resin layer covering the die and the dicing lanes on the front side of the wafer; as well as The resin layer is ground to reveal the die.
3. The method for manufacturing a wafer back side alignment mark according to claim 1, characterized in that: The insulating material used in the insulating layer is resin, and the steps of making a scribe line between the tube cores and an insulating layer covering the tube cores and the scribe line on the front side of the wafer include the following steps: Making conductive bumps on the bonding points of the tube core and making crisscrossing scribing lanes between the tube cores on the front side of the wafer, wherein the depth of the scribing lanes is less than the first thickness; forming a resin layer covering the conductive bumps and the scribe lines on the front side of the wafer; and The resin layer is ground to expose the conductive bumps.
4. The method for manufacturing a wafer back side alignment mark according to claim 2 or 3, characterized in that: The criss-crossing scribing paths between the tube cores are formed on the front side of the wafer by deep groove etching, laser scribing, or grinding wheel scribing.
5. The method for manufacturing a wafer back side alignment mark according to claim 1, characterized in that: The edge area where the second backside thinning process is performed is an area within 4 mm from the outer edge of the wafer.
6. The method for manufacturing a wafer back side alignment mark according to claim 1, characterized in that: The step of manufacturing the metal layer on the back side of the thinned wafer includes: depositing the metal layer on the back side of the wafer by using a sputtering process or an evaporation process.
7. A wafer back side alignment mark, characterized in that: The wafer back side alignment mark is manufactured on the wafer by the method for manufacturing the wafer back side alignment mark according to any one of claims 1 to 6.
8. A wafer backside cutting method, characterized in that: The steps include: Making a wafer back side alignment mark on the wafer by the method for making a wafer back side alignment mark according to any one of claims 1 to 6; and The wafer back side alignment mark is used to perform dicing process from the back side of the wafer.
9. A wafer backside photolithography method, characterized in that: The steps include: Making a wafer back side alignment mark on the wafer by the method for making a wafer back side alignment mark according to any one of claims 1 to 6; and The alignment mark on the back side of the wafer is used to perform photolithography processing from the back side of the wafer.
10. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises processing the wafer using the method for making the alignment mark on the back side of the wafer as claimed in any one of claims 1 to 6.