Wafer back alignment mark and manufacturing method thereof

Abstract

The embodiment of the invention provides a wafer back alignment mark, a manufacturing method of the wafer back alignment mark, a wafer back cutting method, a wafer back photoetching method and a preparation method of a semiconductor device. The manufacturing method comprises the following steps: providing a wafer of which the front surface is provided with a tube core and a scribing channel; a blind hole array corresponding to the scribing channels is manufactured in the edge area of the front face of the wafer, and the hole depth of blind holes is larger than the first thickness; thinning the middle region of the back surface of the wafer, and manufacturing a metal layer in the thinned middle region of the back surface of the wafer; and grinding the edge area of the back surface of the wafer to enable the blind hole array in the edge area to be completely exposed, and forming a wafer back surface alignment mark which is displayed on the back surface of the wafer and can be used for scribing or photoetching the back surface of the wafer. By means of the manufactured wafer back face alignment mark, processes including wafer back face cutting or wafer back face photoetching and the like can be executed on the back face of the wafer, and the problem that effective wafer back face alignment marks are lacked when related manufacturing processes are carried out on the back face of the wafer in the related technology is solved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a wafer back side alignment mark and a manufacturing method thereof, a wafer back side cutting method, a wafer back side photolithography method, and a semiconductor device manufacturing method. Background Art

[0002] Wafer refers to the silicon chip used to make silicon semiconductor circuits. Its raw material is silicon. Silicon crystal rods are cut and polished into bare wafers with a thickness of about 1mm. The bare wafers are then made into wafers with chips through front-end and back-end processes and cut into dies in a certain way. The cut dies are packaged to form wafers, and finally the packaged chips are tested.

[0003] In wafer manufacturing processes, for example, wafer scribing or photolithography, corresponding alignment marks need to be set on the wafer.

[0004] Take wafer dicing as an example. In the chip packaging process, wafer dicing is an essential process. The whole wafer of the chip is divided into single dies according to the grain size and reserved dicing lanes. With the reduction of grain size and thickness and the reduction of wafer dicing lane width, the influence of dicing process on grain quality becomes more and more prominent.

[0005] Generally, the wafer is cut along the scribe line on the front side of the wafer to separate the chip from the wafer. However, in some special packaging processes, such as wafer level packaging (WLP), due to the opaque epoxy resin covering, the scribe line on the front side of the wafer cannot be effectively identified when dicing on the front side of the wafer, making it difficult to align the scribe line. Therefore, it is necessary to start dicing from the back side of the wafer, but there is no scribe line on the back side of the wafer. How to align the cutting knife on the back side of the wafer with the scribe line on the front side of the wafer becomes a tricky problem. Summary of the invention

[0006] In view of the above-mentioned deficiencies in the related technologies, the purpose of the present disclosure is to provide a wafer back side alignment mark and a method for making the same, a wafer back side cutting method, a wafer back side photolithography method, and a method for preparing a semiconductor device, so as to solve the problem in the related technologies of the lack of effective wafer back side alignment marks when performing related process technology on the back side of the wafer.

[0007] The first aspect of the present disclosure provides a method for manufacturing an alignment mark on the back side of a wafer, comprising the following steps:

[0008] Providing a wafer, wherein a die and crisscrossing dicing lanes are arranged on the front side of the wafer;

[0009] Making a blind hole array corresponding to the scribe line at an edge region of the front side of the wafer, wherein the blind hole array includes at least two blind holes corresponding to each scribe line, and the hole depth of the blind hole is greater than the first thickness;

[0010] Thinning the middle area of ​​the back side of the wafer, and forming a metal layer in the middle area of ​​the back side of the wafer after thinning, wherein the thickness of the middle area after forming the metal layer is a first thickness; and

[0011] The edge area of ​​the back side of the wafer is ground to fully expose the blind hole array in the edge area, thereby forming a wafer back side alignment mark that is visible on the back side of the wafer and can be used for wafer dicing or photolithography.

[0012] In some examples of the first aspect, forming a blind hole array corresponding to the scribe line in the edge region of the front side of the wafer includes: forming at least two blind holes in the edge region of the front side of the wafer along each scribe line.

[0013] In some examples of the first aspect, forming the blind hole in the edge area of ​​the front side of the wafer is achieved by laser drilling or etching process.

[0014] In some examples of the first aspect, the edge area is an area within 4 mm from the outer edge of the wafer.

[0015] In some examples of the first aspect, forming a metal layer in a middle area of ​​the back side of the thinned wafer includes: depositing a metal layer in a patterned area on the back side of the wafer using a sputtering process or an evaporation process.

[0016] In some examples of the first aspect, after grinding the edge region of the back side of the wafer, a step height difference between the edge region of the wafer and a middle region of the wafer is less than or equal to 10 microns.

[0017] A second aspect of the present disclosure provides a wafer back side alignment mark, wherein the wafer back side alignment mark is manufactured on a wafer by the wafer back side alignment mark manufacturing method as described above.

[0018] The third aspect of the present disclosure provides a method for cutting the back side of a wafer, comprising the following steps: making a wafer back side alignment mark on the wafer by the method for making the wafer back side alignment mark as described above; and performing a dicing process on the back side of the wafer using the wafer back side alignment mark.

[0019] The fourth aspect of the present disclosure provides a wafer lithography method, comprising the following steps: making a wafer back side alignment mark on a wafer by the method for making a wafer back side alignment mark as described above; and performing lithography processing on the back side of the wafer using the wafer back side alignment mark.

[0020] A fifth aspect of the present disclosure provides a method for preparing a semiconductor device, which comprises processing a wafer using the method for making a wafer back side alignment mark as described above.

[0021] The embodiment of the present disclosure provides a wafer back side alignment mark and a method for making the same, a wafer back side cutting method, a wafer back side photolithography method, and a method for preparing a semiconductor device. The method for making the wafer back side alignment mark includes: providing a wafer, wherein the front side of the wafer is provided with a die and crisscrossing scribing lanes; making a blind hole array corresponding to the scribing lanes in the edge area of ​​the front side of the wafer, wherein each scribing lane includes at least two blind holes, and the hole depth of the blind hole is greater than the first thickness; thinning the middle area of ​​the back side of the wafer, and making a metal layer in the middle area of ​​the thinned back side of the wafer; grinding the edge area of ​​the back side of the wafer, so that the blind hole array in the edge area is completely exposed, forming a wafer back side alignment mark that appears on the back side of the wafer and can be used for wafer scribing or photolithography. In this way, the wafer back side alignment mark can be used to perform processes including wafer cutting or wafer photolithography on the back side of the wafer, thereby solving the problem of lack of effective wafer back side alignment mark when performing related process on the back side of the wafer in the related technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a wafer back side alignment mark according to an embodiment of the present invention.

[0023] FIG. 2A to FIG. 6B Based on Figure 1 Schematic diagram of the structure of the method for making the alignment mark on the back side of the wafer in each step.

[0024] Figure 7 Shown is a schematic flow chart of a wafer backside cutting method in one embodiment of the present invention.

[0025] Figure 8 The back side of the wafer cutting method disclosed in the present invention is shown as follows Figure 6B Schematic diagram of the structure of the dicing mark lines formed by the various through holes on the back side of the wafer.

[0026] Fig. 9 Shown is a schematic flow chart of a wafer backside photolithography method in one embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the information disclosed by the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in the present disclosure can also be modified or changed in various ways according to different viewpoints and application modules without departing from the spirit of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0028] The following is a detailed description of the embodiments of the present disclosure with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0029] In the representations of the present disclosure, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or a group of embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present disclosure and the features of different embodiments or examples, unless they are mutually contradictory.

[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of the present disclosure, "a group" means two or more, unless otherwise clearly and specifically defined.

[0031] In order to clearly describe the present disclosure, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0032] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0033] Although the terms first, second, etc. are used to represent various elements in this article in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate that there are the described features, steps, operations, elements, modules, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or a group of other features, steps, operations, elements, modules, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0034] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present disclosure. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0035] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with relevant technical literature and the message of the present disclosure, and shall not be overly interpreted as ideal or very formal meanings unless defined.

[0036] In the related art, the alignment marks are mostly arranged on the front side of the wafer. Because the back side of the wafer is sealed with plastic packaging material or covered with other opaque materials, it is quite difficult to perform the corresponding process from the back side of the wafer.

[0037] The disclosed embodiment provides a wafer back side alignment mark and a method for making the same, a wafer back side cutting method, a wafer back side photolithography method, and a method for preparing a semiconductor device. The method for making the wafer back side alignment mark includes: providing a wafer with a die and crisscrossing scribing lanes arranged on the front side; making a blind hole array corresponding to the scribing lanes in the edge area of ​​the front side of the wafer, wherein at least two blind holes are included corresponding to each scribing lane, and the hole depth of the blind hole is greater than a first thickness; thinning the middle area of ​​the back side of the wafer to a first thickness, and making a metal layer in the middle area of ​​the back side of the wafer after thinning; grinding the edge area of ​​the back side of the wafer to fully expose the blind hole array in the edge area to form a wafer back side alignment mark. In this way, the wafer back side alignment mark can be used to perform processes including wafer back side cutting or wafer back side photolithography on the back side of the wafer, thereby solving the problem of lack of effective wafer back side alignment mark when performing related process on the back side of the wafer in the related technology.

[0038] On one hand, the present embodiment provides a method for manufacturing a wafer back side alignment mark, which is used to manufacture a wafer back side alignment mark that can be visible on the back side of the wafer.

[0039] See also Figure 1 , which is a schematic flow chart of a method for manufacturing a wafer back side alignment mark in one embodiment of the present invention.

[0040] like Figure 1 As shown, the method for making the wafer back side alignment mark in this embodiment may include the following steps:

[0041] Step S101, providing a wafer, wherein the front side of the wafer is provided with dies and criss-crossing scribe lines.

[0042] like Figure 2A , providing a wafer 100, wherein the wafer 100 includes a middle area and an edge area surrounding the middle area. The edge area is an area within 4 mm from the outer edge of the wafer. Specifically, the edge area may be, for example, an annular area with a width of 4 mm, but is not limited thereto. The size of the edge area from the outer edge of the wafer may still be changed in other ways.

[0043] A die array is arranged in the device region on the front side of the wafer. The die array includes a plurality of regularly arranged die 101 . Slicing lanes 102 are arranged between adjacent die 101 , thereby forming crisscrossing slicing lanes 102 .

[0044] Step S103, making a blind hole array corresponding to the scribe line in the edge area of ​​the front side of the wafer, wherein the blind hole array includes at least two blind holes corresponding to each scribe line, and the hole depth of the blind hole is greater than the first thickness.

[0045] like Figure 3A and Figure 3B As shown, a blind hole array corresponding to the scribe line 102 is made in the edge area of ​​the front side of the wafer 100, wherein the blind hole array includes at least two blind holes 103 corresponding to each scribe line 102, that is, there are at least two blind holes 103 along each scribe line or its extension line.

[0046] Therefore, in step S103, making a blind hole array corresponding to the scribe line in the edge region of the front side of the wafer includes: making at least two blind holes in the edge region of the front side of the wafer along each scribe line.

[0047] In some embodiments, the blind hole is formed in the edge area of ​​the front side of the wafer by laser drilling or etching process, and the blind hole has a preset hole depth and hole diameter, wherein the hole depth of the blind hole is greater than the first thickness, and the hole diameter of the blind hole can be equivalent to the width of the dicing street, for example, the hole diameter of the blind hole can be greater than or equal to the width of the dicing street, or the hole diameter of the blind hole can be less than or equal to the width of the dicing street.

[0048] Step S105 , thinning the middle area of ​​the back side of the wafer, and forming a metal layer in the middle area of ​​the back side of the wafer after thinning, wherein the thickness of the middle area after forming the metal layer is a first thickness.

[0049] Furthermore, the step S105 may further include the following steps:

[0050] First, the middle area of ​​the back side of the wafer 100 is thinned to form a Figure 4A The cross-sectional structure shown.

[0051] After the middle area of ​​the back side of the wafer 100 is thinned, the back side of the wafer 100 can be observed as follows: Figure 4B The structure shown.

[0052] Next, a metal layer 104 is formed in the middle area of ​​the back side of the thinned wafer 100 to form a Figure 5A The cross-sectional structure shown.

[0053] In some embodiments, the metal layer may be formed on the surface of the middle area of ​​the back side of the wafer by using an evaporation process or a sputtering process.

[0054] It should be noted that the thickness of the middle region after the metal layer is formed is the first thickness, that is, the sum of the thickness of the middle region after the thinning process and the thickness of the metal layer is the first thickness.

[0055] After the metal layer 104 is formed on the middle area of ​​the back side of the wafer 100, the back side of the wafer can be observed as follows: Figure 5B The structure shown.

[0056] Step S107 , grinding the edge area of ​​the back side of the wafer to fully expose the blind hole array in the edge area, thereby forming an alignment mark on the back side of the wafer.

[0057] like Fig. 6A As shown in the cross-sectional structure, the edge area of ​​the back side of the wafer 100 is ground until the bottom of each blind hole of the blind hole array is ground away, so that each blind hole is opened after grinding to form a through hole and is exposed.

[0058] After grinding the edge area of ​​the back side of the wafer 100 until each through hole is exposed, the back side of the wafer can be observed as follows: Figure 6B The structure shown.

[0059] It is worth noting that when grinding the edge area of ​​the back side of the wafer 100, in order to avoid damaging the metal layer 104 made in the layout area on the back side of the wafer 100, the grinding will not touch the metal layer 104, and the thickness of the edge area of ​​the back side of the wafer 100 after grinding should be greater than the first thickness. Specifically, when observed from the back side of the wafer 100, the edge area of ​​the back side of the wafer 100 after grinding should protrude from the metal layer 104, that is, there is a step between the edge area of ​​the back side of the wafer 100 after grinding and the metal layer 104. In some examples, the step height difference is, for example, less than or equal to 10 microns (e.g., Fig. 6A as shown).

[0060] In this way, the through holes formed after the blind holes exposed in the edge area on the back side of the wafer are opened can be used as wafer back side alignment marks. Subsequently, based on the wafer back side alignment marks, the wafer can be subjected to processes such as wafer back side scribing or wafer back side lithography.

[0061] The disclosed embodiment provides a method for making a wafer back side alignment mark, including: providing a wafer with a die and crisscrossing scribing lanes arranged on the front side; making a blind hole array corresponding to the scribing lanes in the edge area of ​​the front side of the wafer, wherein the hole depth of each blind hole in the blind hole array is greater than a first thickness; thinning the middle area of ​​the back side of the wafer, and making a metal layer in the middle area of ​​the thinned back side of the wafer, wherein the thickness of the middle area after making the metal layer is the first thickness; grinding the edge area of ​​the back side of the wafer, so that the blind hole array in the edge area is completely exposed, forming a wafer back side alignment mark that appears on the back side of the wafer. In this way, the manufactured wafer back side alignment mark can be used to perform processes including wafer cutting or wafer lithography on the back side of the wafer, thereby solving the problem of the lack of effective wafer back side alignment marks when performing related process technologies on the back side of the wafer in the related art.

[0062] On the other hand, the present embodiment provides a wafer back side alignment mark manufactured by the aforementioned wafer back side alignment mark manufacturing method. The wafer back side alignment mark can correspond to the dicing line on the front side of the wafer and can be visible on the back side of the wafer, so that it can be suitable for processes such as wafer back side cutting or wafer back side lithography performed from the back side of the wafer in the wafer-level packaging process.

[0063] Another aspect of this embodiment provides a wafer backside cutting method. Figure 7 , which is a schematic flow chart of the wafer backside cutting method in one embodiment.

[0064] like Figure 7 As shown, the wafer backside cutting method comprises the following steps:

[0065] Step S201, providing a wafer, wherein the front side of the wafer is provided with dies and criss-crossing scribe lines.

[0066] Step S203, making a blind hole array corresponding to the scribe line in the edge area of ​​the front side of the wafer, wherein the blind hole array includes at least two blind holes corresponding to each scribe line, and the hole depth of the blind hole is greater than the first thickness.

[0067] Step S205 , thinning the middle area of ​​the back side of the wafer, and forming a metal layer in the middle area of ​​the back side of the wafer after thinning, wherein the thickness of the middle area after forming the metal layer is a first thickness.

[0068] Step S207 , grinding the edge area of ​​the back side of the wafer to fully expose the blind hole array in the edge area, thereby forming an alignment mark on the back side of the wafer.

[0069] Step S209, using the alignment mark on the back side of the wafer, scribing is performed from the back side of the wafer.

[0070] In step S209, if Figure 8 As shown, the through holes exposed on the back side of the wafer 100 are used as alignment marks for the back side of the wafer. These through holes are used to connect the corresponding through holes in the vertical and horizontal positions to form straight lines, so that criss-crossing scribe marking lines 105 that are consistent with the scribe lanes on the front side of the wafer 100 can be formed on the back side of the wafer 100. These criss-crossing scribe marking lines 105 can be used to perform back-side scribe processing on the wafer subsequently, thereby cutting and separating the individual tube cores on the wafer.

[0071] Another aspect of this embodiment provides a wafer backside photolithography method. Fig. 9 , which is a schematic diagram of the process of the wafer back side lithography method in one embodiment.

[0072] like Fig. 9 As shown, the wafer backside photolithography method comprises the following steps:

[0073] Step S301, providing a wafer, wherein the front side of the wafer is provided with dies and criss-crossing scribe lines.

[0074] Step S303, making a blind hole array corresponding to the scribe line in the edge area of ​​the front side of the wafer, wherein the blind hole array includes at least two blind holes corresponding to each scribe line, and the hole depth of the blind hole is greater than the first thickness.

[0075] Step S305 , thinning the middle area on the back side of the wafer, and forming a metal layer in the middle area on the back side of the wafer after thinning, wherein the thickness of the middle area after forming the metal layer is a first thickness.

[0076] Step S307 , grinding the edge area of ​​the back side of the wafer to fully expose the blind hole array in the edge area, thereby forming an alignment mark on the back side of the wafer.

[0077] Step S309 , using the alignment mark on the back side of the wafer, perform photolithography processing from the back side of the wafer.

[0078] Of course, the embodiments of the present disclosure may also provide a method for preparing a semiconductor device, wherein the method for preparing the semiconductor device includes the step of making a wafer back side alignment mark on the wafer using the aforementioned method for making a wafer back side alignment mark.

[0079] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the protection scope of the present disclosure.

Claims

1. A method for making a wafer back side alignment mark, characterized in that: The steps include: Providing a wafer, wherein a die and crisscrossing dicing lanes are arranged on the front side of the wafer; Making a blind hole array corresponding to the scribe line at an edge region of the front side of the wafer, wherein the blind hole array includes at least two blind holes corresponding to each scribe line, and the hole depth of the blind hole is greater than the first thickness; Thinning the middle area of ​​the back side of the wafer, and forming a metal layer in the middle area of ​​the back side of the wafer after thinning, wherein the thickness of the middle area after forming the metal layer is a first thickness; and The edge area of ​​the back side of the wafer is ground to fully expose the blind hole array in the edge area, thereby forming a wafer back side alignment mark that is visible on the back side of the wafer and can be used for wafer dicing or photolithography.

2. The method for manufacturing a wafer back side alignment mark according to claim 1, characterized in that: Producing a blind hole array corresponding to the scribe line in the edge area of ​​the front side of the wafer comprises: At least two blind holes are formed in the edge area of ​​the front side of the wafer along each scribe line.

3. The method for manufacturing a wafer back side alignment mark according to claim 1 or 2, characterized in that: The blind holes are formed in the edge area of ​​the front side of the wafer by laser drilling or etching process.

4. The method for manufacturing a wafer back side alignment mark according to claim 2 or 3, characterized in that: The edge area is the area within 4 mm from the outer edge of the wafer.

5. The method for manufacturing a wafer back side alignment mark according to claim 1, characterized in that: The method of manufacturing a metal layer in the middle area of ​​the back side of the thinned wafer includes: depositing the metal layer in the pattern area of ​​the back side of the wafer by using a sputtering process or an evaporation process.

6. The method for manufacturing a wafer back side alignment mark according to claim 1, characterized in that: After grinding the edge area of ​​the back side of the wafer, the step height difference between the edge area of ​​the wafer and the middle area of ​​the wafer is less than or equal to 10 microns.

7. A wafer back side alignment mark, characterized in that: The wafer back side alignment mark is manufactured on the wafer by the method for manufacturing the wafer back side alignment mark according to any one of claims 1 to 6.

8. A wafer backside cutting method, characterized in that: The steps include: Making a wafer back side alignment mark on the wafer by the method for making a wafer back side alignment mark according to any one of claims 1 to 6; and The wafer back side is used for dicing by utilizing the alignment mark on the wafer back side.

9. A wafer backside photolithography method, characterized in that: The steps include: Making a wafer back side alignment mark on the wafer by the method for making a wafer back side alignment mark according to any one of claims 1 to 6; and The alignment mark on the back side of the wafer is used to perform photolithography processing on the back side of the wafer.

10. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises processing the wafer using the method for making a wafer back side alignment mark according to any one of claims 1 to 6.

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