An inverter system with enhanced anti-reverse flow adaptability architecture

Abstract

The present application discloses an anti-backflow adaptability enhancement architecture for an inverter system, including a load imbalance enhancement module, a collection module, and a switch circuit; the switch circuit is built into a three-phase four-wire inverter system and connected to a DC side bus through a first end, and the load imbalance enhancement module is connected to a second end of the switch circuit through a three-phase connection end; the collection module is suitable for collecting the zero-line current of the inverter system to determine whether the load imbalance current exceeds a set threshold; when the load imbalance current exceeds the set threshold, the switch circuit is turned on so that the load imbalance enhancement module is connected to the inverter system to increase the equivalent DC bus capacitance. Beneficial effects of the present application: by introducing an external load imbalance enhancement module, the adaptability of the inverter system under unbalanced load conditions can be significantly improved; and the current impact when the external capacitor is connected can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of renewable energy power generation, and in particular to an inverter system architecture with enhanced anti-backflow adaptability. Background Art

[0002] In the design of photovoltaic systems, in order to improve the ability to cope with unbalanced three-phase loads in anti-backflow scenarios, a common practice is to upgrade the traditional three-phase three-wire system to a three-phase four-wire system. The introduction of the neutral line does enhance the system's ability to cope with unbalanced loads to a certain extent, but in practical applications, the system still has inherent limitations.

[0003] For example, when the three-phase load is in a balanced state, the current in the neutral line is almost zero. At this time, the bus capacitor is mainly responsible for stabilizing the DC bus voltage and suppressing the voltage fluctuation caused by the inverter switching action. In view of this, in the planning stage of system design, it is usually preferred to select a bus capacitor with a relatively small capacity to ensure that the system can perform well under the three-phase load balance state and meet a certain degree of unbalanced load operation requirements.

[0004] However, in actual applications, the degree to which the three-phase load deviates from the balanced state is often difficult to accurately estimate. Since the actual conditions of various unbalanced loads were not fully considered in the early design, the selected bus capacitor capacity is often unable to fully absorb and balance these additional currents. Especially in the case of severe imbalance of three-phase loads, the bus capacitor may not be able to be effectively regulated, resulting in significant fluctuations in the DC bus voltage, and in severe cases may even affect the stable operation of the inverter. Therefore, the insufficient capacity of the bus capacitor has become an important factor restricting the system's ability to adapt to unbalanced loads in anti-backflow scenarios, further limiting the overall performance of the system. Summary of the invention

[0005] One of the objectives of the present application is to provide an inverter system anti-backflow adaptability enhanced architecture that can solve at least one of the defects in the above-mentioned background technology.

[0006] In order to achieve at least one of the above-mentioned purposes, the technical solution adopted in the present application is: an inverter system anti-backflow adaptability enhanced architecture, including a load imbalance enhancement module, a collection module and a switching circuit; the switching circuit is built into a three-phase four-wire inverter system and connected to the DC side bus through a first end, and the load imbalance enhancement module is connected to the second end of the switching circuit through a three-phase connection end; the collection module is suitable for collecting the neutral line current of the inverter system to determine whether the load imbalance current exceeds a set threshold; when the load imbalance current exceeds the set threshold, the switching circuit is turned on so that the load imbalance enhancement module is connected to the inverter system to increase the equivalent DC bus capacitance.

[0007] Preferably, the load imbalance enhancement module includes a capacitor unit, a protection circuit and an auxiliary power supply; the capacitor unit is suitable for being connected to the switching circuit; the protection circuit is installed between the capacitor unit and the switching circuit, and the protection circuit is suitable for suppressing the impact current generated when the switching circuit is turned on; the auxiliary power supply is suitable for drawing power from the inverter system through the switching circuit, thereby powering the internal devices of the load imbalance enhancement module.

[0008] Preferably, the capacitor units are divided into two groups connected in series, and the two groups of capacitor units are respectively connected in parallel to the positive half bus and the auxiliary half bus of the inverter system through the switching circuit; the protection circuit adopts a shunt circuit, and the two groups of capacitor units are connected to one side of the inverter system bus and are connected to the switching circuit through the shunt circuit, and the shunt circuit is suitable for shunting the impact current generated when the switching circuit is turned on.

[0009] Preferably, the shunt circuit includes a current limiting resistor and a control switch; the current limiting resistor is connected in series between the capacitor unit and the switch circuit, and the control switch is connected in parallel to the current limiting resistor; the control switch is suitable for disconnecting when the switch circuit is turned on; the control switch is suitable for closing after the switch circuit is turned on for a set time.

[0010] Preferably, the capacitor units are divided into two groups connected in series, and the two groups of capacitor units are respectively connected in parallel to the positive half bus and the secondary half bus of the inverter system through the switching circuit; the protection circuit adopts a discharge circuit, and the discharge circuit is connected in parallel to the two groups of capacitor units, and the discharge circuit is suitable for discharging the bus voltage of the inverter system when the switching circuit is turned on.

[0011] Preferably, the discharge circuit includes a resistor string, a first control switch and a second control switch; a discharge branch formed by connecting the resistor string and the second control switch in series is connected in parallel to two groups of capacitor units; the first control switch is connected in series between one side of each group of capacitor units corresponding to the connection bus and a connection point of the discharge branch; the first control switch is suitable for being disconnected when the switch circuit is turned on, and at this time the second control switch is closed to connect the resistor string to the inverter system; after the resistor string is connected for a set time, the first control switch is closed first, and then the second control switch is disconnected.

[0012] Preferably, the auxiliary power supply adopts an isolated DC / DC architecture, and the auxiliary power supply includes a corresponding main coil and multiple secondary coils; the main coil is suitable for being connected to the switching circuit through a DC / DC module, and each secondary coil has a different turns ratio with the main coil, so that each secondary coil outputs a different supply voltage.

[0013] Preferably, the load imbalance enhancement module includes a capacitor unit, and the capacitor unit is divided into two groups connected in series, and the two groups of capacitor units are respectively connected in parallel to the positive half bus and the auxiliary half bus of the inverter system through the switch circuit; when the load unbalanced current exceeds a set threshold, before the switch circuit is closed, the power generation unit of the inverter system is first cut off and the grid-connected switch is disconnected, so that the functional unit connected through the inverter system discharges the bus capacitor; after completing the voltage discharge of the bus capacitor, the switch circuit is closed and the power generation unit is reconnected and the grid-connected switch is closed.

[0014] Preferably, the inverter system is suitable for discharging the bus voltage through a load.

[0015] Preferably, the acquisition module is suitable for directly acquiring current from the neutral line of the inverter system; or, the acquisition module is suitable for acquiring three-phase current on the AC side of the inverter system, and then calculating the neutral line current.

[0016] Compared with the prior art, the beneficial effects of this application are:

[0017] By introducing an external load imbalance enhancement module, the adaptability of the inverter system under unbalanced load conditions can be significantly improved; and the current impact when the external capacitor is connected can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the overall architecture of this application.

[0019] Figure 2 This is a structural diagram of Example 1 of the load imbalance enhancement module in the present application.

[0020] Figure 3 It is a schematic diagram of the structure of the auxiliary power supply in this application.

[0021] Figure 4 For this application Figure 2 A schematic diagram showing the relationship between the voltage of the capacitor unit and the driving signal in the load imbalance enhancement module is shown.

[0022] Figure 5 For this application Figure 2 The flowchart of the load imbalance enhancement module is shown.

[0023] Figure 6 For this application Figure 5 Schematic diagram of device-level signals at various stages in the workflow shown.

[0024] Figure 7 This is a schematic diagram of the workflow of the present application for accessing a load imbalance enhancement module based on voltage discharge.

[0025] Figure 8 This is a structural diagram of Embodiment 2 of the load imbalance enhancement module in the present application.

[0026] Fig. 9 For this application Figure 8 The flowchart of the load imbalance enhancement module is shown.

[0027] Fig.10 For this application Fig. 9 Schematic diagram of device-level signals at various stages in the workflow shown.

[0028] Fig.11 This is a structural diagram of Example 3 of the load imbalance enhancement module in this application.

[0029] Fig.12 For this application Fig.11 The flowchart of the load imbalance enhancement module is shown.

[0030] Fig.13 For this application Fig.12 Schematic diagram of device-level signals at various stages in the workflow shown.

[0031] Fig.14 This is a schematic diagram of the working process of the control loop of this application after the load imbalance enhancement module is connected.

[0032] In the figure: an inverter system 100 , a switch circuit 101 , a neutral line 102 , a load imbalance enhancement module 200 , a shunt circuit 201 , an auxiliary power supply 202 , a discharge circuit 203 , and a collection module 300 . DETAILED DESCRIPTION

[0033] Below, the present application is further described in conjunction with specific implementation methods. It should be noted that in the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily being directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0034] In the description of the present application, it should be noted that directional words, such as the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating directions and positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of narrating the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and cannot be understood as limiting the specific scope of protection of the present application.

[0035] It should be noted that the terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0036] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be connected, detachably connected, or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0037] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0038] The terms "including" and "having" and any variations thereof in the specification and claims of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0039] One of the preferred embodiments of the present application is as follows: Figure 1 As shown, an inverter system anti-reverse current adaptability enhancement architecture includes a load imbalance enhancement module 200, a collection module 300 and a switch circuit 101. The switch circuit 101 is built into the three-phase four-wire inverter system 100 and is connected to the DC side bus through the first end. The load imbalance enhancement module 200 is connected to the second end of the switch circuit 101 through the three-phase connection end. The collection module 300 can collect the neutral line current of the inverter system 100 to determine whether the load imbalance current exceeds the set threshold. When the load imbalance current exceeds the set threshold, the switch circuit 101 is turned on so that the load imbalance enhancement module 200 is connected to the inverter system 100 to increase the equivalent DC bus capacitance.

[0040] It should be known that the inverter system 100 follows the principle of "self-generation for self-use, and the surplus is not connected to the grid" during actual use; that is, the electric energy generated by the inverter system 100 gives priority to meeting the local load demand, and the excess electric energy is prohibited from being reversely fed into the grid. This function is also the anti-backflow function of the inverter system 100. In the design of the conventional three-phase four-wire inverter system 100, if the imbalance degree of the three-phase load exceeds a certain threshold, such as 20%, the DC side bus voltage of the inverter system 100 will fluctuate significantly. In other words, the severe three-phase load imbalance and the relatively insufficient capacity of the bus capacitor restrict the imbalance adjustment ability of the system. This phenomenon not only reduces the operating efficiency of the inverter system 100, but may also aggravate the instability of the inverter system 100, thereby affecting the anti-backflow function of the inverter system 100.

[0041] Therefore, when configuring the three-phase four-wire inverter system 100, the impact of load imbalance on the DC bus voltage stability must be considered. In the design stage, it is particularly important to reasonably determine the capacity of the bus capacitor. On the one hand, capacitor redundancy caused by over-design should be avoided to improve the economy and resource utilization efficiency of the system; on the other hand, it is necessary to ensure that the capacitor capacity can effectively meet the regulation requirements of the system under various load imbalance conditions, so as to fully guarantee the overall performance and stability of the system.

[0042] Therefore, in this embodiment, a load imbalance enhancement module 200 is provided, and the load imbalance enhancement module 200 can be connected to the switch circuit 101 built into the inverter system 100. When the load imbalance of the inverter system 100 is low, the switch circuit 101 can keep the load imbalance enhancement module 200 disconnected; only when the load imbalance of the inverter system 100 is high, the switch circuit 101 will be turned on to connect the load imbalance enhancement module 200 to the inverter system 100 to increase the equivalent DC bus capacitance, thereby significantly enhancing the inverter system 100's ability to regulate the bus voltage to expand the adaptability of the anti-backflow function.

[0043] It should be noted that the load power of the inverter system 100 is variable, that is, as the load access amount of the inverter system 100 increases, its load imbalance will change. Therefore, the load imbalance enhancement module 200 can be set as an optional module. When the load imbalance of the system is low, the inverter system 100 does not need the load imbalance enhancement module 200, which can ensure the economy of the inverter system 100. When the load imbalance of the inverter system 100 exceeds the processing capacity of the inverter system 100, the load imbalance enhancement module 200 needs to be selected. Therefore, when designing the inverter system 100, the inverter system 100 can be built-in with a switch circuit 101, and the switch circuit 101 has a three-phase interface; when the load imbalance enhancement module 200 needs to be selected, it is only necessary to connect the three-phase connection end of the load imbalance enhancement module 200 to the three-phase interface of the switch circuit 101.

[0044] In this embodiment, Figure 1As shown, in the three-phase four-wire inverter system 100, the connection of the neutral line 102 is to improve the load unbalance capability of the inverter system 100, so the neutral line current corresponding to the neutral line 102 is the load unbalance current. Therefore, the load unbalance degree of the inverter system 100 can be determined by comparing the neutral line current value with the set threshold. That is, once it is found that the three-phase load of the inverter system 100 is unbalanced, that is, there is current on the neutral line 102, the inverter system 100 will immediately enter the evaluation stage, at which time the acquisition module 300 can collect the current of the neutral line 102 to determine whether the load unbalance current exceeds the set threshold, and if it exceeds, the switch circuit 101 is controlled to be turned on to connect the load unbalance enhancement module 200; otherwise, the switch circuit 101 remains disconnected.

[0045] It should be known that, for the collection of the neutral line current, the collection module 300 can directly collect the current from the neutral line 102 of the inverter system 100; that is, the collection module 300 is connected to the neutral line 102 through a current sensor to collect the current on the neutral line 102 in real time. Of course, the neutral line current can also be collected through the three-phase circuit i on the AC side of the inverter system 100. a 、i b and i c The acquisition module 300 can also acquire the three-phase current of the AC side of the inverter system 100 through calculation; that is, the acquisition module 300 is connected to the three-phase circuit of the AC side of the inverter system 100 through the current sensor to acquire the three-phase current in real time. The specific structure and working principle of the current sensor are well-known technologies for those skilled in the art, so they are not elaborated in detail here; the current sensor of the scene includes a Hall sensor, etc.

[0046] In this embodiment, the switch circuit 101 has multiple specific structures. For ease of understanding, one of the structures will be described in detail below. Figure 1 As shown, the switch circuit 101 includes three control switches and three interfaces; the three control switches are defined as switches S a , S b and S c , the three interfaces are defined as interfaces a', b' and c'. Switch S a Installed between the DC side positive bus and the interface a' of the inverter system 100, the switch S b Installed between the DC bus midpoint of the inverter system 100 and the interface b', the switch S c Installed between the negative busbar on the DC side of the inverter system 100 and the interface c'. When the load imbalance enhancement module 200 is installed, the load imbalance enhancement module 200 is connected to the interfaces a', b' and c' of the switch circuit 101 through the connection end. When the load imbalance enhancement module 200 is connected, the switch Sa , S b and S c The load imbalance enhancement module 200 is closed so that it is connected to the DC side of the inverter system 100 and connected in parallel with the bus capacitor to increase the equivalent DC bus capacitance of the inverter system 100 .

[0047] It should be known that the load imbalance enhancement module 200 mainly includes a large capacitor, that is, when the load imbalance enhancement module 200 is connected to the inverter system 100, the large capacitor of the load imbalance enhancement module 200 is connected in parallel with the bus capacitor of the inverter system 100 to be connected to the DC bus, so that the inverter system 100 can obtain an equivalent DC bus capacitor with a larger capacity. At this time, the inverter system 100 can more efficiently adjust the voltage and current, thereby maintaining the stability and reliability of the system.

[0048] It should be noted that when the load imbalance enhancement module 200 is connected in parallel to the DC side of the inverter system 100, it is necessary to ensure the safety and stability of the operation process. Because the bus capacitor of the inverter system 100 often maintains a certain steady-state voltage before the load imbalance enhancement module 200 is connected, if a large capacitor is directly connected at this time, the voltage difference between the two will induce a significant current impact phenomenon. The impact current will not only damage the load imbalance enhancement module 200, but may also have an adverse effect on the stable operation of the entire inverter system 100, and even cause system failure. Therefore, in the process of connecting the load imbalance enhancement module 200 to the inverter system 100, measures must be taken to suppress the possible impact current.

[0049] There are many specific ways and specific stages for suppressing the impact current; for example, according to the stage of suppression, the impact current can be suppressed before the load imbalance enhancement module 200 is connected to the inverter system 100, or it can be suppressed during the process of connecting the load imbalance enhancement module 200; for ease of understanding, the following will be described in detail through three embodiments for the above two different suppression stage scenarios. It should be noted that the specific embodiments that can achieve the suppression of the impact current include but are not limited to the following three embodiments.

[0050] Scenario 1: Inrush current suppression scenario during the access phase of the load imbalance enhancement module 200.

[0051] Embodiment 1:

[0052] like Figure 2As shown, the load imbalance enhancement module 200 includes a capacitor unit, a protection circuit and an auxiliary power supply 202. The capacitor unit can be connected to the switch circuit 101 so that the capacitor unit is connected to the inverter system 100 to increase the equivalent DC capacity. The protection circuit is installed between the capacitor unit and the switch circuit 101, and the protection circuit can shunt the impact current generated when the switch circuit 101 is turned on. The auxiliary power supply 202 can draw power from the inverter system 100 through the switch circuit 101, and then power the internal components of the load imbalance enhancement module 200.

[0053] It can be understood that, in the inverter system 100, the bus capacitors generally include two; for example Figure 1 As shown, the two bus capacitors are marked as C1 and C2 respectively. The bus capacitor C1 is connected between the positive bus and the bus midpoint of the inverter system 100, that is, the bus capacitor C1 is connected to the positive half bus of the inverter system 100; the bus capacitor C2 is connected between the negative bus and the bus midpoint of the inverter system 100, that is, the bus capacitor C2 is connected to the negative half bus of the inverter system 100. In order to ensure the stable operation of the inverter system 100 after the load imbalance enhancement module 200 is connected, the capacitor units also need to be divided into two groups. After the load imbalance enhancement module 200 is connected to the inverter system 100, the two groups of capacitor units can be connected in parallel with the bus capacitor C1 and the bus capacitor C2 respectively through the switch circuit 101.

[0054] It should be known that the two groups of capacitor units can be independently connected in parallel with the two bus capacitors, or the two groups of capacitor units can be connected in series and then connected in parallel with the two bus capacitors. If the two groups of capacitor units are independently connected in parallel, then both the inverter system 100 and the load imbalance enhancement module 200 need to be provided with two bus midpoint interfaces, which may cause a waste of interface resources; while for the parallel connection of the two groups of capacitor units in series, it is only necessary to extend the bus midpoint interface at the midpoint of the branch formed by the two groups of capacitor units in series and connect it to the interface b´ of the inverter system 100. Therefore, in this embodiment, if Figure 2 As shown, two groups of capacitor units connected in series are preferably used to achieve parallel connection with two bus capacitors. Specifically, the connection end of the load imbalance enhancement module 200 is provided with interfaces a, b and c, and the two ends of the branch formed by the two groups of capacitor units connected in series are respectively connected to interfaces a and c, and the midpoint of the branch is connected to interface b; when the load imbalance enhancement module 200 is installed, interfaces a, b and c are connected to interfaces a', b' and c' of the inverter system 100 in sequence.

[0055] In this embodiment, Figure 2As shown, since the function of the protection circuit is to shunt the impact current, the protection circuit in this embodiment adopts a shunt circuit 201. In order to perform shunt protection on two groups of capacitor units at the same time, the two groups of capacitor units are connected to the bus of the inverter system 100 on one side and connected to the switch circuit 101 through the shunt circuit 201. That is, the shunt circuit 201 is installed between the interface a and the interface c and the capacitor units on the corresponding side. There are many specific structures of the shunt circuit 201 that can achieve the shunt effect. For the sake of easy understanding, one of the structures will be described in detail below.

[0056] Specifically, Figure 2 As shown, the shunt circuit 201 includes a current limiting resistor and a control switch; the current limiting resistor is connected in series between the capacitor unit and the switch circuit 101, and the control switch is connected in parallel to the current limiting resistor. The control switch can be disconnected when the switch circuit 101 is turned on. At this time, the current limiting resistor will be connected in series to the connection loop between the capacitor unit and the corresponding bus capacitor, so that the current limiting resistor can shunt the impact current in the connection loop. As the switch circuit 101 is turned on, the difference between the voltage of the capacitor unit and the bus voltage gradually decreases. Therefore, after the switch circuit 101 is turned on for a set time, the control switch can be closed to short-circuit the current limiting resistor.

[0057] It is understandable that there are many ways to control the closing and opening of the control switch, which can be controlled according to the bus voltage change of the inverter system 100, or according to the voltage of the two groups of capacitor units. In this embodiment, it is preferred to control the closing or opening of the switch by the voltage of the capacitor unit; the voltage of the capacitor unit can be detected by a voltage sensor, and the specific structure and working principle of the voltage sensor are well known to those skilled in the art, so they are not elaborated in detail here; the voltage sensor can be powered by the auxiliary power supply 202.

[0058] It can also be understood that during the operation of the capacitor unit, its voltage may fluctuate with the load state of the inverter system 100, and the voltage fluctuation of the capacitor unit may cause the control switch state to switch frequently. There are many specific ways to suppress the control switch from switching frequently with the voltage fluctuation of the capacitor unit. For example, when designing the control logic of the control switch, a hysteresis comparator can be designed to stabilize the state of the control switch by introducing hysteresis characteristics; of course, a latch can also be used to lock the drive signal of the control switch to avoid unnecessary jumping. For ease of understanding, the state control process of the control switch will be described in detail below with a hysteresis comparator and a latch; for ease of description, the control switches corresponding to the two shunt circuits 201 can be marked as switches S1 and S2; there are many specific types of control switches, which can be relays or semiconductor switch devices, etc., and the subsequent control switch takes a relay as an example.

[0059] For the control process of the hysteresis comparator, such as Figure 2 and Figure 4 As shown in the figure, the voltage sensor output is sent to the inverting input of the comparator, and the output is the driving signal for controlling the switch. There are two key threshold voltages in the hysteresis comparator, namely, the low threshold voltage V L and high threshold voltage V H When the voltage of the capacitor unit rises to a value exceeding the high threshold voltage V H When the voltage of the capacitor unit drops below the low threshold voltage V L When the drive signal is switched to a low level state, switches S1 and S2 are disconnected to shunt the impact current. It is particularly important that when the voltage of the capacitor unit is at the low threshold voltage V L and high threshold voltage V H When the voltage fluctuates between , the driving signal of the control switch will not immediately respond to the small change in voltage, but will maintain its current high or low state until the voltage of the capacitor unit crosses another threshold point, thereby reducing the malfunction of the control switch. L and high threshold voltage V H The specific value of can be set according to the actual working conditions of those skilled in the art, for example, the high threshold voltage V H 90% of the half DC bus voltage, low threshold voltage V L It is 20% of the half DC bus voltage.

[0060] For the control process of the latch, a low threshold voltage V can also be set L and high threshold voltage V H When the voltage of the capacitor unit rises to the preset high threshold voltage V H When the high-level trigger signal is sent to the input of the latch, the latch responds to this signal and then outputs a high-level signal to drive switches S1 and S2 to close. At the same time, the high-level state will be captured and locked by the latch, even if the voltage of the subsequent capacitor unit is below the high threshold voltage V H Even if disturbances occur nearby, the latch will keep its output state unchanged to ensure the stability of the switch drive signal. L When the low-level trigger signal is sent to the input of the latch, the latch responds to this signal and then outputs a low-level signal to drive switches S1 and S2 to disconnect.

[0061] In this embodiment, there are many specific structures of the auxiliary power supply 202. For ease of understanding, one of the structures will be described in detail below. Figure 3 As shown, the auxiliary power supply 202 adopts an isolated DC / DC architecture, and the auxiliary power supply 202 includes a corresponding main coil and a plurality of secondary coils. The main coil can be connected to the connection end interfaces a, b and c of the load imbalance enhancement module 200 through the DC / DC module, so that the main coil can be connected to the switch circuit 101 through the DC / DC module, thereby realizing power supply from the inverter system 100. The turns ratio of each secondary coil to the main coil is different, so that each secondary coil outputs a different supply voltage.

[0062] It should be known that the number of secondary coils and the turns ratio to the main coil can be set according to actual needs. Generally speaking, the power supply voltage required by the load imbalance enhancement module 200 includes 5V voltage, 15V voltage and 24V voltage. The 5V voltage is used to power the gate driver, the 15V voltage is used to power the control circuit, and the 24V voltage is used to power the relay coil or the voltage sensor. Therefore, in this embodiment, the number of secondary coils is at least three, and in order to ensure the independence of the power supplies formed by each secondary coil and avoid mutual interference, the ground wire of each power supply is independent and will not be electrically connected to the ground wire of other power supplies.

[0063] For ease of understanding, the specific access process of the load imbalance enhancement module 200 of this embodiment will be described in detail below. The specific number of each group of capacitor units can be one or more, and can be selected according to the actual needs of those skilled in the art; for the convenience of subsequent description, each group includes one capacitor unit as an example, and the two capacitor units corresponding to the two groups can be marked as capacitors C3 and C4, respectively, and the two ends of the capacitor C3 are connected to the interfaces a and b respectively, and the two ends of the capacitor C4 are connected to the interfaces b and c respectively.

[0064] like Figure 5 and Figure 6 As shown, when the inverter system 100 is operating normally, that is, Figure 6 Before time t1, the neutral current state of the inverter system 100 needs to be continuously monitored to ensure stable operation of the system.

[0065] like Figure 5 and Figure 6 Therefore, at time t1, it is detected that the neutral current of the inverter system 100 exceeds the set threshold value, and at this time, the switch S of the switch circuit 101 a , S b and S c The corresponding driving signal is high level, and then the switch S a , Sb and S c The load imbalance enhancement module 200 is closed so that the load imbalance enhancement module 200 is electrically connected to the DC side bus of the inverter system 100; at this time, the capacitors C3 and C4 in the load imbalance enhancement module 200 begin to enter the charging stage. Since the switches S1 and S2 of the shunt circuit 201 in the load imbalance enhancement module 200 are in the normally open state, the current i0 of the capacitors C3 and C4 in the initial charging stage will not produce a large impact due to the influence of the current limiting resistor, but will experience a process of first rapidly increasing until reaching a peak value. Subsequently, as the difference between the voltage at both ends of the capacitors C3 and C4 and the bus voltage gradually decreases, the current corresponding to the charging stage of the capacitors C3 and C4 also decreases accordingly; in this process, the change trend of the voltage at both ends of the capacitor unit is shown as first rapidly rising, and then gradually stabilizing.

[0066] like Figure 5 and Figure 6 Therefore, at time t2, when the voltage across capacitors C3 and C4 is close to the preset high threshold voltage V H , the current i0 flowing through the capacitor unit has gradually decayed to almost zero. At this time, switches S1 and S2 receive a high-level drive signal and close to bypass the current-limiting resistor, eliminating the current-limiting resistor's obstruction to the normal circuit operating current, thereby reducing energy loss. Since the current-limiting resistor is successfully bypassed, the current i0 will have a slight mutation, but will then continue to decrease until it completely drops to zero at time t3. At the same time, the voltage of the capacitor unit also just reaches half the bus voltage. Thereafter, the load imbalance enhancement module 200 enters its normal working state.

[0067] Scenario 2: Scenarios of suppressing the inrush current before the load imbalance enhancement module 200 is connected.

[0068] It is understandable that the above scenario 1 is to connect the capacitor unit online during the soft start process, and suppress the impact current by shunting the current limiting resistor. However, those skilled in the art should know that the impact current is caused by the large voltage difference between the voltage of the capacitor unit and the bus voltage, that is, the bus capacitor voltage; therefore, scenario 2 can discharge the residual voltage on the bus capacitor before the capacitor unit is connected to the inverter system 100, so that the bus voltage is reduced to a lower level or zero, which can effectively suppress or avoid the occurrence of current impact.

[0069] The specific working process is as follows Figure 7As shown, when it is detected that the load imbalance current exceeds the set threshold, the load imbalance enhancement module 200 is connected to both ends of the bus capacitor after the inverter system 100 stops working. Specifically, in order to ensure the safety of subsequent parallel operation, the inverter system 100 will disconnect the power generation unit before the load imbalance enhancement module 200 is connected, so that the power generation unit cannot be connected to the bus; then the grid-connected switch is disconnected in time to make the inverter system 100 enter the off-grid state, so as to avoid interference or impact on the power grid when the external load imbalance enhancement module 200 is connected in parallel.

[0070] After confirming that the DC side and AC side of the inverter system 100 are disconnected, the bus capacitor of the inverter system 100 is discharged, and then the capacitor unit of the load imbalance enhancement module 200 is connected in parallel to the two ends of the bus capacitor in a safe and smooth manner. After the capacitor unit of the load imbalance enhancement module 200 is successfully connected in parallel, the inverter system 100 will restart the power generation unit to restore normal operation, and reopen the grid-connected switch to ensure that the inverter system 100 can be safely reconnected to the grid and ensure the stability and reliability of the power system. Subsequently, the capacitor unit of the load imbalance enhancement module 200 will work normally to improve the adaptability of the inverter system 100 to load imbalance.

[0071] It is understandable that there are multiple ways to discharge the bus voltage before the capacitor unit is connected, which can be mainly divided into direct discharge and indirect discharge, which will be described in detail through two embodiments below.

[0072] Embodiment 2:

[0073] like Figure 8 As shown, this embodiment adopts an indirect discharge method for the bus voltage. The specific structure of the load imbalance enhancement module 200 in this embodiment is basically the same as that of the first embodiment, and the difference is that the protection circuit of the load imbalance enhancement module 200 adopts a discharge circuit 203, and the discharge circuit 203 is connected in parallel to the two groups of capacitor units of the load imbalance enhancement module 200. Therefore, before the capacitor unit is connected to the inverter system 100, the discharge circuit 203 can discharge the bus voltage of the inverter system 100 when the switch circuit 101 is turned on.

[0074] In this embodiment, there are multiple specific structures of the discharge circuit 203 that can realize bus voltage discharge. For the sake of easy understanding, one of the structures will be described in detail below. Figure 8As shown, the discharge circuit 203 includes a resistor string, a first control switch and a second control switch. The discharge branch formed by the series connection of the resistor string and the second control switch is connected in parallel to two groups of capacitor units. A first control switch is connected in series between one side of each group of capacitor units corresponding to the connection of the bus and the connection point of the discharge branch. The first control switch can be disconnected when the switch circuit 101 is turned on, and the second control switch is closed to connect the resistor string to the inverter system 100 to achieve the discharge of the bus voltage; after the resistor string is connected for a set time, the first control switch is closed first, and then the second control switch is disconnected, so that the resistor string is disconnected from the inverter system 100, and the capacitor unit is connected in parallel to the DC side of the inverter system 100.

[0075] It should be known that the number and resistance values ​​of the resistors included in the resistor string can be set according to the actual needs of those skilled in the art, for example Figure 8 As shown, the number of resistors included in the resistor string is three, and the three resistors are connected in series in sequence. The inverter system 100 of the present application can be applied to the field of photovoltaic power generation, or to the fields of wind power generation or hydropower generation. For the convenience of description, the inverter system 100 in the subsequent content takes a photovoltaic inverter system as an example, that is, the power generation unit of the inverter system 100 is a PV unit.

[0076] For ease of understanding, the specific access process of the capacitor unit of this embodiment will be described in detail below; for ease of description, the two first control switches can be defined as switches S3 and S5, respectively, and the second control switch can be defined as switch S4. Switch S4 can be connected in parallel with the discharge branch formed by the resistor series connection between interface a and interface c, switch S3 is installed between capacitor C3 and interface a, and switch S5 is installed between capacitor C4 and interface c.

[0077] like Fig. 9 and Fig.10 As shown, when the inverter system 100 is operating normally, that is, Fig.10 Before time t4, the neutral current state of the inverter system 100 needs to be continuously monitored to ensure stable operation of the system.

[0078] like Fig. 9 and Fig.10 As shown, at time t4, it is detected that the neutral current of the inverter system 100 exceeds the set threshold value. At this time, the PV unit of the inverter system 100 can be controlled to be cut off and the grid-connected switch can be disconnected to shut down the inverter system 100. When it is confirmed that the inverter system 100 is shut down, the switch S of the switch circuit 101 is turned on at time t5. a , S b and S c The corresponding drive signal is set to high level, and then the switch S a , Sb and S c The load imbalance enhancement module 200 is closed to establish an electrical connection with the DC bus of the inverter system 100. Since switches S3 and S5 are in a normally open state and switch S4 is in a normally closed state, capacitors C3 and C4 in the load imbalance enhancement module 200 are in a disconnected state, but the resistor string is connected in parallel to the DC side of the inverter system 100, and then the energy in the bus capacitor is converted into heat energy through the resistor string for heat dissipation, that is, the bus capacitor voltage is quickly discharged.

[0079] like Fig. 9 and Fig.10 As shown, at time t6, the voltage of bus capacitors C1 and C2 in the inverter system 100 has gradually decreased to a safe level V2, indicating that the bus voltage of the inverter system 100 has been lower than the set threshold V2. At this time, the auxiliary power supply 202 can still work normally, and switches S3 and S5 can be closed to connect capacitors C3 and C4 in parallel to the DC side of the inverter system 100 to start the charging stage. The current i0 of capacitors C3 and C4 increases rapidly in the charging stage and then gradually decreases.

[0080] like Fig. 9 and Fig.10 As shown, at time t7, the bus voltage of the inverter system 100 has dropped to the minimum voltage V1 at which the auxiliary power supply 202 can work normally, and then the auxiliary power supply 202 will stop working. At this time, the resistor string is still consuming power, so the charging current i0 of the capacitors C3 and C4 and the voltage of the bus capacitors C1 and C2 will continue to drop until they drop to zero at time t8, at which time the load imbalance enhancement module 200 and the inverter system 100 both stop working.

[0081] like Fig. 9 and Fig.10 As shown, at time t9, the PV units of the inverter system 100 are reconnected and the grid-connected switch is closed, the inverter system 100 resumes normal operation, the voltages of the bus capacitors C1 and C2 gradually increase, and the auxiliary power supply 202 resumes operation after the voltages of the bus capacitors C1 and C2 are greater than the minimum startup voltage V1, and at t 10 At this moment, the switch S4 is disconnected to prevent the resistor string from causing further energy loss. At this time, the charging current i0 of the capacitors C3 and C4 increases faster than the previous moment until t 11 When the voltage of bus capacitors C1 and C2 reaches half bus voltage, charging current i0 also reaches the maximum value and then decreases to zero. Subsequently, the inverter system 100 enters the normal working stage, and capacitors C3 and C4 of the load imbalance enhancement module 200 also work normally to enhance the load imbalance adaptability of the inverter system 100.

[0082] Embodiment three:

[0083] like Fig.11 and Fig.12 As shown, this embodiment adopts a direct discharge method for the bus voltage. Compared with the first embodiment and the second embodiment, the difference of this embodiment is that the specific structure of the load imbalance enhancement module 200 only includes a capacitor unit. When the load imbalance current exceeds the set threshold, before the switch circuit 101 is closed, the power generation unit of the inverter system 100 is cut off and the grid-connected switch is disconnected, so that the bus capacitor is discharged through the functional unit connected to the inverter system 100; after the voltage discharge of the bus capacitor is completed, the switch circuit 101 is closed and the power generation unit is reconnected and the grid-connected switch is closed.

[0084] It should be known that the functional units of the inverter system 100 include loads, DC / AC units, and capacitors and inductors on the AC side, etc. Therefore, when the bus voltage of the inverter system 100 is directly discharged, the inverter system 100 can disconnect the load and discharge naturally through power devices such as inductors and capacitors on the AC side; or the inverter system 100 can connect the load to the bus capacitor through the control of the DC / AC unit to realize the consumption of the bus voltage. Since the discharge speed of power devices such as capacitors and inductors is relatively slow, it is preferred to discharge the bus voltage by load discharge in this embodiment.

[0085] For ease of understanding, the specific access process of the load imbalance enhancement module 200 of this embodiment will be described in detail below.

[0086] like Fig.12 and Fig.13 As shown, when the inverter system 100 is operating normally, that is, Fig.13 Medium 12 Before the instant, the neutral current state of the inverter system 100 needs to be continuously monitored to ensure stable operation of the system.

[0087] like Fig.12 and Fig.13 As shown, at t 12 At time t, it is detected that the neutral current of the inverter system 100 exceeds the set threshold value. At this time, the PV unit of the inverter system 100 can be controlled to be cut off and the grid-connected switch can be disconnected to shut down the inverter system 100. Then at t 13 The DC / AC unit is controlled to work at all times so that the bus voltage can be consumed by the load, that is, the voltage discharge process of the bus capacitors C1 and C2 is realized until t 14 At this moment, the bus voltage is basically released.

[0088] like Fig.12 and Fig.13 As shown, at t 15 At this moment, the PV units of the inverter system 100 are reconnected and the grid-connected switch is closed, and the inverter system 100 resumes normal operation, and the voltages of the bus capacitors C1 and C2 gradually increase. When the voltages of the bus capacitors C1 and C2 are greater than the minimum voltage V1 for the auxiliary power supply 202 to start, that is, t 16 At this moment, the switch S of the switch circuit 101 is controlled a , S b and S c The load imbalance enhancement module 200 is closed so that it is connected to the DC side of the inverter system 100. The auxiliary power supply 202 exists inside the inverter system 100 to supply power to the internal components of the inverter system 100.

[0089] like Fig.13 As shown in FIG. 1 , when the capacitors C3 and C4 of the load imbalance enhancement module 200 begin to charge, since there is a small voltage difference between the bus capacitors C1 and C2 and the capacitors C3 and C4, the charging current i0 increases slightly and then increases to a peak value. 17 At this moment, the voltage of bus capacitors C1 and C2 reaches half bus voltage and remains stable, and the charging current i0 also increases to the maximum value and decreases to zero. Thereafter, capacitors C3 and C4 of the load imbalance enhancement module 200 will work normally.

[0090] In the embodiments of the present application, Fig.14 As shown, when the inverter system 100 has load imbalance, in order to ensure the stable operation of the inverter system 100, it is necessary to perform load imbalance control on the control loop of the inverter system 100. Specifically, the control loop adopts dq control, and the three-phase current i a 、i b and i c Reference value I under dq transformation d * and I q * It is restricted by the imbalance of three-phase load to prevent bus voltage fluctuation caused by serious imbalance of three-phase load.

[0091] It should be known that the specific working process of the control loop of the inverter system 100 is well known to those skilled in the art, and for ease of understanding, a brief introduction is given below.

[0092] like Fig.14 As shown, the three-phase current i a 、i b and i c First, after two coordinate transformations, we get the component i of the dq axis dand i q , and then with the reference value I controlled by the load imbalance d * and I q * Compare to form the current outer loop. Grid voltage v ga 、v gb and v gc Phase locking is performed through a phase-locked loop (PLL), and two coordinate transformations are performed for feedforward control. After the feedforward control is superimposed on the output of the current outer loop, the coordinates are inversely transformed again to finally obtain a PWM duty cycle signal for adjusting the DC / AC unit.

[0093] The above describes the basic principles, main features and advantages of the present application. Those skilled in the art should understand that the present application is not limited by the above embodiments, and the above embodiments and the specification only describe the principles of the present application. The present application may have various changes and improvements without departing from the spirit and scope of the present application, and these changes and improvements fall within the scope of the present application for which protection is sought. The scope of protection claimed by the present application is defined by the attached claims and their equivalents.

Claims

1. An inverter system anti-backflow adaptability enhanced architecture, characterized in that: include: Switching circuit; The switch circuit is built into a three-phase four-wire inverter system and connected to a DC bus through a first end; Load imbalance enhancement module; The load imbalance enhancement module is connected to the second end of the switch circuit via a three-phase connection end; and Acquisition module; the acquisition module is suitable for collecting the neutral line current of the inverter system to determine whether the load unbalanced current exceeds a set threshold; When the load unbalanced current exceeds a set threshold, the switch circuit is turned on so that the load unbalance enhancement module is connected to the inverter system to increase the equivalent DC bus capacitance.

2. The inverter system anti-backflow adaptability enhanced architecture according to claim 1, characterized in that: The load imbalance enhancement module comprises: Capacitor unit; the capacitor unit is suitable for connecting to the switch circuit; A protection circuit; the protection circuit is installed between the capacitor unit and the switch circuit, and the protection circuit is suitable for suppressing the impact current generated when the switch circuit is turned on; and Auxiliary power supply; the auxiliary power supply is suitable for drawing power from the inverter system through the switching circuit, and then supplying power to the internal components of the load imbalance enhancement module.

3. The inverter system anti-backflow adaptability enhanced architecture according to claim 2, characterized in that: The capacitor units are divided into two groups connected in series, and the two groups of capacitor units are respectively connected in parallel to the positive half bus and the secondary half bus of the inverter system through the switch circuit; The protection circuit adopts a shunt circuit, and one side of the two groups of capacitor units connected to the inverter system bus is connected to the switch circuit through the shunt circuit. The shunt circuit is suitable for shunting the impact current generated when the switch circuit is turned on.

4. The inverter system anti-backflow adaptability enhanced architecture according to claim 3, characterized in that: The shunt circuit comprises a current limiting resistor and a control switch; the current limiting resistor is connected in series between the capacitor unit and the switch circuit, and the control switch is connected in parallel to the current limiting resistor; The control switch is suitable for disconnecting when the switch circuit is turned on; The control switch is suitable for closing after the switch circuit is turned on for a set time.

5. The inverter system anti-backflow adaptability enhanced architecture according to claim 2, characterized in that: The capacitor units are divided into two groups connected in series, and the two groups of capacitor units are respectively connected in parallel to the positive half bus and the secondary half bus of the inverter system through the switch circuit; The protection circuit adopts a discharge circuit, which is connected in parallel to the two groups of capacitor units. The discharge circuit is suitable for discharging the bus voltage of the inverter system when the switch circuit is turned on.

6. The inverter system anti-backflow adaptability enhanced architecture according to claim 5, characterized in that: The discharge circuit includes a resistor string, a first control switch and a second control switch; A discharge branch formed by connecting the resistor string and the second control switch in series is connected in parallel to the two groups of capacitor units; The first control switch is connected in series between one side of each group of capacitor units corresponding to the connection of the busbar and the connection point of the discharge branch; The first control switch is adapted to be disconnected when the switch circuit is turned on, and at this time the second control switch is closed to connect the resistor string to the inverter system; After the resistor string is connected for a set time, the first control switch is first closed, and then the second control switch is opened.

7. The inverter system anti-backflow adaptability enhanced architecture according to any one of claims 2 to 6, characterized in that: The auxiliary power supply adopts an isolated DC / DC architecture, and the auxiliary power supply includes a corresponding main coil and a plurality of secondary coils; The main coil is suitable for being connected to the switch circuit through a DC / DC module, and the turns ratio of each secondary coil to the main coil is different, so that each secondary coil outputs a different supply voltage.

8. The inverter system anti-backflow adaptability enhanced architecture according to claim 1, characterized in that: The load imbalance enhancement module includes a capacitor unit, which is divided into two groups connected in series. The two groups of capacitor units are respectively connected in parallel to the positive half bus and the secondary half bus of the inverter system through the switch circuit; When the load unbalanced current exceeds the set threshold, before the switch circuit is closed, the power generation unit of the inverter system is cut off and the grid-connected switch is disconnected, so that the functional unit connected through the inverter system discharges the bus capacitor; after the voltage discharge of the bus capacitor is completed, the switch circuit is closed and the power generation unit is reconnected and the grid-connected switch is closed.

9. The inverter system anti-backflow adaptability enhanced architecture according to claim 8, characterized in that: The inverter system is suitable for discharging the bus voltage through the load.

10. The inverter system anti-backflow adaptability enhanced architecture according to claim 1, characterized in that: The acquisition module is suitable for directly acquiring current from the neutral line of the inverter system; Alternatively, the acquisition module is suitable for acquiring the three-phase current of the AC side of the inverter system, and then calculating the neutral line current.

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