Gain circuit and high-speed DRAM interface

Abstract

The present application proposes a gain circuit and a high-speed DRAM interface, and relates to the field of test technology. The gain circuit includes: a signal input circuit is connected to a signal to be gained; a reference voltage signal is connected to the input end of a reference circuit, and the reference circuit is used to set a reference voltage for gain; an adjustment circuit is electrically connected to the signal input circuit and the reference circuit respectively, and the adjustment circuit is used to dynamically adjust the gain of the signal; an output circuit is electrically connected to the signal input circuit and the reference circuit respectively, and the output circuit is used to output a signal after gain; a current compensation circuit is electrically connected to the signal input circuit, the reference circuit, and the adjustment circuit respectively, and the current compensation circuit is used to increase the current flowing through the signal input circuit, the reference circuit, and the adjustment circuit respectively when the reference voltage decreases; or is used to increase the current flowing through the signal input circuit, the reference circuit, and the adjustment circuit respectively when the reference voltage increases. The present application can maintain a stable gain output of the signal when the reference voltage signal decreases.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a gain circuit and a high-speed DRAM interface. Background Art

[0002] Currently, in communication systems, gain control of high-speed DRAM interfaces is critical to ensure signal quality. However, the existing RX gain circuit has a small gain margin at a lower reference voltage, which makes the signal susceptible to noise during transmission, thereby reducing signal integrity. Summary of the invention

[0003] The main purpose of the present invention is to provide a gain circuit, aiming to improve the RX margin of a high-speed DRAM interface.

[0004] To achieve the above object, the present invention provides a gain circuit, the gain circuit comprising:

[0005] A signal input circuit, the signal input circuit is used to receive the signal to be amplified;

[0006] A reference circuit, wherein an input terminal of the reference circuit is used to receive a reference voltage signal, and the reference circuit is used to set a reference voltage for gain;

[0007] A regulating circuit, the regulating circuit being electrically connected to the signal input circuit and the reference circuit respectively, and the regulating circuit being used to dynamically adjust the gain of the signal;

[0008] An output circuit, the output circuit being electrically connected to the signal input circuit and the reference circuit respectively, the output circuit being used to output a signal after gain;

[0009] A current compensation circuit, wherein the current compensation circuit is electrically connected to the signal input circuit, the reference circuit and the adjustment circuit, respectively, and the current compensation circuit is used to increase the current flowing through the signal input circuit, the reference circuit and the adjustment circuit when the reference voltage decreases; or to increase the current flowing through the signal input circuit, the reference circuit and the adjustment circuit when the reference voltage increases.

[0010] Optionally, the current compensation circuit includes:

[0011] A first switch circuit, the first switch circuit is connected in parallel with the signal input circuit, and the first switch circuit is used to perform current compensation on the signal to be amplified according to the reference voltage signal;

[0012] a second switch circuit, the second switch circuit being connected in parallel with the reference circuit, and the second switch circuit being used for performing current compensation on the reference voltage signal;

[0013] A third switch circuit is connected in parallel with the regulating circuit, and is used for performing current compensation on the regulating signal flowing through the regulating circuit according to the reference voltage signal.

[0014] Optionally, the first switch circuit, the second switch circuit and the third switch circuit each include a pair of back-to-back switch tubes.

[0015] Optionally, the signal input circuit includes:

[0016] A first switch tube, wherein a controlled end of the first switch tube is used to access a signal to be amplified, a first conduction end of the first switch tube is electrically connected to the regulating circuit, and a second conduction end of the first switch tube is connected to a power supply.

[0017] Optionally, the reference circuit includes:

[0018] A second switch tube, wherein the controlled end of the second switch tube is used to access a reference voltage signal, the first conduction end of the second switch tube is electrically connected to the regulating circuit, and the second conduction end of the second switch tube is connected to a power supply.

[0019] Optionally, the regulating circuit includes:

[0020] A third switch tube, wherein a first conduction end of the third switch tube is used for grounding, and a second conduction end of the third switch tube is electrically connected to the signal input circuit and the reference circuit respectively.

[0021] Optionally, the gain circuit further includes:

[0022] A voltage divider circuit, wherein a first end of the voltage divider circuit is electrically connected to the signal input circuit, a second end of the voltage divider circuit is electrically connected to the reference circuit, and a third end of the voltage divider circuit is connected to the controlled end of the third switch tube.

[0023] Optionally, the gain circuit further includes:

[0024] A first current limiting circuit, wherein the first current limiting circuit is electrically connected to the signal input circuit, and the first current limiting circuit is used to limit the current flowing through the signal input circuit.

[0025] Optionally, the gain circuit further includes:

[0026] A second current limiting circuit, wherein the second current limiting circuit is electrically connected to the reference circuit, and the second current limiting circuit is used to limit the current flowing through the reference circuit.

[0027] In addition, to achieve the above-mentioned purpose, the present invention also provides a high-speed DRAM interface, including the gain circuit and high-speed data buffer as described above, wherein the high-speed data buffer is used to receive a high-speed data signal input from the outside and pass the high-speed data signal to the gain circuit for signal gain processing.

[0028] The embodiment of the present invention is provided with a signal input circuit to access the signal to be gained, and a reference circuit to access the reference voltage signal, so as to set the reference voltage of the gain. Then, an adjustment circuit is provided to be electrically connected to the signal input circuit and the reference circuit respectively to dynamically adjust the gain of the signal, and the gain-posted signal is output through the output circuit. In order to reduce the self-bias voltage level when the reference voltage signal is reduced, resulting in a reduction in the current and gain of the first-stage amplifier, a current compensation circuit is provided to be electrically connected to the signal input circuit, the reference circuit and the adjustment circuit respectively, so as to add an additional current path through the current compensation circuit to enhance the additional current, so that when the reference voltage signal is reduced, the RX margin of the high-speed DRAM interface is improved, and the reduction in the current and gain of the first-stage amplifier can be reduced, thereby maintaining a stable gain output of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figure 1 is a circuit structure block diagram of a gain circuit according to an embodiment of the present invention;

[0032] Figure 2 It is a schematic diagram of compensation model of current compensation circuit;

[0033] Figure 3 is a circuit structure block diagram of a gain circuit according to another embodiment of the present invention;

[0034] Figure 4 A circuit structure block diagram of a gain circuit according to another embodiment of the present invention;

[0035] Figure 5 is a first circuit principle diagram of the gain circuit of the present invention;

[0036] Figure 6This is a second circuit principle diagram of the gain circuit of the present invention.

[0037] Description of Figure Numbers:

[0038]

[0039] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, and the well-known modules, units and their connections, links, communications or operations are not shown or described in detail. In addition, the described features, architectures or functions can be combined in any way in one or more embodiments. It should be understood by those skilled in the art that the various embodiments described below are only for illustration and not for limiting the scope of protection of the present invention. It can also be easily understood that the modules or units or processing methods in the various embodiments described herein and shown in the drawings can be combined and designed according to various different configurations. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0041] The limitations of various nouns or methods referred to in the following embodiments, except for those that are logically untenable, are generally based on the broad concepts that can be implemented under the premise of the disclosure in the embodiments. Under such understanding, the various specific subordinate specific limitations of the nouns or methods should be regarded as the inventive content of the present invention, and should not be understood narrowly or interpreted in a biased manner on the grounds that the specification does not disclose the specific limitations. Similarly, under the premise that it can be implemented logically, the order of the steps in the method is flexible and changeable, and the specific subordinate specific limitations in the broad concepts of various nouns or methods all fall within the scope of protection of the present invention.

[0042] The main solution of the embodiment of the present application is: by providing a signal input circuit to access the signal to be gained, providing a reference circuit to access the reference voltage signal, so as to set the reference voltage of the gain, and then providing an adjustment circuit electrically connected to the signal input circuit and the reference circuit respectively to dynamically adjust the gain of the signal, and outputting the gained signal through the output circuit. In order to reduce the self-bias voltage level caused by the reduction of the reference voltage signal, resulting in a reduction in the current and gain of the first-stage amplifier, a current compensation circuit is provided, which is electrically connected to the signal input circuit, the reference circuit and the adjustment circuit respectively, so as to add an additional current path through the current compensation circuit to enhance the additional current.

[0043] Since the gain margin of the RX gain circuit in the prior art is small at a lower reference voltage, the signal is easily affected by noise during transmission, thereby reducing the integrity of the signal.

[0044] The present application provides a solution, which improves the RX margin of the high-speed DRAM interface when the reference voltage signal decreases, and can reduce the reduction of the current and gain of the first-stage amplifier, thereby maintaining a stable gain output of the signal.

[0045] Reference Figure 1 In one embodiment of the present invention, the gain circuit includes a signal input circuit 10, a reference circuit 20, an adjustment circuit 30, an output circuit 40 and a current compensation circuit 50, wherein:

[0046] The signal input circuit 10 is used to access the signal to be gained; the input end of the reference circuit 20 is used to access the reference voltage signal, and the reference circuit 20 is used to set the reference voltage of the gain; the adjustment circuit 30 is electrically connected to the signal input circuit 10 and the reference circuit 20 respectively, and the adjustment circuit 30 is used to dynamically adjust the gain of the signal; the output circuit 40 is electrically connected to the signal input circuit 10 and the reference circuit 20 respectively, and the output circuit 40 is used to output the signal after gain; the current compensation circuit 50 is electrically connected to the signal input circuit 10, the reference circuit 20 and the adjustment circuit 30 respectively, and the current compensation circuit 50 is used to increase the current flowing through the signal input circuit 10, the reference circuit 20 and the adjustment circuit 30 when the reference voltage decreases; or to increase the current flowing through the signal input circuit 10, the reference circuit 20 and the adjustment circuit 30 when the reference voltage increases.

[0047] It is important to understand that in high-speed DRAM interfaces, the gain of the differential amplifier is determined by the transconductance (gm) of the transistor and the load resistance (RLoad), where gm is proportional to the drain current (I D ). When the reference voltage signal VREF decreases, the self-bias level of the transistor also decreases, resulting in a decrease in both the current and gain of the first-stage amplifier. This decrease can have an adverse effect on the high-speed performance of the amplifier. However, the additional current path controlled by the reference voltage signal VREF and using the PMOS transistor mitigates this effect. As VREF decreases, the gate-source voltage (V GS ) is increased, thereby enhancing the additional current, which can effectively compensate for the gain performance degradation caused by using a lower VREF in the gain circuit of the existing design.

[0048] In this embodiment, the signal input circuit 10 can be a signal input circuit 10 composed of a PMOS transistor or an NMOS transistor. The signal input circuit 10 can effectively receive an external signal and convert it into a voltage signal suitable for processing by the gain circuit. The reference circuit 20 can also be composed of a PMOS transistor or an NMOS transistor to ensure that an accurate and stable reference voltage is provided. The adjustment circuit 30 can be composed of a PMOS transistor or an NMOS transistor to achieve fine adjustment of the gain. The output circuit 40 is responsible for stably outputting the signal after gain, and may include a buffer to drive subsequent circuits or devices. The design of the current compensation circuit 50 is key. It is composed of a PMOS transistor or an NMOS transistor, and under the control of the reference voltage signal, it adjusts the current flowing through the circuit accordingly to maintain the stability of the gain and the high-speed performance of the amplifier.

[0049] Please refer to Figure 2 As shown, when the reference voltage signal VERF decreases, the current required to be compensated by the PMOS transistor is:

[0050] ;

[0051] in, is the migration rate, is the unit gate capacitance, W and L are the width and length of the transistor. When the signal input circuit 10, the reference circuit 20 and the adjustment circuit 30 are PMOS transistors, reduce, When the signal input circuit 10, the reference circuit 20 and the adjustment circuit 30 are NMOS transistors, improve improve, constant.

[0052] Optionally, refer to Figure 3 Another embodiment of the present invention provides a gain circuit based on the above Figure 1 In the embodiment shown, the current compensation circuit 50 includes a first switch circuit 51, a second switch circuit 52 and a third switch circuit 53, wherein:

[0053] The first switch circuit 51 is connected in parallel with the signal input circuit 10, and the first switch circuit 51 is used to perform current compensation on the gain signal according to the reference voltage signal; the second switch circuit 52 is connected in parallel with the reference circuit 20, and the second switch circuit 52 is used to perform current compensation on the reference voltage signal; the third switch circuit 53 is connected in parallel with the adjustment circuit 30, and the third switch circuit 53 is used to perform current compensation on the adjustment signal flowing through the adjustment circuit 30 according to the reference voltage signal.

[0054] In this embodiment, the first switch circuit 51 can use transistors with different threshold voltages to achieve accurate compensation for signals to be gained with different amplitudes. The second switch circuit 52 can be designed to quickly respond and adjust the current when the reference voltage signal VREF changes to maintain the stability of the reference circuit 20. The third switch circuit 53 can be configured to implement dynamic current compensation in the adjustment circuit 30 to ensure the accuracy and timeliness of gain adjustment.

[0055] In the application of high-speed DRAM interface, the performance of current compensation circuit 50 directly affects the response speed and signal integrity of the gain circuit. Therefore, the stability and anti-interference ability of current compensation circuit 50 need to be fully considered during design to ensure that stable current compensation can be provided in various working environments, thereby ensuring the high-speed performance and reliability of the gain circuit.

[0056] Optionally, refer to Figure 5 Another embodiment of the present invention provides a gain circuit, based on the above Figure 3 In the illustrated embodiment, the first switch circuit 51 includes a pair of back-to-back switch tubes; the second switch circuit 52 includes a pair of back-to-back switch tubes; and the third switch circuit 53 includes a pair of back-to-back switch tubes.

[0057] In this embodiment, by adopting the design of back-to-back switch tubes, the failure of the current compensation circuit 50 caused by the failure of a single switch tube can be effectively prevented. This back-to-back switch tube design not only improves the reliability of the current compensation circuit 50, but also can better adapt to the rapid change of the signal in the application of high-speed DRAM interface, ensuring the stable output of the gain circuit. In addition, the back-to-back switch tube configuration can also reduce the voltage spike caused by the switching action, thereby reducing the interference to other circuit parts and improving the anti-interference ability of the overall circuit.

[0058] Optionally, refer to Figure 5 Another embodiment of the present invention provides a gain circuit, based on the above Figure 1 In the embodiment shown, the signal input circuit 10 includes a first switch tube Q1, wherein:

[0059] The controlled end of the first switch tube Q1 is used to access the signal to be amplified, the first conduction end of the first switch tube Q1 is electrically connected to the regulating circuit 30, and the second conduction end of the first switch tube Q1 is connected to the power supply.

[0060] In this embodiment, the first switch tube Q1 can be an NMOS, and its conduction state is determined by the level of the signal to be gained. When the signal to be gained is at a high level, the first switch tube Q1 is turned on, allowing the signal to pass and be transmitted to the adjustment circuit 30; conversely, when the signal to be gained is at a low level, the first switch tube Q1 is turned off, preventing the transmission of the signal. This design enables the signal input circuit 10 to dynamically adjust its working state according to the actual situation of the signal to be gained, thereby achieving accurate control and processing of the signal to be gained. The adjustment circuit 30 performs corresponding gain adjustment on the signal according to the conduction or cut-off state of the first switch tube Q1 to ensure the stability and accuracy of the output signal. In this way, the gain circuit can adapt to input signals of different amplitudes and frequencies, and meet the strict requirements of the high-speed DRAM interface for signal processing.

[0061] Optionally, refer to Figure 6 Another embodiment of the present invention provides a gain circuit, based on the above Figure 1 In the embodiment shown, the signal input circuit 10 includes a first switch tube Q1, wherein:

[0062] The controlled end of the first switch tube Q1 is used to access the signal to be amplified, the first conduction end of the first switch tube Q1 is electrically connected to the regulating circuit 30, and the second conduction end of the first switch tube Q1 is grounded.

[0063] In this embodiment, the first switch tube Q1 can be a PMOS, and its conduction state is determined by the level of the signal to be amplified. When the signal to be amplified is at a low level, the first switch tube Q1 is turned on, allowing the signal to pass and be transmitted to the adjustment circuit 30; conversely, when the signal to be amplified is at a high level, the first switch tube Q1 is turned off, preventing the transmission of the signal. This design enables the signal input circuit 10 to dynamically adjust its working state according to the actual situation of the signal to be amplified, thereby achieving accurate control and processing of the signal to be amplified. The adjustment circuit 30 performs corresponding gain adjustment on the signal according to the conduction or cut-off state of the first switch tube Q1 to ensure the stability and accuracy of the output signal. In this way, the gain circuit can adapt to input signals of different amplitudes and frequencies, and meet the strict requirements of the high-speed DRAM interface for signal processing.

[0064] Optionally, refer to Figure 5 Another embodiment of the present invention provides a gain circuit based on the above Figure 1 In the embodiment shown, the reference circuit 20 includes a second switch tube Q2, wherein:

[0065] The controlled end of the second switch tube Q2 is used to access the reference voltage signal, the first conduction end of the second switch tube Q2 is electrically connected to the regulating circuit 30, and the second conduction end of the second switch tube Q2 is connected to the power supply.

[0066] In this embodiment, the second switch tube Q2 can be an NMOS, and its conduction state is determined by the level of the reference voltage signal. When the reference voltage signal is at a high level, the second switch tube Q2 is turned on, allowing the signal to pass and be transmitted to the adjustment circuit 30; conversely, when the reference voltage signal is at a low level, the second switch tube Q2 is turned off, preventing the transmission of the signal. This design enables the reference circuit 20 to dynamically adjust its working state according to the actual situation of the reference voltage signal, thereby achieving accurate control and processing of the reference signal. The adjustment circuit 30 performs corresponding gain adjustment on the signal according to the conduction or cut-off state of the second switch tube Q2 to ensure the stability and accuracy of the output signal. In this way, the gain circuit can adapt to reference signals of different amplitudes and frequencies, and meet the strict requirements of the high-speed DRAM interface for signal processing.

[0067] Optionally, refer to Figure 6 Another embodiment of the present invention provides a gain circuit, based on the above Figure 1 In the embodiment shown, the reference circuit 20 includes a second switch tube Q2, wherein:

[0068] The controlled end of the second switch tube Q2 is used to access the reference voltage signal, the first conduction end of the second switch tube Q2 is electrically connected to the regulating circuit 30, and the second conduction end of the second switch tube Q2 is grounded.

[0069] In this embodiment, the second switch tube Q2 can be a PMOS, and its conduction state is determined by the level of the reference voltage signal. When the reference voltage signal is at a low level, the second switch tube Q2 is turned on, allowing the signal to pass and be transmitted to the adjustment circuit 30; conversely, when the reference voltage signal is at a high level, the second switch tube Q2 is turned off, preventing the transmission of the signal. This design enables the reference circuit 20 to dynamically adjust its working state according to the actual situation of the reference voltage signal, thereby achieving accurate control and processing of the reference signal. The adjustment circuit 30 performs corresponding gain adjustment on the signal according to the conduction or cut-off state of the second switch tube Q2 to ensure the stability and accuracy of the output signal. In this way, the gain circuit can adapt to reference signals of different amplitudes and frequencies, and meet the strict requirements of the high-speed DRAM interface for signal processing.

[0070] Optionally, refer to Figure 5 Another embodiment of the present invention provides a gain circuit, based on the above Figure 1 In the embodiment shown, the regulating circuit 30 includes a third switch tube Q3, wherein:

[0071] The first conduction end of the third switch tube Q3 is used for grounding, and the second conduction end of the third switch tube Q3 is electrically connected to the signal input circuit 10 and the reference circuit 20 respectively.

[0072] If the third switch tube Q3 is an NMOS, the first conduction end of the third switch tube Q3 is used for grounding; Figure 6 As shown, when the third switch tube Q3 is a PMOS, the first conduction end of the third switch tube Q3 is used to access the power supply.

[0073] In this embodiment, the design of the regulating circuit 30 allows the third switch tube Q3 to be dynamically switched according to the level states of the signal input circuit 10 and the reference circuit 20. When the level of the signal input circuit 10 is higher than that of the reference circuit 20, the third switch tube Q3 transmits the signal of the signal input circuit 10 to the output end to achieve signal gain amplification; conversely, when the level of the reference circuit 20 is higher than that of the signal input circuit 10, the third switch tube Q3 transmits the signal of the reference circuit 20 to the output end to achieve signal attenuation. The design of this regulating circuit 30 enables the gain circuit to flexibly perform precise gain adjustment according to the difference between the input signal and the reference signal, thereby meeting the high-precision requirements of the high-speed DRAM interface for signal processing. In addition, this configuration of the third switch tube Q3 further enhances the stability and reliability of the circuit, ensuring that a stable output signal can be provided under various working conditions.

[0074] Optionally, refer to Figure 5 Another embodiment of the present invention provides a gain circuit, based on the above Figure 5 In the embodiment shown, the gain circuit further includes a voltage divider circuit 80, wherein:

[0075] A first end of the voltage divider circuit 80 is electrically connected to the signal input circuit 10 , a second end of the voltage divider circuit 80 is electrically connected to the reference circuit 20 , and a third end of the voltage divider circuit 80 is connected to the controlled end of the third switch tube Q3 .

[0076] In this embodiment, the design of the voltage divider circuit 80 can realize fine adjustment of the gain of the gain circuit according to the potential difference between the signal input circuit 10 and the reference circuit 20, and feedback back to the controlled end of the adjustment circuit 30. The voltage divider circuit 80 can provide a control voltage proportional to the potential difference between the input signal and the reference signal by generating a voltage dividing point between the signal input circuit 10 and the reference circuit 20. This control voltage can enable the adjustment circuit 30 to accurately adjust the gain of the signal to ensure the stability and accuracy of the output signal. The introduction of the voltage divider circuit 80 enables the gain circuit to respond to various different input conditions more flexibly, thereby meeting the high-speed DRAM interface's high-precision and stability requirements for signal processing. In this way, the gain circuit can not only adapt to input signals of different amplitudes and frequencies, but also dynamically adjust the gain according to the real-time changes of the signal to achieve the best signal processing effect.

[0077] Optionally, refer to Figure 4Another embodiment of the present invention provides a gain circuit based on the above Figure 1 In the embodiment shown, the gain circuit further includes a first current limiting circuit 60 and a second current limiting circuit 70, wherein:

[0078] The first current limiting circuit 60 is electrically connected to the signal input circuit 10 , and is used to limit the current flowing through the signal input circuit 10 ; the second current limiting circuit 70 is electrically connected to the reference circuit 20 , and is used to limit the current flowing through the reference circuit 20 .

[0079] In this embodiment, the design of the first current limiting circuit 60 and the second current limiting circuit 70 can effectively prevent damage to circuit elements due to excessive current. When the current of the input signal or the reference signal exceeds the preset safety threshold, the corresponding current limiting circuit will start to limit the further increase of the current, thereby protecting the circuit from overload damage. This design not only improves the stability and safety of the circuit, but also extends the service life of the circuit. In addition, the introduction of the current limiting circuit also helps to reduce power consumption and improve the energy efficiency ratio of the entire gain circuit. By accurately controlling the flow of current, the gain circuit can more stably process the signals required by the high-speed DRAM interface, ensuring the continuity and reliability of signal processing.

[0080] Optionally, refer to Figure 5 Another embodiment of the present invention provides a gain circuit, based on the above Figure 4 In the illustrated embodiment, the first current limiting circuit 60 includes a first resistor R1, wherein:

[0081] A first end of the first resistor R1 is electrically connected to the signal input circuit 10 , and a second end of the first resistor R1 is connected to a power source.

[0082] In this embodiment, the resistance value of the first resistor R1 is precisely selected to ensure that under normal operating conditions, the current in the signal input circuit 10 is maintained at a safe and effective level. The presence of the first resistor R1 can effectively limit the peak value of the current to prevent damage to the signal input circuit 10 due to excessive current. In addition, the first resistor R1 can also play a certain filtering role, reducing the noise in the signal, thereby improving the quality of the signal. In this way, the gain circuit can not only protect itself from overload damage, but also provide a clearer and more stable signal output, meeting the high requirements of the high-speed DRAM interface for signal quality.

[0083] Optionally, refer to Figure 5 Another embodiment of the present invention provides a gain circuit, based on the above Figure 4 In the illustrated embodiment, the second current limiting circuit 70 includes a second resistor R2, wherein:

[0084] A first end of the second resistor R2 is electrically connected to the reference circuit 20 , and a second end of the second resistor R2 is connected to a power source.

[0085] In this embodiment, the resistance value of the second resistor R2 is precisely selected to ensure that under normal operating conditions, the current in the signal input circuit 10 is maintained at a safe and effective level. The presence of the second resistor R2 can effectively limit the peak value of the current to prevent damage to the signal input circuit 10 due to excessive current. In addition, the second resistor R2 can also play a certain filtering role, reduce the noise in the signal, and thus improve the quality of the signal. In this way, the gain circuit can not only protect itself from overload damage, but also provide a clearer and more stable signal output, meeting the high requirements of the high-speed DRAM interface for signal quality.

[0086] The present invention also provides a high-speed DRAM interface, which includes the gain circuit as described in the above embodiment.

[0087] It is worth noting that since the high-speed DRAM interface of the present invention is based on the above-mentioned gain circuit, the embodiments of the high-speed DRAM interface of the present invention include all technical solutions of all embodiments of the above-mentioned gain circuit, and the technical effects achieved are also exactly the same, which will not be repeated here.

[0088] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0089] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0090] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, including a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0091] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A gain circuit, characterized in that: The gain circuit comprises: A signal input circuit, the signal input circuit is used to receive the signal to be amplified; A reference circuit, wherein an input terminal of the reference circuit is used to receive a reference voltage signal, and the reference circuit is used to set a reference voltage for gain; A regulating circuit, the regulating circuit being electrically connected to the signal input circuit and the reference circuit respectively, and the regulating circuit being used to dynamically adjust the gain of the signal; An output circuit, the output circuit being electrically connected to the signal input circuit and the reference circuit respectively, the output circuit being used to output a signal after gain; a current compensation circuit, the current compensation circuit being electrically connected to the signal input circuit, the reference circuit and the adjustment circuit, respectively, and the current compensation circuit being used to increase the current flowing through the signal input circuit, the reference circuit and the adjustment circuit respectively when the reference voltage decreases; or being used to increase the current flowing through the signal input circuit, the reference circuit and the adjustment circuit respectively when the reference voltage increases; The current compensation circuit comprises: A first switch circuit, the first switch circuit is connected in parallel with the signal input circuit, and the first switch circuit is used to perform current compensation on the signal to be amplified according to the reference voltage signal; a second switch circuit, the second switch circuit being connected in parallel with the reference circuit, and the second switch circuit being used for performing current compensation on the reference voltage signal; A third switch circuit is connected in parallel with the regulating circuit, and is used for performing current compensation on the regulating signal flowing through the regulating circuit according to the reference voltage signal.

2. The gain circuit according to claim 1, characterized in that The first switch circuit, the second switch circuit and the third switch circuit each include a pair of back-to-back switch tubes.

3. The gain circuit according to claim 1, characterized in that The signal input circuit comprises: A first switch tube, wherein a controlled end of the first switch tube is used to access a signal to be amplified, a first conduction end of the first switch tube is electrically connected to the regulating circuit, and a second conduction end of the first switch tube is connected to a power supply.

4. The gain circuit according to claim 1, wherein: The reference circuit comprises: A second switch tube, wherein the controlled end of the second switch tube is used to access a reference voltage signal, the first conduction end of the second switch tube is electrically connected to the regulating circuit, and the second conduction end of the second switch tube is connected to a power supply.

5. The gain circuit according to claim 1, wherein: The regulating circuit comprises: A third switch tube, wherein a first conduction end of the third switch tube is used for grounding, and a second conduction end of the third switch tube is electrically connected to the signal input circuit and the reference circuit respectively.

6. The gain circuit according to claim 5, characterized in that: The gain circuit further includes: A voltage divider circuit, wherein a first end of the voltage divider circuit is electrically connected to the signal input circuit, a second end of the voltage divider circuit is electrically connected to the reference circuit, and a third end of the voltage divider circuit is connected to the controlled end of the third switch tube.

7. The gain circuit according to claim 1, wherein: The gain circuit further includes: A first current limiting circuit, the first current limiting circuit is electrically connected to the signal input circuit, and the first current limiting circuit is used to limit the current flowing through the signal input circuit; A second current limiting circuit, wherein the second current limiting circuit is electrically connected to the reference circuit, and the second current limiting circuit is used to limit the current flowing through the reference circuit.

8. The gain circuit according to claim 7, characterized in that: The first current limiting circuit comprises: a first resistor, wherein a first end of the first resistor is electrically connected to the signal input circuit, and a second end of the first resistor is connected to a power supply; The second current limiting circuit comprises: A second resistor, wherein a first end of the second resistor is electrically connected to the reference circuit, and a second end of the second resistor is connected to a power supply.

9. A high-speed DRAM interface, characterized in that: It comprises a gain circuit as described in any one of claims 1 to 8 and a high-speed data buffer, wherein the high-speed data buffer is used to receive a high-speed data signal input from the outside and transmit the high-speed data signal to the gain circuit for signal gain processing.

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