Frequency dividing circuit, frequency dividing method and chip

Abstract

The embodiment of the invention provides a frequency dividing circuit, a frequency dividing method and a chip. The frequency dividing circuit comprises a calculation circuit used for receiving a software frequency dividing coefficient and a hardware frequency dividing coefficient; determining a target frequency division coefficient according to the software frequency division coefficient and the hardware frequency division coefficient; determining a counting lower limit value and a counting upper limit value according to the target frequency division coefficient and the frequency division coefficient threshold value; sending the counting lower limit value and the counting upper limit value to a counting circuit; the counting circuit is used for receiving an initial clock signal, a counting lower limit value and a counting upper limit value; counting in a counting range represented by the counting lower limit value and the counting upper limit value according to the initial clock signal to obtain a counting signal; and outputting the highest bit of the counting signal as a first frequency division signal.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a frequency divider circuit, a frequency divider method, and a chip. Background Technology

[0002] As chip integration increases, chip logic functions become more complex, and the number of integrated sub-modules increases. Different sub-modules typically require clock signals of different frequencies. Therefore, a clock generation module is needed to generate multiple clocks of different frequencies from a single clock source. Such a circuit is called a frequency divider (or frequency divider circuit).

[0003] With the continuous development of electronic devices, the requirements for chip performance and power consumption are increasing. Especially in fields such as wireless communication and radio frequency signal processing, precise frequency control has become one of the key technologies. Traditional frequency divider circuit designs have some limitations, such as limited configuration options and significant delays, which make them difficult to meet the requirements in certain application scenarios. Summary of the Invention

[0004] This disclosure provides a frequency divider circuit, a frequency divider method, and a chip.

[0005] In a first aspect, embodiments of this disclosure provide a frequency divider circuit, the frequency divider circuit comprising:

[0006] A calculation circuit is configured to receive a software frequency division coefficient and a hardware frequency division coefficient; determine a target frequency division coefficient based on the software frequency division coefficient and the hardware frequency division coefficient; determine a lower limit value and a higher limit value for counting based on the target frequency division coefficient and a frequency division coefficient threshold; and send the lower limit value and the higher limit value for counting to a counting circuit.

[0007] The counting circuit is used to receive an initial clock signal, the lower limit of the count, and the upper limit of the count; count within the counting range represented by the lower limit of the count and the upper limit of the count according to the initial clock signal to obtain a counting signal; and output the most significant bit of the counting signal as a first frequency divider signal.

[0008] In some embodiments, the computing circuit includes:

[0009] The first sub-computing circuit is configured to receive the software frequency division coefficient and the hardware frequency division coefficient, determine a first frequency division value based on the software frequency division coefficient, determine a second frequency division value based on the hardware frequency division coefficient, and perform a multiplication operation on the first frequency division value and the second frequency division value to obtain the target frequency division coefficient.

[0010] The second sub-computing circuit is used to receive the target frequency division coefficient, and calculate the lower limit value and the upper limit value of the count based on the target frequency division coefficient and the frequency division coefficient threshold.

[0011] In some embodiments, the target frequency division coefficient is an N-bit binary number, and the frequency division coefficient threshold is the maximum value of a (N-1)-bit binary number; N is an integer greater than 1.

[0012] In some embodiments, the frequency divider circuit further includes:

[0013] An output circuit is configured to receive the first frequency division signal and a first selection signal, wherein the first selection signal is used to indicate the parity of the target frequency division coefficient; when the target frequency division coefficient is even, the first frequency division signal is output as the target frequency division signal; when the target frequency division coefficient is odd, the first frequency division signal is adjusted by adjusting its duty cycle and then output as the target frequency division signal.

[0014] In some embodiments, the output circuit includes: a first selection circuit, a delay circuit, and an OR gate;

[0015] The first selection circuit is configured to receive the first selection signal, the preset signal, and the first frequency division signal; when the first selection signal indicates that the target frequency division coefficient is even, the first frequency division signal is sent to the delay circuit; when the first selection signal indicates that the target frequency division coefficient is odd, the preset signal is sent to the delay circuit.

[0016] The delay circuit is used to delay the signal sent by the first selection circuit for a preset time to obtain a second frequency-divided signal, and send the second frequency-divided signal to the OR gate; the preset time is half of the clock period of the initial clock signal;

[0017] The OR gate is used to receive the first frequency division signal and the second frequency division signal, and perform an OR operation on the first frequency division signal and the second frequency division signal to obtain the target frequency division signal.

[0018] In some embodiments, the first selection circuit includes a first selector, and the delay circuit includes a NOT gate and a flip-flop;

[0019] The control terminal of the first selector receives the first selection signal, the first input terminal of the first selector receives the preset signal, the second input terminal of the first selector receives the first frequency division signal, and the output terminal of the first selector is connected to the input terminal of the trigger.

[0020] The input of the NOT gate receives the initial clock signal, the output of the NOT gate is connected to the clock terminal of the flip-flop, and the output of the flip-flop outputs the second frequency divider signal.

[0021] In some embodiments, the first selection signal is the least significant bit of the target frequency division coefficient.

[0022] In some embodiments, the frequency divider circuit further includes:

[0023] The second selection circuit is used to receive the second selection signal, the initial clock signal, and the target frequency division signal, and to select the initial clock signal or the target frequency division signal for output according to the second selection signal.

[0024] Secondly, embodiments of this disclosure provide a frequency division method, the method comprising:

[0025] The target frequency division coefficient is determined based on the software frequency division coefficient and the hardware frequency division coefficient; the lower limit value and the upper limit value of counting are determined based on the target frequency division coefficient and the frequency division coefficient threshold.

[0026] The counting signal is obtained by counting within the counting range represented by the lower and upper count values ​​based on the initial clock signal; the most significant bit of the counting signal is output as the first frequency divider signal.

[0027] Thirdly, embodiments of this disclosure provide a chip that includes the frequency divider circuit described in the first aspect.

[0028] This disclosure provides a frequency divider circuit, a frequency divider method, and a chip. The frequency divider circuit includes: a calculation circuit for receiving software and hardware frequency divider coefficients; determining a target frequency divider coefficient based on the software and hardware frequency divider coefficients; determining a lower and upper count limit based on the target frequency divider coefficient and a frequency divider coefficient threshold; and sending the lower and upper count limit values ​​to a counting circuit; and a counting circuit for receiving an initial clock signal, the lower and upper count limit values; counting within the counting range represented by the lower and upper count limit values ​​based on the initial clock signal to obtain a counting signal; and outputting the most significant bit of the counting signal as a first frequency divider signal. Thus, since the target frequency divider coefficient is determined jointly by the software and hardware frequency divider coefficients, the configuration range of the target frequency divider coefficient is increased, and the target frequency divider coefficient can be flexibly configured according to actual needs. Because the target frequency divider coefficient can be configured via software, it has strong versatility and adaptability, thus eliminating the need to modify the hardware design of the frequency divider circuit. Furthermore, the frequency divider circuit of this invention also supports hardware configuration, exhibiting high stability and reliability. Attached Figure Description

[0029] Figure 1 A schematic diagram of a frequency divider circuit provided in an embodiment of this disclosure. Figure 1 ;

[0030] Figure 2A schematic diagram of a frequency divider circuit provided in an embodiment of this disclosure. Figure 2 ;

[0031] Figure 3 A schematic diagram of a frequency divider circuit provided in an embodiment of this disclosure. Figure 3 ;

[0032] Figure 4 A signal timing diagram of a frequency divider circuit provided in an embodiment of this disclosure. Figure 1 ;

[0033] Figure 5 A schematic diagram of a frequency divider circuit provided in an embodiment of this disclosure. Figure 4 ;

[0034] Figure 6 A flowchart illustrating a frequency division method provided in an embodiment of this disclosure;

[0035] Figure 7 A signal timing diagram of a frequency divider circuit provided in an embodiment of this disclosure. Figure 2 ;

[0036] Figure 8 A signal timing diagram of a frequency divider circuit provided in an embodiment of this disclosure. Figure 3 ;

[0037] Figure 9 This is a schematic diagram of the composition structure of a chip provided in an embodiment of this disclosure. Detailed Implementation

[0038] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0040] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0041] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0042] When using counter-based frequency divider circuits to divide clock signals, the following problems exist: 1) Fixed division ratio: Frequency divider circuits typically have a fixed division ratio, which cannot be flexibly adjusted according to actual needs, limiting their applicability and flexibility in different application scenarios. 2) Difficult hardware modification: Frequency divider circuits usually require the implementation of the division logic in hardware circuits. If the division ratio needs to be modified, the hardware circuit needs to be modified or redesigned, which increases development costs and time. 3) Difficult to debug and verify: Since frequency divider circuits are usually implemented in hardware, the debugging and verification process is relatively difficult, especially when the division ratio or operation logic needs to be frequently adjusted. 4) Power consumption and area: Hardware frequency divider circuits may occupy a large chip area and may consume a lot of power, especially when complex division logic or high-speed division is required. 5) Limited division range: Due to technical limitations in counter design, extremely high or extremely low division ratios cannot be achieved in some cases, limiting their application in different frequency ranges.

[0043] Based on this, the present disclosure provides a frequency divider circuit that can at least solve some of the problems mentioned above. Since the target frequency divider coefficient is determined jointly by the software and hardware frequency divider coefficients, the configuration range of the target frequency divider coefficient is increased, and the target frequency divider coefficient can be flexibly configured according to actual needs. Because the target frequency divider coefficient can be configured via software, it has strong versatility and adaptability, thus eliminating the need to modify the hardware design of the frequency divider circuit. Furthermore, the frequency divider circuit of the present invention also supports hardware configuration, exhibiting high stability and reliability.

[0044] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0045] In one embodiment of this disclosure, see [link to embodiment]. Figure 1 This illustrates a schematic diagram of the composition structure of a frequency divider circuit 10 provided in an embodiment of this disclosure. For example... Figure 1 As shown, the frequency divider circuit 10 includes:

[0046] The calculation circuit 11 is used to receive the software frequency division coefficient and the hardware frequency division coefficient; determine the target frequency division coefficient based on the software frequency division coefficient and the hardware frequency division coefficient; determine the lower limit value and the upper limit value of counting based on the target frequency division coefficient and the frequency division coefficient threshold; and send the lower limit value and the upper limit value of counting to the counting circuit 12.

[0047] The counting circuit 12 is used to receive an initial clock signal, a lower limit value, and an upper limit value; count within the counting range represented by the lower limit value and the upper limit value according to the initial clock signal to obtain a counting signal; and output the highest bit of the counting signal as the first frequency divider signal.

[0048] In this embodiment, the software frequency division factor can be represented by cfg_div, the hardware frequency division factor can be represented by dcd_div, and the target frequency division factor can be represented by cfg_div_load. The software frequency division factor cfg_div is a parameter set by a software configuration register and can be configured through a software interface, such as input / output (I / O) ports, memory-mapped register addresses, or dedicated communication protocols.

[0049] It should be noted that the software frequency division coefficient can be configured according to actual needs; for example, the software frequency division coefficient can be configured to a width of 8 bits (8-bit binary number), represented by cfg_div[7:0] (i.e., the combined representation of cfg_div[7] to cfg_div[0]), and its value range is 0 to 255; as another example, the software frequency division coefficient can be configured to a width of 4 bits, represented by cfg_div[3:0], and its value range is 0 to 15.

[0050] Since the software division coefficient can be freely configured, the frequency divider circuit 10 does not need to modify the hardware design when performing frequency division. The configuration of the software division coefficient can be achieved simply through software programming, which is convenient and quick to develop. This allows for more flexible debugging and verification during the development process, which is conducive to rapid iteration and updates, thereby accelerating the product development cycle and improving development efficiency.

[0051] It should also be noted that the hardware frequency divider coefficient dcd_div is a parameter that is determined during the chip hardware design. Modifying the hardware frequency divider coefficient usually requires replacing the hardware or redesigning the circuit. For example, the hardware frequency divider coefficient can be designed to have an 8-bit width, represented by dcd_div[7:0], and its value range is 0 to 255.

[0052] Since the hardware division factor is determined by the chip's hardware design, it is not affected by software errors or anomalies, thus exhibiting high stability and reliability. This broadens the application scenarios of the frequency divider circuit 10, making it particularly suitable for applications with high system stability requirements, such as aerospace, medical, and automotive electronics.

[0053] In this embodiment, the target frequency division coefficient is configured by both software and hardware frequency division coefficients. This allows the target frequency division coefficient to be dynamically adjusted during chip runtime by changing the values ​​of the software and hardware frequency division coefficients according to different application scenarios and requirements. This reduces dependence on specific hardware and improves the flexibility and versatility of the system.

[0054] It should also be noted that the lower limit of the count is the minimum value at which the counting circuit 12 begins counting, and the upper limit of the count is the maximum value that the counting circuit 12 can count within the defined counting range. Once the upper limit of the count is reached, the counting circuit 12 will restart the cyclic counting from the lower limit of the count. During this process, the highest bit of the counting signal will periodically change between logic 1 and logic 0, thereby obtaining the first frequency division signal corresponding to the target frequency division coefficient.

[0055] In this embodiment, the target frequency division coefficient is an N-bit binary number, and the frequency division coefficient threshold is the maximum value of (N-1)-bit binary numbers; N is an integer greater than 1. For example, if the target frequency division coefficient is a 17-bit binary number, then the frequency division coefficient threshold is a 16-bit binary number of 1s (i.e., 65535). Based on the target frequency division coefficient and the frequency division coefficient threshold, a lower limit value for counting that is less than the frequency division coefficient threshold and an upper limit value for counting that is greater than the frequency division coefficient threshold are obtained. Counting is performed within the counting range, and the highest bit of the resulting counting signal (N=17, then the 17th bit) is the first frequency-divided signal obtained after dividing the initial clock signal according to the target frequency division coefficient. For example, if the target frequency division coefficient is 2, then the frequency of the first frequency-divided signal is 1 / 2 of the initial clock signal.

[0056] It should also be noted that the counting circuit 12 obtains the first frequency division signal by cyclically counting within the counting range. When the target frequency division coefficient is even, the duty cycle of the first frequency division signal is 50%. However, when the target frequency division coefficient is odd, the duty cycle of the first frequency division signal is not 50% (e.g., 40%). In practical applications, a 50% duty cycle reduces distortion caused by signal waveform asymmetry, ensuring high fidelity during signal transmission and processing, resulting in higher stability and efficiency in signal processing. Therefore, clock signals often require a 50% duty cycle.

[0057] To ensure that the divided signal also has a 50% duty cycle when the target frequency division factor is odd, please refer to [reference needed]. Figure 2 The frequency divider circuit 10 may also include:

[0058] The output circuit 13 is used to receive a first frequency division signal and a first selection signal. The first selection signal is used to indicate the parity of the target frequency division coefficient. When the target frequency division coefficient is even, the first frequency division signal is output as the target frequency division signal. When the target frequency division coefficient is odd, the first frequency division signal is adjusted by adjusting the duty cycle and then output as the target frequency division signal.

[0059] In this embodiment, the output circuit 13 can flexibly process the first frequency division signal according to the parity of the target frequency division coefficient. When the target frequency division coefficient is even, since the first frequency division signal has a 50% duty cycle, the output circuit 13 outputs the first frequency division signal as the target frequency division signal. When the target frequency division coefficient is odd, since the duty cycle of the first frequency division signal is not 50%, the output circuit 13 adjusts the duty cycle of the first frequency division signal so that the output target frequency division signal has a 50% duty cycle. In this way, it can ensure that the output target frequency division signal has a more accurate duty cycle, thereby optimizing the signal quality and reducing signal distortion or error that may be caused by inaccurate duty cycle.

[0060] Next, please refer to Figure 3 The frequency divider circuit 10 will be described in detail.

[0061] In some embodiments, such as Figure 3 As shown, the computing circuit 11 includes:

[0062] The first sub-computing circuit 111 is used to receive the software frequency division coefficient cfg_div and the hardware frequency division coefficient dcd_div, determine the first frequency division value based on the software frequency division coefficient cfg_div, determine the second frequency division value based on the hardware frequency division coefficient dcd_div, and perform a multiplication operation on the first frequency division value and the second frequency division value to obtain the target frequency division coefficient cfg_div_load;

[0063] The second sub-computing circuit 112 is used to receive the target frequency division coefficient cfg_div_load, and calculate the lower limit and upper limit of the count based on the target frequency division coefficient cfg_div_load and the frequency division coefficient threshold.

[0064] Here, the frequency division coefficient threshold can be represented by CONST, the lower limit of the count can be represented by cnt_min, and the upper limit of the count can be represented by cnt_max.

[0065] In this embodiment of the disclosure, the first frequency division value = (software frequency division coefficient cfg_div+1), the second frequency division value = (hardware frequency division coefficient dcd_div+1), and the target frequency division coefficient cfg_div_load = first frequency division value × second frequency division value = (software frequency division coefficient cfg_div+1) × (hardware frequency division coefficient dcd_div+1).

[0066] Taking a software frequency divider coefficient cfg_div and a hardware frequency divider coefficient dcd_div both as having an 8-bit width as an example, the configuration range of the software frequency divider coefficient cfg_div[7:0] is 0 to 255, and correspondingly, the configuration range of the first frequency divider value is 1 to 256; the hardware frequency divider coefficient dcd_div[7:0] ( Figure 4 The configuration range of the second frequency division value (not shown in the figure) is 0 to 255, and the configuration range of the second frequency division value is 1 to 256. The maximum target frequency division coefficient cfg_div_load is 256×256=65536 frequency division, and the target frequency division coefficient cfg_div_load is 17 bits wide, represented by cfg_div_load[16:0].

[0067] In implementation, when it is necessary to divide the initial clock signal (represented by in_clk) by 1 (i.e., the target division coefficient cfg_div_load is 1, meaning no division), both the software division coefficient cfg_div and the hardware division coefficient dcd_div can be configured to be 0. Similarly, when it is necessary to divide the initial clock signal in_clk by 2 (i.e., the target division coefficient cfg_div_load is 2), the software division coefficient cfg_div can be configured to be 1, and the hardware division coefficient dcd_div to be 0; or, the software division coefficient cfg_div can be configured to be 0, and the hardware division coefficient dcd_div to be 1.

[0068] It should be noted that the target frequency division coefficient cfg_div_load[16:0] is the actual frequency division value; when the dynamic frequency division function is enabled (i.e., both the software frequency division coefficient and the hardware frequency division coefficient are dynamically configured), the target frequency division coefficient cfg_div_load is: (software frequency division coefficient cfg_div+1)×(hardware frequency division coefficient dcd_div+1); when the dynamic frequency division function is not enabled (i.e., only the software frequency division coefficient is dynamically configured, and the hardware frequency division coefficient is fixed at 0), the target frequency division coefficient cfg_div_load is only: (software frequency division coefficient cfg_div+1).

[0069] In this embodiment of the disclosure, the second sub-computing circuit 112 can calculate the lower limit value cnt_min and the upper limit value cnt_max respectively using the following formulas (1) and (2);

[0070] cnt_min=CONST-INI(cfg_div_load / 2)+1-cfg_div_load[0](1)

[0071] cnt_max=CONST+INI(cfg_div_load / 2)(2)

[0072] Here, CONST is the frequency division coefficient threshold; INI(X) is a function that rounds down: converts a real number X into the largest integer not exceeding X. It can be seen from formulas (1) and (2) that the lower limit value cnt_min and the upper limit value cnt_max are set around the frequency division coefficient threshold CONST (equivalent to the frequency division coefficient threshold being the middle value of the counting range).

[0073] For example, in this embodiment of the disclosure, the first sub-computation circuit 111 can consist of two adders and a multiplier. The two adders add 1 to the software frequency division coefficient cfg_div and the hardware frequency division coefficient dcd_div, respectively, to obtain the first frequency division value and the second frequency division value. The multiplier is used to perform a multiplication operation on the first frequency division value and the second frequency division value to obtain the target frequency division coefficient cfg_div_load. Similarly, the second calculation sub-circuit can also be implemented by a calculation circuit that implements the corresponding function, which will not be described in detail here.

[0074] As mentioned above, in this embodiment of the disclosure, the target frequency division coefficient cfg_div_load is an N-bit binary number, and the frequency division coefficient threshold is the maximum value of (N-1)-bit binary numbers. For example, when the target frequency division coefficient cfg_div_load[16:0] is a 17-bit binary number and the initial clock signal in_clk is divided by 4, the set frequency division coefficient threshold is the maximum value of a 16-bit binary number, i.e., 65535; the count lower limit value cnt_min and count upper limit value cnt_max are calculated using formulas (1) and (2) to be 65534 and 65537, respectively. As another example, when the target frequency division coefficient cfg_div_load[16:0] is a 17-bit binary number and the initial clock signal in_clk is divided by 5, the count lower limit value cnt_min and count upper limit value cnt_max are calculated using formulas (1) and (2) to be 65533 and 65537, respectively.

[0075] It should be noted that, to simplify the length of the signal representation, 65533, 65535, etc., are all decimal representations. The width (i.e., number of bits) of the lower limit value cnt_min and the upper limit value cnt_max is the same as the width of the target frequency division coefficient cfg_div_load, for example, 17 bits. In this way, it can be ensured that the lower limit value cnt_min[16:0] and the upper limit value cnt_max[16:0] can identify the entire counting range.

[0076] Assuming the hardware frequency division factor dcd_div[7:0] is fixed at 0 (the second frequency division value is fixed at 1), Figure 4 This is a schematic diagram of the corresponding signal timing. Please refer to it. Figure 3 and Figure 4In this embodiment of the present disclosure, the counting range of the counting circuit 12 is from the lower limit value cnt_min to the upper limit value cnt_max. In the frequency division with a target frequency division coefficient cfg_div_load of 256×256, the counting circuit 12 can perform counting operations through a 17-bit counting signal, represented by count[16:0]. The counting signal count[16:0] is composed of a 1-bit first frequency division signal div_even and a 16-bit div_cnt_tmp[15:0] signal (i.e., the signals of the remaining bits in the counting signal that are not the highest bit, which can be recorded as the remaining counting signals); that is, the counting signal count[16:0] = {div_even, div_cnt_tmp}, where the first allocation signal div_even is the highest bit count

[16] of the counting signal count[16:0].

[0077] Thus, during the counting process of the counting circuit 12, the counting signal count[16:0] starts from the lower limit value cnt_min[16:0] and counts once at the rising edge of the initial clock signal in_clk (this is just an example; it could also be the falling edge, a high level, or a low level). Each time it counts, the count value corresponding to the counting signal count[16:0] is incremented by 1. When the count value corresponding to the counting signal count[16:0] is less than the frequency division coefficient threshold 65535, the first frequency division signal div_even is 0; when the count value corresponding to the counting signal[16:0] is greater than the frequency division coefficient threshold 65535, an overflow occurs (i.e., the remaining 16 bits except the highest bit are all 0, and the highest bit carries over to 1), and the first frequency division signal div_even becomes 1; when the count value corresponding to the counting signal count[16:0] reaches the maximum count value cnt_max, it returns to the minimum count value cnt_min and starts counting again, and the first frequency division signal div_even becomes 0 again. Thus, by utilizing the periodic variation of the most significant bit div_even of the counting signal count[16:0], the first frequency divider signal div_even can be generated. Specifically, when the target frequency divider coefficient cfg_div_load[16:0] is even, the first frequency divider signal div_even is an even-numbered frequency divider clock with a 50% duty cycle (e.g., ...). Figure 4 (As shown in region B); when the target frequency division coefficient cfg_div_load[16:0] is odd, the first frequency division signal div_even is an odd frequency division clock with a duty cycle of 1:2 (as shown in region B); Figure 4 (As shown in region C). It should be noted that, Figure 4 In the hexadecimal representation, ffff is 65535; fffe is 65534.

[0078] In some embodiments, please refer to Figure 3 The output circuit 13 includes: a first selection circuit 131, a delay circuit 132, and an OR gate 133; a first sub-calculation circuit 111, which is also used to send the first selection signal to the first selection circuit 131.

[0079] The first selection circuit 131 is used to receive a first selection signal, a preset signal, and a first frequency division signal div_even; when the first selection signal indicates that the target frequency division coefficient cfg_div_load is even, it sends the first frequency division signal to the delay circuit 132; when the first selection signal indicates that the target frequency division coefficient cfg_div_load is odd, it sends the preset signal to the delay circuit 132.

[0080] The delay circuit 132 is used to delay the signal sent by the first selection circuit 131 for a preset time to obtain a second frequency-divided signal, and send the second frequency-divided signal to the OR gate 133; the preset time is half of the clock period of the initial clock signal;

[0081] OR gate 133 is used to receive the first frequency division signal div_even and the second frequency division signal div_neg, and perform an OR operation on the first frequency division signal div_even and the second frequency division signal div_neg to obtain the target frequency division signal out_clk.

[0082] Here, the first selection signal can be represented by cfg_div_load[0], which is used to indicate the parity of the target frequency division coefficient cfg_div_load. For example, if the first selection signal is 0, it means that the target frequency division coefficient cfg_div_load is even; if the first selection signal is 1, it means that the target frequency division coefficient cfg_div_load is odd.

[0083] In this embodiment, the first selection signal cfg_div_load[0] is the least significant bit of the target frequency division signal cfg_div_load[16:0]. When the first selection signal cfg_div_load[0] is even (i.e., 0), it indicates that the target frequency division signal cfg_div_load[16:0] is even; when the first selection signal cfg_div_load[0] is odd (i.e., 1), it indicates that the target frequency division signal cfg_div_load[16:0] is odd. The preset signal is a continuous low-level signal (i.e., continuously 0), which can be represented by div_0. The second frequency division signal can be represented by div_neg.

[0084] It should be noted that when the target frequency division signal cfg_div_load[16:0] is even, since the first frequency division signal div_even output by the counting circuit 12 can be directly used as the target frequency division signal out_clk, after the first selection signal cfg_div_load[0] selects the preset signal output, the second frequency division signal div_neg output is still a continuous low-level signal (the same as the preset signal) after being delayed for a preset time by the delay circuit 132. Then, the target frequency division signal out_clk output by performing an OR operation between the second frequency division signal div_neg and the first frequency division signal div_even is the same as the first frequency division signal div_even. That is, in this case, the output target frequency division signal out_clk is the first frequency division signal div_even.

[0085] It should also be noted that when the target frequency divider signal cfg_div_load[16:0] is odd, the duty cycle of the first frequency divider signal div_even needs to be adjusted to 50% before output. After the first selection signal cfg_div_load[0] selects the first frequency divider signal div_even for output, the first frequency divider signal div_even is delayed by half the clock period of the initial clock signal in_clk through the delay circuit 132 to obtain the second frequency divider signal div_neg. Then, the second frequency divider signal div_neg is ORed with the first frequency divider signal div_even, and the output target frequency divider signal out_clk has a 50% duty cycle.

[0086] In some embodiments, please refer to Figure 3 The first selection circuit 131 includes a first selector 131a, and the delay circuit 132 includes an NOT gate 132a and a flip-flop 132b.

[0087] The control terminal of the first selector 131a receives the first selection signal cfg_div_load[0]. The first input terminal of the first selector 131a receives a preset signal. The second input terminal of the first selector 131a receives the first frequency division signal div_even. The output terminal of the first selector 131a is connected to the input terminal of the flip-flop 132b. The input terminal of the NOT gate 132a receives the initial clock signal in_clk. The output terminal of the NOT gate 132a is connected to the clock terminal of the flip-flop 132b. The output terminal of the flip-flop 132b outputs the second frequency division signal div_neg.

[0088] In this embodiment of the disclosure, the output of the first selector 131a is controlled by the first selection signal cfg_div_load[0]. When the first selection signal cfg_div_load[0] is even, a preset signal is selected for output. When the first selection signal cfg_div_load[0] is odd, the first frequency division signal div_even is selected for output.

[0089] After performing a NOT operation on the initial clock signal in_clk using NOT gate 132a, the preset signal or the first frequency divider signal div_even is sampled, causing the preset signal or the first frequency divider signal div_even to be delayed by a preset duration of half a clock cycle, thereby generating the second frequency divider signal div_neg, which is then used to generate the target frequency divider signal out_clk.

[0090] In some embodiments, such as Figure 5 As shown, the frequency divider circuit 10 also includes:

[0091] The second selection circuit 14 is used to receive the second selection signal (which can be represented by clk_sel_1x), the initial clock signal in_clk, and the target frequency divider signal out_clk, and to select the initial clock signal in_clk or the target frequency divider signal out_clk for output according to the second selection signal clk_sel_1x.

[0092] It should be noted that, in this embodiment, the frequency-divided signal or the initial clock signal can also be selected for output based on actual needs. When the second selection signal clk_sel_1x is the first value, it indicates that frequency division is not currently required, and the initial clock signal in_clk is selected as the final output signal clk_sel_out. When clk_sel_1x is the second value, it indicates that frequency division is currently required according to the set coefficient, and in this case, the target frequency-divided signal out_clk is output as the output signal clk_sel_out. The first value can be 1, and the second value can be 0; or vice versa, or other values ​​are not specifically limited.

[0093] like Figure 5 As shown, the second selection circuit 14 may include a second selector 142. The control terminal of the second selector 142 receives the second selection signal clk_sel_1x, the first input terminal of the second selector 142 receives the target frequency division signal out_clk, and the second input terminal of the second selector 142 receives the initial clock signal in_clk. Please refer to... Figure 4 and Figure 5When the second selection signal clk_sel_1x is the first value, the second selector 142 selects the initial clock signal in_clk as the output signal clk_sel_out (e.g., ...). Figure 4 (As shown in region A); when the second selection signal clk_sel_1x is the second value, the target frequency division signal out_clk is selected as the output signal clk_sel_out.

[0094] In this way, the second selection circuit 14 can flexibly control whether to divide the initial clock signal in_clk. When the second selection signal clk_sel_1x is the second value, the initial clock signal is directly output without frequency division, thereby enabling rapid switching of the clock frequency and reducing signal delay.

[0095] In this embodiment of the disclosure, since the frequency divider circuit 10 can support software configuration of the software frequency divider coefficient, it has strong versatility and adaptability. It can be configured according to different application scenarios and requirements, reducing the dependence on specific hardware and improving the flexibility and versatility of the system.

[0096] In another embodiment of this disclosure, a frequency division method is also provided, please refer to... Figure 6 The frequency division method includes steps S110 and S120.

[0097] Step S110: Determine the target frequency division coefficient cfg_div_load based on the software frequency division coefficient cfg_div and the hardware frequency division coefficient dcd_div; determine the lower limit value cnt_min and the upper limit value cnt_max based on the target frequency division coefficient cfg_div_load and the frequency division coefficient threshold CONST.

[0098] It should be noted that this frequency division method is applied to the frequency division circuit 10 in the above embodiment.

[0099] Next, we will use the target frequency division coefficients cfg_div_load of 4 and 5 as examples for explanation; where, Figure 7 The timing diagram is for a target frequency division coefficient cfg_div_load of 4. Figure 8 The timing diagram is shown when the target frequency division coefficient cfg_div_load is 5.

[0100] Please refer to Figure 7 and Figure 8The software frequency division coefficient cfg_div[1:0] and the hardware frequency division coefficient dcd_div[1:0] are received through the first sub-computing circuit 111. The configuration range of the software frequency division coefficient cfg_div[1:0] is 0 to 3, and the configuration range of the first frequency division value is 1 to 4. The configuration range of the hardware frequency division coefficient dcd_div[1:0] is 0 to 3, and the configuration range of the second frequency division value is 1 to 4. The target frequency division coefficient cfg_div_load is at most 4×4=16 frequency division, and the target frequency division coefficient cfg_div_load has a width of 5 bits and is represented by cfg_div_load[4:0].

[0101] It should be noted that the connection structure of the first sub-computing circuit 111, the second sub-computing circuit 112, etc., can be referenced. Figure 4 or Figure 5 To understand.

[0102] In this embodiment, the target frequency division coefficient cfg_div_load[4:0] is received by the second sub-computing circuit 112, and the target frequency division coefficient cfg_div_load[4:0] and the frequency division coefficient threshold CONST are substituted into the above formulas (1) and (2) to determine the lower limit value cnt_min[4:0] and the upper limit value cnt_max[4:0]. Here, when the target frequency division coefficient cfg_div_load[4:0] is a 5-bit binary number, the frequency division coefficient threshold CONST is the maximum value of a 4-bit binary number, i.e., 15.

[0103] Please refer to Figure 7 When the target frequency division coefficient cfg_div_load is 4, the lower limit of the count cnt_min[4:0] and the upper limit of the count cnt_max[4:0] are 0_1110 (i.e., 14) and 1_0001 (i.e., 17), respectively. Please refer to [reference needed]. Figure 8 When the target frequency division coefficient cfg_div_load is 5, the lower limit value cnt_min[4:0] and the upper limit value cnt_max[4:0] are 0_1101 (i.e. 13) and 1_0001 (i.e. 17), respectively.

[0104] Finally, the obtained lower limit value cnt_min[4:0] and upper limit value cnt_max[4:0] are sent to the counting circuit 12.

[0105] Step S120: Count within the counting range represented by the lower limit value cnt_min and the upper limit value cnt_max according to the initial clock signal in_clk to obtain the counting signal count[4:0]; output the highest bit of the counting signal count[4:0] as the first frequency divider signal div_even.

[0106] In this embodiment of the present disclosure, the counting circuit 12 receives the initial clock signal in_clk, the lower limit value cnt_min[4:0], and the upper limit value cnt_max[4:0], and counts within the counting range represented by the lower limit value cnt_min[4:0] and the upper limit value cnt_max[4:0] according to the initial clock signal in_clk, to obtain the counting signal count[4:0] (not shown); wherein, the counting signal count[4:0] is composed of the first frequency division signal div_even and the remaining counting signals div_cnt_tmp[3:0].

[0107] Please continue to refer to this. Figure 7 When the lower limit value cnt_min[4:0] and the upper limit value cnt_max[4:0] are 0_1110 (i.e., 14) and 1_0001 (i.e., 17) respectively, the initial clock signal in_clk is counted. When the count signal is 0_1110 to 0_1111, the highest bit 0 of the count signal is used as the first frequency divider signal div_even. When the count signal is 0_1111 to 1_0000, the highest bit 1 of the output count signal is used as the first frequency divider signal div_even.

[0108] Please continue to refer to this. Figure 8 When the lower limit value cnt_min[4:0] and the upper limit value cnt_max[4:0] are 0_1101 (i.e. 13) and 1_0001 (i.e. 17) respectively, the initial clock signal in_clk is counted. When the count signal is 0_1110 to 0_1111, the highest bit 0 of the count signal is used as the first frequency divider signal div_even. When the count signal is 0_1111 to 1_0001, the highest bit 1 of the output count signal is used as the first frequency divider signal div_even.

[0109] In this embodiment of the disclosure, the frequency division method may further include: step S130, receiving a first frequency division signal div_even and a first selection signal cfg_div_load[0] through the output circuit 13, wherein the first selection signal cfg_div_load[0] is used to indicate the parity of the target frequency division coefficient cfg_div_load[4:0]; when the target frequency division coefficient cfg_div_load[4:0] is even, outputting the first frequency division signal div_even as the target frequency division signal out_clk; when the target frequency division coefficient cfg_div_load[4:0] is odd, adjusting the duty cycle of the first frequency division signal div_even and outputting it as the target frequency division signal out_clk.

[0110] Please refer to Figure 7 When the target frequency division signal cfg_div_load[4:0] is 4, after the first selection signal cfg_div_load[0] selects the preset signal output, it is delayed for a preset time by the delay circuit 132, and the output second frequency division signal div_neg is a continuous low-level signal (the same as the preset signal). Then, the target frequency division signal out_clk output by performing an OR operation between the second frequency division signal div_neg and the first frequency division signal div_even is the same as the first frequency division signal div_even.

[0111] Please refer to Figure 8 When the target frequency division signal cfg_div_load[4:0] is 5, since the duty cycle of the first frequency division signal div_even needs to be adjusted to 50% before output, after the first selection signal cfg_div_load[0] selects the first frequency division signal div_even for output, the second frequency division signal div_neg is the same as the first frequency division signal div_even after being delayed by half a clock cycle by the delay circuit 132. Then, the target frequency division signal out_clk output by performing an OR operation between the second frequency division signal div_neg and the first frequency division signal div_even has a 50% duty cycle.

[0112] In this embodiment of the disclosure, the frequency division method may further include: step S140, receiving a second selection signal clk_sel_1x, an initial clock signal in_clk, and a target frequency division signal out_clk through a second selection circuit 14, and selecting either the initial clock signal in_clk or the target frequency division signal out_clk for output according to the second selection signal clk_sel_1x.

[0113] The frequency division method provided in this embodiment is similar to the operation method of the frequency division structure in the above embodiments. For technical features not disclosed in detail in this embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0114] In addition, this disclosure also provides a chip 20, please refer to... Figure 9 The chip 20 includes the frequency divider circuit 10 in the above embodiments.

[0115] In some embodiments, the chip 20 may include a Dynamic Random Access Memory (DRAM) chip. The DRAM chip can conform to not only Double Data Rate (DDR), DDR2, DDR3, DDR4, DDR5, and DDR6 memory specifications, but also Low Power Double Data Rate (LPDDR), LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6 memory specifications; no specific limitation is made here.

[0116] In this embodiment of the disclosure, since the chip 20 includes the frequency divider circuit 10 described in the foregoing embodiments, the initial clock signal can be divided without redesigning the circuit of the chip 20, thereby reducing the chip development cost and cycle.

[0117] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0118] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0119] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0120] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0121] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0122] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0123] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A frequency division circuit, characterized in that: include: A calculation circuit, used for receiving a software frequency division coefficient and a hardware frequency division coefficient; Determine a target frequency division coefficient according to the software frequency division coefficient and the hardware frequency division coefficient; Determine a lower count limit value and an upper count limit value according to the target frequency division coefficient and the frequency division coefficient threshold value; send the lower count limit value and the upper count limit value to a counting circuit; The counting circuit is used to receive an initial clock signal, the counting lower limit value and the counting upper limit value; count within the counting range represented by the counting lower limit value and the counting upper limit value according to the initial clock signal to obtain a counting signal; and output the highest bit of the counting signal as a first frequency division signal.

2. The frequency division circuit according to claim 1, characterized in that: The calculation circuit comprises: a first sub-calculation circuit, configured to receive the software frequency division coefficient and the hardware frequency division coefficient, determine a first frequency division value according to the software frequency division coefficient, and determine a second frequency division value according to the hardware frequency division coefficient; and perform multiplication operation on the first frequency division value and the second frequency division value to obtain the target frequency division coefficient; The second sub-calculation circuit is used to receive the target frequency division coefficient, and perform calculation according to the target frequency division coefficient and the frequency division coefficient threshold to obtain the count lower limit value and the count upper limit value.

3. The frequency division circuit according to claim 2, characterized in that: The target frequency division coefficient is an N-bit binary number, and the frequency division coefficient threshold is the maximum value of an (N-1)-bit binary number; N is an integer greater than 1.

4. The frequency division circuit according to any one of claims 1 to 3, characterized in that: The frequency division circuit further includes: The output circuit is used to receive the first frequency division signal and a first selection signal, wherein the first selection signal is used to indicate the parity of the target frequency division coefficient; when the target frequency division coefficient is an even number, the first frequency division signal is output as the target frequency division signal; when the target frequency division coefficient is an odd number, the first frequency division signal is duty cycle adjusted and then output as the target frequency division signal.

5. The frequency division circuit according to claim 4, characterized in that: The output circuit comprises: a first selection circuit, a delay circuit and an OR gate; The first selection circuit is configured to receive the first selection signal, the preset signal, and the first frequency division signal; when the first selection signal indicates that the target frequency division coefficient is an even number, the first frequency division signal is sent to the delay circuit; when the first selection signal indicates that the target frequency division coefficient is an odd number, the preset signal is sent to the delay circuit; The delay circuit is used to delay the signal sent by the first selection circuit for a preset time length to obtain a second frequency-divided signal, and send the second frequency-divided signal to the OR gate; the preset time length is half of the clock period of the initial clock signal; The OR gate is used to receive the first frequency-divided signal and the second frequency-divided signal, and perform an OR operation on the first frequency-divided signal and the second frequency-divided signal to obtain the target frequency-divided signal.

6. The frequency division circuit according to claim 5, characterized in that: The first selection circuit includes a first selector, and the delay circuit includes a NOT gate and a trigger; The control end of the first selector receives the first selection signal, the first input end of the first selector receives the preset signal, the second input end of the first selector receives the first frequency-divided signal, and the output end of the first selector is connected to the input end of the trigger; The input end of the NOT gate receives the initial clock signal, the output end of the NOT gate is connected to the clock end of the trigger, and the output end of the trigger outputs the second frequency-divided signal.

7. The frequency division circuit according to claim 4, characterized in that: The first selection signal is the least significant bit of the target frequency division coefficient.

8. The frequency division circuit according to any one of claims 5 to 7, characterized in that: The frequency division circuit further includes: The second selection circuit is used to receive a second selection signal, the initial clock signal and the target frequency-divided signal, and select the initial clock signal or the target frequency-divided signal for output according to the second selection signal.

9. A frequency division method, characterized in that: The method comprises: Determine a target frequency division coefficient according to the software frequency division coefficient and the hardware frequency division coefficient; determine a lower count limit value and an upper count limit value according to the target frequency division coefficient and the frequency division coefficient threshold value; Counting is performed within the counting range represented by the counting lower limit value and the counting upper limit value according to the initial clock signal to obtain a counting signal; and the highest bit of the counting signal is output as a first frequency-divided signal.

10. A chip, characterized in that: The method comprises the frequency dividing circuit as claimed in any one of claims 1 to 8.

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