A driving assembly of a frequency divider and a driving method thereof

Abstract

The application provides a driving assembly of a frequency divider and a driving method thereof. The driving assembly comprises a clock selection module and a frequency division module connected in sequence. The clock selection module is used for controlling the selection of a frequency division reference clock and performing real-time non-glitch clock switching and reset synchronization. The frequency division module is used for generating high-precision frequency division clock outputs of any one of odd frequency division, even frequency division, fractional frequency division and fractional frequency division under different main frequencies according to configuration information configured outside a chip. The application can generate frequency division clock signals of different frequencies for multiple controlled device chips in the back end, greatly simplifies the overall structure of a high-precision frequency divider, improves the integration and efficiency of the driving assembly. Compared with a traditional scheme, the application can realize more complex and high-precision frequency division functions, and the difficulty of driving circuit design and verification is lower.

Description

Technical Field

[0001] This invention proposes a driving component and driving method for a frequency divider, belonging to the field of digital integrated circuits. Background Technology

[0002] A frequency divider circuit is used to divide the clock frequency according to a certain ratio, reducing the frequency of the input signal to the desired target frequency. Frequency dividers can support various modules and have many important functions in electronic systems. They are widely used in wireless communication, digital signal processing, and other fields, including clock generation, frequency synthesis, signal processing, timing, modulation / demodulation, and data transmission.

[0003] The current mainstream design approach for frequency divider circuits is a top-down design method. This involves first planning the clock division requirements at the top level, and then designing the preceding and following stages based on those requirements. This approach requires designing the frequency division requirements based on the overall chip's array driver circuit and readout circuit hardware structure, and finally designing the control logic to generate the target frequency clock. Designing and implementing fractional frequency dividers can be more complex than integer frequency dividers. The divider circuit has lower precision, less flexibility in adjusting the divided frequency, and high manpower and integration costs for subsequent verification. Therefore, more design and testing work is required, leading to increased costs. The complex design also results in higher power consumption and more circuit components. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention proposes a driving component and driving method for a frequency divider, which can greatly simplify the overall structure of a high-precision frequency divider and improve the system's integration and efficiency.

[0005] The technical solution adopted by the driving component of this invention is as follows:

[0006] A frequency divider driving component includes a clock selection module and a frequency division module connected in sequence; the clock selection module is used to control the selection of the frequency division reference clock and to perform real-time, glitch-free clock switching and reset synchronization; the frequency division module is used to configure and generate a high-precision frequency division clock output of any one of the following frequency division types: odd frequency division, even frequency division, fractional frequency division, and fractional frequency division, under different main frequencies, based on off-chip configuration information.

[0007] The present invention also provides a driving method using the driving component of the frequency divider described above, for generating frequency-divided clock signals of different frequencies for multiple controlled device chips in the back end.

[0008] Furthermore, the method for generating fractional frequency division using the driving component of the aforementioned frequency divider specifically includes the following steps:

[0009] S1, Reference Clock Selection: After receiving the external configuration information Config_Data, if the clock selection module contains only an external input signal including an input clock Clock and a reset signal Rst, the clock selection module will synchronize the external reset signal according to the input clock, and then output the synchronized reset signal Rst_n and the output reference clock Clock_ref to the subsequent frequency divider module; after receiving the controlled device chip type and operating mode signal Config_Type and multiple ideal arbitrary frequency reference clocks Clock_n, the frequency divider module is configured to select the reference clock Clock_ref based on the signal Config_Type after combination judgment logic; when the clock switching enable signal Clock_SelectValid is pulled high, the clock selection module realizes real-time, glitch-free clock switching according to the change of the controlled device chip type and operating mode signal Config_Type.

[0010] S2, Clock division: After receiving the off-chip configuration information Config_DivRatio, the frequency division module determines the type and division ratio of the divided clock through combinational logic, and configures the corresponding storage units for the fractional value of the divided frequency DivRatio_Fra, the fractional division period PeriodNum, the odd division high-level count value DivRatio_Int_M_1, and the even division high-level count value DivRatio_Int_M_2. The frequency division submodule starts working when the synchronous reset signal Rst_n is low. The frequency division submodules share the PeriodCounter counting unit to count according to the number of odd and even division periods. Under the control of the odd-even division switching flag signal PeriodFlag, the odd and even frequency division submodules are controlled to perform DivRatio_Int division of PeriodNum-DivRatio_Fra times and DivRatio_Int+1 division of DivRatio_Fra times within the period, thereby realizing the output of a high-precision divided clock.

[0011] Compared to traditional solutions, this invention can achieve more complex and higher-precision frequency division functions, while the design and verification of the drive circuit are simpler, and it has the following advantages:

[0012] (1) The driving component of the present invention decouples the original on-chip frequency divider clock generation module and divides it into two modules, including a clock selection module and a frequency divider module. Each module is flexible and adjustable. By combining them, the flexible configuration and switching of the driving clock frequency of different device chips in different modes can be realized, which meets the on-chip driving needs of multiple devices and multiple modes and improves the integration and efficiency of the driving component.

[0013] (2) The frequency divider module of the present invention has low hardware complexity and can be repeatedly instantiated in batches. The reusability of the frequency divider module shortens the design cycle. By instantiating multiple frequency divider modules, based on the off-chip configuration information and the ideal frequency divider reference clock, the flexible configuration and real-time switching of high-precision arbitrary frequency clocks in different modes of different devices can be met without additional custom design.

[0014] (3) The driving method of the present invention includes data configuration writing, device type division, frequency division storage unit configuration and frequency division clock driving configuration. This driving method can flexibly and efficiently configure and generate high-precision frequency division clock signals of arbitrary frequency division. Attached Figure Description

[0015] Figure 1 This is a block diagram of the numerical control circuit of the drive component of the frequency divider in an embodiment of the present invention;

[0016] Figure 2 This is a flowchart of the numerical control circuit driving method of the frequency divider driving component in an embodiment of the present invention;

[0017] Figure 3 This is a timing diagram of the fractional division drive of the frequency divider in an embodiment of the present invention (taking a division frequency of 3.12 as an example). Detailed Implementation

[0018] This invention proposes a driving component and driving method for a frequency divider. Using the driving component of this invention, the frequency divider can configure memory cell data for different modes of different controlled device chips based on the type and operating mode encoding information of the controlled device, and can provide multiple frequency division ratios of various controlled device chips in batches.

[0019] The driving components in this embodiment include a clock selection module and a frequency divider module. The clock selection module is used to control the selection of the frequency divider reference clock and to perform real-time, glitch-free clock switching and reset synchronization. It can select a suitable frequency divider reference clock according to the device chip type and operating mode. The frequency divider module can be used as a general-purpose modulation unit to generate a high-precision frequency divider clock output of any one of the following frequency divider types—odd-number divider, even-number divider, fractional divider, and decimal divider—at different main frequencies based on off-chip configuration information, thereby meeting the needs of different device chips.

[0020] This embodiment provides a method for driving a frequency divider, and the flowchart is as follows: Figure 1 As shown. Figure 1 In this context, Config_data represents off-chip configuration information; Clock_ref is the frequency division reference clock selected based on the device chip type and function mode; Rst_n is the synchronous reset signal; Clock_out is the output frequency division clock; and CountNum is the clock test count value.

[0021] Figure 2 A block diagram of the specific modules of the CNC circuit for the drive component is shown. Figure 2 In this code, Config_data, Config_DivRatio, and Config_Test are external data configuration parameters; Decoder is the decoding logic module; ClockSwitch is the clock switching module; Synchronous is the synchronization module; Clock_ref is the output reference clock; Rst_n is the synchronization reset signal; ODD FD is the odd-number divider module; EVEN FD is the even-number divider module; LR FD is the little-two divider module; Verif_Block is the divider clock verification module; Clock_out is the output divider clock; CountNum is the count value of the clock test module; Judge_Logic is the combinational judgment logic unit; and Data_Processing... Unit is the data processing unit; PeriodNum is the value configured for the fractional frequency division period storage unit; DivRatio_Fra is the value configured for the odd frequency division period storage unit in fractional frequency division; DivRatio_Int is the value configured for the frequency division round-down storage unit; DivRatio_Int_M_1 is the value configured for the odd frequency division high-level duration storage unit in fractional frequency division; DivRatio_Int_M_2 is the value configured for the even frequency division high-level duration storage unit in fractional frequency division; PeriodFlag is the odd-even frequency division switching flag signal; EvenCounter is the even frequency division counting unit; OddCounter is the odd frequency division counting unit; OddCounter_r is the odd frequency division delay counting unit; SinCounter is the reference clock counting unit; TestCounter is the test module counting unit.

[0022] The clock selection module adapts to one digital input signal and two digital output signals. The one digital input signal is the external data configuration information `Config_data`, and the two digital output signals are the output reference clock `Clock_ref` and the synchronous reset signal `Rst_n`. The external data configuration information `Config_data` includes n ideal arbitrary frequency input clocks `Clock_n` or the external input device reset signal `Rst`, where n ≥ 1. Alternatively, it may also include the device chip type and operating mode signal `Config_Type` and / or the clock switching enable signal `Clock_SelectValid`. The device chip type and operating mode signal `Config_Type` includes device number information and controlled device operating mode information, such as at least one of the following modes: programming mode, read / write mode, drive mode, etc.

[0023] Specifically, the clock selection module includes a decoding module (Decorder), a clock switching module (ClockSwitch), and a synchronization module (Synchronous). The decoding module decodes the external configuration information (Config_Type) signal and selects a suitable clock from n ideal arbitrary-frequency reference clocks (Clock_n) as the output reference clock (Clock_ref) via a selector. The external configuration information allows for real-time configuration but does not switch the output reference clock. The clock switching enable signal (Clock_SelectValid) and the external configuration information (Config_Type) together control the switching of the output reference clock. When the clock switching enable signal (Clock_SelectValid) is high, the clock switching module performs a glitch-free clock switch, avoiding glitches and clock jetting during switching, adapting to the various operating frequency requirements of different device chips in different modes. The synchronization module synchronizes the external reset signal (Rst) based on the selected output reference clock (Clock_ref), thereby preventing internal circuit metastability caused by the reset signal.

[0024] The frequency divider module adapts to at least three digital input signals and one digital output signal. In this embodiment, it adapts to four digital input signals: external configuration information `Config_DivRatio`, test module configuration information `Config_Test`, an output reference clock `Clock_ref` from the clock selection module, and a synchronization reset signal `Rst_n`. The one digital output signal is the frequency divider clock `Clock_out` required by the controlled device chip. The external configuration information `Config_DivRatio` includes the frequency division type, such as odd-number division, even-number division, fractional division, or integer-valued frequency division; or fractional-valued frequency division. The test module configuration information `Config_Test` includes the ideal high-frequency test clock `Clock_Test` and the test enable signal `Clock_Test_Valid`. The frequency divider clock `Clock_out` is preferably a one-dimensional array signal, but this is not a limitation.

[0025] Specifically, the frequency divider module includes a decoding module, an odd-number frequency divider submodule (ODD FD), an even-number frequency divider submodule (EVEN FD), a little-two frequency divider submodule (LR FD), and a frequency divider clock test module. Each of the odd-number, even-number, and little-two frequency divider submodules can be instantiated as k module groups, where k can be customized according to different requirements. If only a single odd-number frequency divider is implemented, only the odd-number frequency divider submodule needs to be instantiated. For a general-purpose frequency divider that can meet the frequency divider requirements of multiple devices, instantiating the same number of submodules is more convenient for front-end and back-end design. Here, k is the number of frequency divider clocks, and k is a positive integer. The frequency divider module can be expanded according to the device chip type and function. Each of the k module groups can work independently and simultaneously generate frequency divider clocks at different frequencies. The decoding module decodes the data based on the configuration information Config_DivRatio and outputs the decoded data to internal sub-modules for data configuration and selection. Sub-modules not selected remain in standby mode. The internal k sub-modules output clocks with different division frequencies under the same main clock frequency. Specifically, the decoding module includes a judgment logic unit and a data processing unit. The judgment logic unit decodes the external configuration information Config_DivRatio through internal combinational logic, and selects the subsequent k module groups based on the division type and division frequency, configuring the data in the storage units DivRatio_Fra and PeriodNum. The data processing unit processes the external configuration information Config_DivRatio and configures the storage units DivRatio_Int_M_1 and DivRatio_Int_M_2. Odd-division sub-modules can be configured to generate odd-division clocks with a duty cycle of 0.5. Even-division sub-modules can be configured to generate even-division clocks with a duty cycle of 0.5. The small-scale divider submodule can be configured to generate high-precision fractional dividers with a division frequency less than 2 to meet the requirements for the quality of the divided clock. High-precision fractional dividers with a division frequency greater than 2 are generated by the odd-scale divider submodule and the even-scale divider submodule working together. The divided clock test module starts working after receiving the test enable signal Clock_Test_Valid. It uses the test clock Clock_Test to sample and count the output divided clock. The count value is stored in the built-in memory unit of the divided clock test module, and the output is the clock test count value CountNum, which is used to determine the division accuracy of the divided clock.

[0026] The specific driving process of the frequency divider module is as follows: In the decoding module, the judgment logic unit determines the frequency division type based on the off-chip configuration information Config_DivRatio and selects the subsequent k module groups. When one module group's frequency division type is 2'b10 decimal division, the decimal value of the frequency division is decoded into DivRatio_Fra and PeriodNum and input to the frequency division submodule. DivRatio_Fra is the decimal value of the frequency division, i.e., the number of divisions within the DivRatio_Int+1 division period. PeriodNum is the decimal division period, and PeriodNum-DivRatio_Fra is the number of divisions within the DivRatio_Int division period. When the frequency division has one decimal place, PeriodNum is 10; when the frequency division has two decimal places, PeriodNum is 100. The integer value of the frequency division is decoded into DivRatio_Int and input to the data processing unit, where it is calculated using the following formula:

[0027] Odd-number frequency division high-level count value

[0028] Even-numbered frequency division high-level count value

[0029] The odd-number division high-level count value DivRatio_Int_M_1 and the even-number division high-level count value DivRatio_Int_M_2 are configured for the odd-number division submodule and the even-number division submodule, respectively. The submodules start working after the synchronous reset Rst_n is pulled low. The built-in counting units OddCounter and OddCounter_r of the odd-number division submodule start counting on the rising and falling edges of the division reference clock Clock_ref, respectively, when the odd-even division switching flag signal PeriodFlag is high, and output a high-level signal. When the count value of the counting unit is greater than DivRatio_Int_M_1, it outputs a low-level signal. When the count reaches the division number, the built-in counting unit resets and starts counting again. The output of the two counting units after passing through a logic AND gate is the odd-number division clock Clk_odd. The even-division submodule also utilizes the built-in counting unit EvenCounter to start working when the odd / even division switching flag signal PeriodFlag is low, based on the even-division high-level count value DivRatio_Int_M_2. It outputs the even-division clock Clk_Even. Both submodules share the PeriodCounter counting unit, which counts the number of divisions within odd and even division periods (i.e., PeriodNum - DivRatio_Fra and DivRatio_Fra) to control the pull-up or pull-down of the odd / even division switching flag signal PeriodFlag. Using the count values ​​from PeriodFlag and the PeriodCounter unit, the odd and even division submodules achieve high-precision fractional division of arbitrary frequencies through the combination of DivRatio_Int and DivRatio_Int+1 divisions.

[0030] When the frequency division type is 2'b11 fractional frequency division, the integer and decimal values ​​of the fractional frequency division represent the denominator and numerator values, respectively. The numerator value of the fractional frequency division is decoded as PeriodNum and input to the post-frequency division submodule, while the denominator value T1 and numerator value T2 of the fractional frequency division are input to the data processing unit.

[0031] DivRatio_Int = T1 / T2

[0032] DivRatio_Fra = T1mod T2

[0033]

[0034] For fractional frequency division, both frequency division submodules share the PeriodCounter counting unit, counting based on odd and even division cycles. High-precision fractional frequency division is achieved using DivRatio_Int divisions of PeriodNum-DivRatio_Fra times and DivRatio_Int+1 times within a cycle. When the division frequency is a fractional frequency between 1 and 2, the frequency division submodule uses a small-two frequency division submodule for high-precision division. The small-two frequency division submodule uses built-in counting units SinCounter and EvenCounter to count the duration of high and low levels in the divided clock. The signals output from the two counting units pass through a clock switching selection module to avoid glitches caused by clock switching selection at lower division frequencies, which would result in poor divided clock quality. The frequency divider submodule ensures the correctness of the divided clock through a primary data selector before inputting it to the subsequent frequency divider clock test module. When the divided frequency is less than 1, the component's built-in protection logic directly selects the frequency divider reference clock Clock_ref as the divided clock output Clock_out in the primary data selector. The frequency divider clock test module tests the divided clock based on the external configuration information Config_Test. The Config_Test signal includes the ideal high-frequency test clock Clock_Test and the test enable signal Clock_Test_Valid. The ideal high-frequency test clock Clock_Test samples and counts the output divided clock when the test enable signal Clock_Test_Valid is high. The count value is stored in the built-in memory unit of the frequency divider clock test module, and the output is the clock test count value CountNum. The external module determines the accuracy of the divided clock by comparing the high level duration of Clock_Test_Valid with the output signal CountNum of the clock test module.

[0035] Figure 3The timing diagram for generating a fractional-division clock using a division frequency of 3.12 as an example is shown. In the decoding module, the decision logic unit decodes the fractional value of the division frequency into DivRatio_Fra and PeriodNum based on the off-chip configuration information Config_DivRatio, and inputs them to the division subunit. The fractional value DivRatio_Fra is 12, and the fractional division period PeriodNum is 100. The integer value of the division frequency is decoded into DivRatio_Int and input to the data processing unit. The high-level count value DivRatio_Int_M_1 for odd-number divisions is calculated to be 1, and the high-level count value DivRatio_Int_M_2 for even-number divisions is calculated to be 2. The two frequency division submodules share the PeriodCounter counting unit, which counts based on the number of odd and even frequency division cycles. When the odd / even frequency division switching flag signal PeriodFlag is high, the odd frequency division submodule is controlled to perform DivRatio_Int(3) frequency division for the number of PeriodNum-DivRatio_Fra(88) times within the cycle. When the odd / even frequency division switching flag signal PeriodFlag is low, the even frequency division submodule is controlled to perform DivRatio_Int+1(4) frequency division for the number of DivRatio_Fra(12) times within the cycle to achieve high-precision 3.13 frequency division.

[0036] The frequency divider driving component provided by this invention can be configured with the division ratio and clock switching selection externally. It can meet the needs of different devices for flexible configuration and real-time switching of different frequency division clocks in multiple modes without additional custom design, thus improving the flexibility of high-precision frequency dividers.

Claims

1. A drive assembly for a frequency divider, characterized in that, The driving component includes a clock selection module and a frequency division module connected in sequence; The clock selection module is used to control the selection of the frequency division reference clock and to perform real-time, glitch-free clock switching and reset synchronization. The frequency division module is used to generate a high-precision frequency division clock output based on the off-chip configuration information, which can be any one of the frequency division types (odd frequency division, even frequency division, fractional frequency division, and decimal frequency division) under different main frequencies. The clock selection module is compatible with one digital input signal and two digital output signals. The one digital input signal is the external data configuration information Config_data, and the two digital output signals are the output reference clock Clock_ref and the synchronous reset signal Rst_n. The external data configuration information Config_data includes n ideal arbitrary frequency input clocks Clock_n or external input device reset signals Rst, n≥1, or it may also include the device chip type and operating mode signal Config_Type and / or the clock switching enable signal Clock_SelectValid. The clock selection module includes a decoding module, a clock switching module, and a synchronization module; The decoding module decodes the device chip type and the operating mode signal Config_Type, and selects a suitable frequency division reference clock Clock_ref; the clock switching module performs real-time, glitch-free clock switching based on the clock switching enable signal Clock_SelectValid, adapting to the various operating frequency requirements of different device chips in different modes; the synchronization module synchronizes the external reset signal Rst based on the reference clock Clock_ref, thereby avoiding the generation of internal circuit metastability caused by the reset signal; The frequency divider module is adapted to at least three digital input signals and one digital output signal. The at least three digital input signals are the off-chip configuration information Config_DivRatio, the reference clock Clock_ref from the clock selection module, and the synchronous reset signal Rst_n. The one digital output signal is the frequency divider clock Clock_out required by the controlled device chip. The frequency division module includes a decoding module, an odd frequency division submodule, an even frequency division submodule, a small-two frequency division submodule, and a frequency division clock testing module. The odd frequency division submodule is used to configure and generate an odd frequency division clock with a duty cycle of 0.

5. The even frequency division submodule is used to configure and generate an even frequency division clock with a duty cycle of 0.

5. The small-two frequency division submodule is used to configure and generate a high-precision fractional frequency division with a division frequency of less than 2.

2. The driving component of a frequency divider according to claim 1, characterized in that, The off-chip configuration information Config_DivRatio includes the frequency division type, integer value of the frequency division, and decimal value of the frequency division.

3. The driving component of a frequency divider according to claim 1, characterized in that, The frequency division clock test module tests the frequency division clock based on the external configuration signal Config_Test. The signal Config_Test includes an ideal high-frequency test clock Clock_Test and a test enable signal Clock_Test_Valid. When the test enable signal Clock_Test_Valid is high, the test clock Clock_Test samples and counts the output frequency division clock. The count value is stored in the built-in storage unit of the frequency division clock test module, and the output is the clock test count value CountNum, which is used to determine the frequency division accuracy of the frequency division clock.

4. The driving component of a frequency divider according to claim 1, characterized in that, The odd-number frequency division submodule, even-number frequency division submodule, and little-two frequency division submodule can be expanded to k, where k is the number of frequency division clocks and k is a positive integer; the decoding module decodes according to the data configuration information and outputs the decoded data to each submodule to configure and select the submodules, while the unselected submodules are in standby mode. The k submodules realize the frequency division clock output of different division frequencies under the same clock master frequency.

5. A driving method using the driving component of a frequency divider as described in claim 1, characterized in that, The device includes a drive component for a frequency divider as described in any one of claims 1 to 4, used to generate frequency-divided clock signals of different frequencies for multiple controlled device chips in the back end.

6. The driving method according to claim 5, characterized in that, This driving method generates fractional frequency divisions, specifically including the following steps: S1, Reference Clock Selection: After receiving the external configuration information Config_Data, if the clock selection module contains only an external input signal including an input clock Clock and a reset signal Rst, the clock selection module will synchronize the external reset signal according to the input clock, and then output the synchronized reset signal Rst_n and the output reference clock Clock_ref to the subsequent frequency divider module; after receiving the controlled device chip type and operating mode signal Config_Type and multiple ideal arbitrary frequency reference clocks Clock_n, the frequency divider module is configured to select the reference clock Clock_ref based on the signal Config_Type after combination judgment logic; when the clock switching enable signal Clock_SelectValid is pulled high, the clock selection module realizes real-time, glitch-free clock switching according to the change of the controlled device chip type and operating mode signal Config_Type. S2, Clock frequency division: After receiving the off-chip configuration information Config_DivRatio, the frequency division module determines the type and division ratio of the frequency division clock through combinational logic, and configures the corresponding storage units for the fractional value of the division frequency DivRatio_Fra, the fractional division period PeriodNum, the odd division high-level count value DivRatio_Int_M_1, and the even division high-level count value DivRatio_Int_M_2. The frequency division submodule starts working when the synchronous reset signal Rst_n is low. The frequency division submodules share the PeriodCounter counting unit to count according to the number of odd and even division periods. Under the control of the odd-even division switching flag signal PeriodFlag, the odd and even frequency division submodules are controlled to perform DivRatio_Int division by PeriodNum - DivRatio_Fra times and DivRatio_Int+1 division by DivRatio_Fra times within the period, thereby realizing the output of a high-precision frequency division clock.

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