Analog-to-digital conversion circuit, digital filter circuit and control method

Abstract

The invention discloses an analog-to-digital conversion circuit, a digital filter circuit and a control method. The analog-to-digital conversion circuit comprises a receiving circuit and a delta-sigma analog-to-digital converter. The receiving circuit receives a first analog input and a second analog input, and takes the first analog input or the second analog input as an output signal according to a control signal. The delta-sigma analog-to-digital converter converts the output signal to generate an input data. The delta-sigma analog-to-digital converter oversamples input data and stores a sampling result. The delta-sigma analog-to-digital converter generates output data according to the sampling result.

Description

Technical Field

[0001] The present invention relates to an analog-to-digital conversion circuit, in particular to an analog-to-digital conversion circuit with multiple channels. Background Art

[0002] With the advancement of technology, the types and functions of electronic devices are increasing. Most electronic devices have an analog-to-digital converter (ADC). The analog-to-digital converter converts an analog signal into a digital signal. However, if multiple analog signals need to be converted, multiple analog-to-digital converters need to be set up. Summary of the invention

[0003] One embodiment of the present invention provides an analog-to-digital conversion circuit, including a receiving circuit and a delta-sigma analog-to-digital converter. The receiving circuit receives a first analog input and a second analog input, and uses the first or second analog input as an output signal according to a control signal. The delta-sigma analog-to-digital converter converts the output signal to generate an output data, and includes a differential amplifier, an integrator, a quantizer, a digital filter circuit, and a digital-to-analog conversion circuit. The differential amplifier amplifies the difference between the output signal and a reference signal to generate an amplified signal. The integrator accumulates the amplified signal to generate an integrated signal. The quantizer quantizes the integrated signal to generate input data. The digital-to-analog conversion circuit converts the input data to generate a reference signal. The digital filter circuit oversamples the input data according to the control signal to generate output data.

[0004] The present invention further provides a digital filter circuit, which oversamples an input data to generate an output data, and includes an integrator circuit, a frequency reduction circuit and a comb filter circuit. The integrator circuit includes a first integrator and a second integrator. The first integrator includes a first adder, a first selection circuit, a first register, a second register and a second selection circuit. The first adder sums the input data and a first temporary storage value to generate a first calculation value. The first selection circuit uses the first calculation value as a first output value or a second output value according to a control signal. The first register stores the first output value. The second register stores the second output value. The second selection circuit uses the first output value stored in the first register or the second output value stored in the second register as the first temporary storage value according to the control signal. The second integrator is connected in series with the first integrator, and includes a second adder, a third selection circuit, a third register, a fourth register and a fourth selection circuit. The second adder adds the first calculated value and the second temporary storage value to generate a second calculated value. The third selection circuit uses the second calculated value as a third output value or a fourth output value according to the control signal. The third temporary storage stores the third output value. The fourth temporary storage stores the fourth output value. The fourth selection circuit uses the third output value stored in the third temporary storage or the fourth output value stored in the fourth temporary storage as the second temporary storage value according to the control signal. The down-conversion circuit down-samples the second calculated value to generate a processed value. The comb filter circuit includes a first comb filter and a second comb filter. The first comb filter includes: a first subtractor, a fifth selection circuit, a fifth temporary storage, a sixth temporary storage and a sixth selection circuit. The first subtractor subtracts the processed value from the third temporary storage value to generate a third calculated value. The fifth selection circuit uses the processed value as a fifth output value or a sixth output value according to the control signal. The fifth temporary storage stores the fifth output value. The sixth temporary storage stores the sixth output value. The sixth selection circuit uses the fifth output value stored in the fifth register or the sixth output value stored in the sixth register as the third temporary storage value according to the control signal. The second comb filter includes a fourth subtractor, a seventh selection circuit, a seventh register, an eighth register and an eighth selection circuit. The fourth subtractor subtracts the third calculated value from the fourth temporary storage value to generate a fourth calculated value. The seventh selection circuit uses the processed value as a seventh output value or an eighth output value according to the control signal. The seventh register stores the seventh output value. The eighth register stores the eighth output value. The eighth selection circuit uses the seventh output value stored in the seventh register or the eighth output value stored in the eighth register as the fourth temporary storage value according to the control signal.

[0005] The present invention further provides a control method, which is applicable to an analog-to-digital converter and includes: receiving a first analog input generated by a first sensing circuit; receiving a second analog input generated by a second sensing circuit; according to a control signal, using the first or second analog signal as an output signal; converting the output signal to generate an input data. The output signal is in an analog format. The output data is in a digital format. When the first analog signal is used as the output signal, oversampling the input data to generate a plurality of first sampling results; storing the first sampling results in a first temporary storage circuit; generating output data according to the first sampling results. When the second analog signal is used as the output signal: oversampling the input data to generate a plurality of second sampling results; storing the second sampling results in a second temporary storage circuit; generating output data according to the second sampling results.

[0006] The control method of the present invention can be implemented through the analog-to-digital converter of the present invention, which is hardware or software that can perform specific functions, or can be recorded in a recording medium in the form of a program and implemented in combination with specific hardware. When the program is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes an analog-to-digital converter for implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a schematic diagram of an analog-to-digital conversion circuit of the present invention.

[0008] Figure 2 Schematic diagram of the digital filter circuit of the present invention.

[0009] Figure 3 This is a possible embodiment of the digital filter circuit of the present invention.

[0010] Figure 4 FIG. 4 is a schematic diagram of the operation of the analog-to-digital conversion circuit of the present invention.

[0011] Figure 5 It is a schematic flow chart of the control method of the present invention.

[0012] Description of Figure Numbers:

[0013] 100: Analog-to-digital conversion circuit

[0014] 110: Receiving circuit

[0015] 111, 112: Channel

[0016] 120: Delta-Sigma Analog-to-Digital Converter

[0017] 121: Differential Amplifier

[0018] 122: Integrator

[0019] 123: Quantizer

[0020] 124: Digital filter circuit

[0021] 125: Digital to analog conversion circuit

[0022] 130: Control circuit

[0023] 140: Programmable Gain Amplifier

[0024] AIN_1, AIN_2: analog input

[0025] SC: Control signal

[0026] SO: Output signal

[0027] SOA: Amplifying the Signal

[0028] SODA: Output Data

[0029] SRF: Reference signal

[0030] SAMP: Amplify the signal

[0031] SIT: Integral Signal

[0032] SIDA: Input Data

[0033] 210, 310: Integrator circuit

[0034] 211, 212, 311, 312: Integrator

[0035] 220, 320: frequency reduction circuit

[0036] 230, 330: Comb filter circuit

[0037] 231, 232, 331, 332: Comb filter

[0038] CH1_1~CH1_4, CH2_1~CH2_4, RG_1~RG_8: register

[0039] AD_1, AD_2: Adders

[0040] SB_1, SB_2: Subtractor

[0041] SEL_1~SEL_8:Selection circuit

[0042] V_1~V_4: Temporary storage value

[0043] C_1~C_4:Calculated values

[0044] O_1~O_8:output value

[0045] PV: Processing Value

[0046] 410, 420, 430-460: Operation period

[0047] 411, 421: Stable period

[0048] 412, 422: Conversion period

[0049] S511~S522: Steps DETAILED DESCRIPTION

[0050] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the following examples are specifically cited and described in detail with the accompanying drawings. The present invention specification provides different examples to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each element in the example is for illustrative purposes and is not intended to limit the present invention. In addition, some repetitions of the figure numbers in the examples are for the purpose of simplifying the description and do not mean the correlation between different examples.

[0051] Figure 1 Schematic diagram of an analog-to-digital conversion circuit of the present invention. The analog-to-digital conversion circuit 100 includes a receiving circuit 110 and a delta-sigma analog-to-digital converter 120. The receiving circuit 110 is coupled to channels 111 and 112 to receive analog inputs AIN_1 and AIN_2. The receiving circuit 110 uses the analog input AIN_1 or AIN_2 as an output signal SO according to a control signal SC. The present invention does not limit the architecture of the receiving circuit 110. In one possible embodiment, the receiving circuit 110 is a multiplexer.

[0052] In other embodiments, the analog-to-digital conversion circuit 100 further includes a control circuit 130. The control circuit 130 sets the control signal SC to switch continuously between a first state (such as a low level) and a second state (such as a high level) according to a set value (not shown). For example, when the set value is a specific value (such as 0), the control circuit 130 sets the control signal SC to a first state. At this time, the receiving circuit 110 may use the analog signal AIN_1 as the output signal SO. When the set value is not a specific value, the control circuit 130 sets the control signal SC to a second state. At this time, the receiving circuit 110 may use the analog signal AIN_2 as the output signal SO. The set value may be written into the control circuit 130 in advance, or it may be adjusted arbitrarily by the user according to actual needs. In other words, the user may instruct the receiving circuit 110 to use the corresponding analog input as the output signal SO through the control circuit 130.

[0053] The present invention does not limit the number of control signals. In one possible embodiment, when the receiving circuit 110 receives more analog signals, the control circuit 130 provides more control signals. The receiving circuit 110 selects a suitable analog signal according to the levels of all control signals.

[0054] The present invention does not limit the number of channels. In other embodiments, the receiving circuit 110 is coupled to more or fewer channels. In one possible embodiment, channels 111 and 112 are each coupled to a first sensing circuit and a second sensing circuit. The physical characteristics (such as temperature, humidity) or electrical characteristics (voltage, current, frequency) sensed by the first sensing circuit may be the same as or different from the physical characteristics or electrical characteristics sensed by the second sensing circuit. For example, the first sensing circuit may be used to sense temperature, and the second sensing circuit may be used to sense an external voltage. In this example, the sensing signal generated by the first sensing circuit is used as the analog input AIN_1, and the sensing signal generated by the second sensing circuit is used as the analog input AIN_2.

[0055] In one possible embodiment, each of the analog inputs AIN_1 and AIN_2 is a differential signal. In this example, the output signal SO is also a differential signal. In another possible embodiment, the receiving circuit 110 has a conversion circuit (not shown) for converting the analog input AIN_1 or AIN_2 into a differential signal. In this example, the converted differential signal is used as the output signal SO.

[0056] In some embodiments, the analog-to-digital conversion circuit 100 further includes a programmable gain amplifier (PGA) 140. The PGA 140 is coupled between the receiving circuit 110 and the delta-sigma analog-to-digital converter 120. The PGA 140 amplifies the output signal SO to generate an amplified signal SOA.

[0057] The delta-sigma analog-to-digital converter 120 converts the output signal SO or the amplified signal SOA to generate an output data SODA. In the present embodiment, the delta-sigma analog-to-digital converter 120 includes a differential amplifier 121, an integrator 122, a quantizer 123, a digital filter circuit 124, and a digital-to-analog converter circuit (DAC) 125.

[0058] The differential amplifier 121 amplifies the difference between the output signal SO and a reference signal SRF to generate an amplified signal SAMP. The integrator 122 accumulates the amplified signal SAMP to generate an integrated signal SIT. The quantizer 123 quantizes the integrated signal SIT to generate an input data SIDA. The digital-to-analog conversion circuit 125 converts the input data SIDA to generate the reference signal SRF. The digital filter circuit 124 oversamples the input data SIDA according to the control signal SC to generate the output data SODA.

[0059] For example, when the control signal SC meets a preset state (such as a low level), the receiving circuit 110 uses the analog input AIN_1 as the output signal SO. The digital filter circuit 124 oversamples the input data SIDA to generate a plurality of first sampling results, and stores the plurality of first sampling results in a first temporary storage circuit. After a settling time, the digital filter circuit 124 completes the oversampling operation. Then, the digital filter circuit 124 generates the output data SODA according to the plurality of first sampling results. When the control signal SC does not meet the preset state, for example, the control signal SC is a high level, the receiving circuit 110 uses the analog input AIN_2 as the output signal SO. The digital filter circuit 124 oversamples the input data SIDA to generate a plurality of second sampling results, and stores the plurality of second sampling results in a second temporary storage circuit. After a settling time, the digital filter circuit 124 completes the oversampling operation. Then, the digital filter circuit 124 generates the output data SODA according to the plurality of second sampling results.

[0060] In this embodiment, the input data SIDA may be 1-bit data. After the digital filter circuit 124 performs an oversampling operation on the input data SIDA, the input data SIDA is expanded into multiple bits. For example, it is assumed that the digital filter circuit 124 performs 34 sampling operations on the input data SIDA. In this example, the stabilization time of the digital filter circuit 124 is the time for performing 34 sampling operations. In other words, after 34 sampling operations, the sampled data reaches stability. Therefore, the digital filter circuit 124 generates the output data SODA according to the sampled data.

[0061] In one possible embodiment, the digital filter circuit 124 may shift the sampling result, such as selecting the higher 24 bits of data and omitting the lower 10 bits of data. In some embodiments, the digital filter circuit 124 may directly use the 34-bit sampling data as the output data SODA.

[0062] When the receiving circuit 110 uses the analog signal AIN_1 as the output signal SO, the digital filter circuit 124 stores a plurality of first sampling results in a first temporary storage circuit. When the receiving circuit 110 uses the analog signal AIN_2 as the output signal SO, the digital filter circuit 124 stores a plurality of second sampling results in a second temporary storage circuit and retains the data stored in the first temporary storage circuit (the first sampling results). Therefore, when the receiving circuit 110 uses the analog signal AIN_1 as the output signal SO again, since the digital filter circuit 124 retains the previous sampling results of the analog signal AIN_1, the digital filter circuit 124 does not need to wait for a stable time (such as 34 sampling times), thereby speeding up the speed at which the digital filter circuit 124 provides the output data SODA. Similarly, when the receiving circuit 110 uses the analog signal AIN_2 as the output signal SO again, since the digital filter circuit 124 retains the data stored in the second temporary storage circuit (i.e., the previous sampling results of the analog signal AIN_2). Therefore, the digital filter circuit 124 does not need to wait for a stable time.

[0063] In addition, by receiving the sensing results (such as AIN_1 and AIN_2) from different sensing circuits through the receiving circuit 110, a single analog-to-digital conversion circuit 100 can convert different analog inputs, thereby improving the efficiency of the analog-to-digital conversion circuit 100. Since it is not necessary to set up multiple analog-to-digital conversion circuits for different analog inputs, the cost of components can be greatly reduced. Furthermore, although the digital filter circuit 124 retains the old sampling results, the analog inputs AIN_1 and AIN_2 will not change significantly in a short period of time, so the old sampling results will not affect the accuracy of the output data SODA. Taking the analog input AIN_1 as an example, it is assumed that the analog input AIN_1 is related to the ambient temperature. In this example, since the ambient temperature will not change suddenly and significantly, the digital filter circuit 124 can still provide the correct output data SODA.

[0064] Figure 2 Schematic diagram of the digital filter circuit of the present invention. Figure 2 As shown, the digital filter circuit 124 includes an integrator circuit 210, a frequency reduction circuit 220, and a comb filter circuit 230. In this embodiment, the digital filter circuit 124 is a cascaded integrator comb (CIC) filter.

[0065] The integrator circuit 210 includes integrators 211 and 212. The integrators 211 and 212 are connected in series. The integrator 211 includes registers CH1_1 and CH2_1. The integrator 212 includes registers CH1_2 and CH2_2. The registers CH1_1 and CH1_2 are used to store the sampling results of the analog signal AIN_1 from the channel 111. The registers CH2_1 and CH2_2 are used to store the sampling results of the analog signal AIN_2 from the channel 112. The present invention does not limit the number of integrators. In other embodiments, the integrator circuit 210 includes more integrators.

[0066] The down-conversion circuit 220 is coupled between the integrator circuit 210 and the comb filter circuit 230 . The down-conversion circuit 220 down-samples the sampling result of the integrator 212 and provides the down-conversion sampling result to the comb filter circuit 230 .

[0067] The comb filter circuit 230 includes comb filters 231 and 232. The comb filters 231 and 232 are connected in series. The comb filter 231 includes registers CH1_3 and CH2_3. The comb filter 232 includes registers CH1_4 and CH2_4. Registers CH1_3 and CH1_4 are used to store the sampling results of the analog signal AIN_1 from the channel 111. Registers CH2_3 and CH2_4 are used to store the sampling results of the analog signal AIN_2 from the channel 112. The present invention does not limit the number of comb filters. In other embodiments, the comb filter circuit 230 includes more comb filters.

[0068] The present invention does not limit the number of registers of each integrator and each comb filter. In the present embodiment, the number of registers of the integrator and the comb filter is related to the number of channels of the analog-to-digital conversion circuit 100. For example, since the analog-to-digital conversion circuit 100 has channels 111 and 112, the integrators 211 and 212 each have two registers, and the comb filters 231 and 232 each have two registers. In other embodiments, when the analog-to-digital conversion circuit 100 has more channels, the integrator and the comb filter have more registers.

[0069] When the receiving circuit 110 uses the analog signal AIN_1 as the output signal SO, after being processed by the differential amplifier 121, the integrator 122, the quantizer 123 and the digital-to-analog conversion circuit 125, the digital filter circuit 124 oversamples the input data SIDA to generate a plurality of first sampling results. The digital filter circuit 124 stores the first sampling results in the registers CH1_1 to CH1_4. In this example, the registers CH1_1 to CH1_4 serve as a first temporary storage circuit. The digital filter circuit 124 generates the output data SODA according to the data stored in CH1_1 to CH1_4.

[0070] When the receiving circuit 110 uses the analog signal AIN_2 as the output signal SO, after being processed by the differential amplifier 121, the integrator 122, the quantizer 123 and the digital-to-analog conversion circuit 125, the digital filter circuit 124 oversamples the input data SIDA to generate a plurality of second sampling results. The digital filter circuit 124 stores the second sampling results in the registers CH2_1 to CH2_4. The registers CH2_1 to CH2_4 constitute a second temporary storage circuit. The digital filter circuit 124 generates the output data SODA according to the data stored in the registers CH2_1 to CH2_4.

[0071] In some embodiments, the digital filter circuit 124 generates output data SODA according to the data in the registers CH2_1 to CH2_4, while the digital filter circuit 124 retains the data in the registers CH1_1 to CH1_4 (i.e., the first sampled data). Similarly, when the digital filter circuit 124 generates output data SODA according to the data in the registers CH2_1 to CH2_4, the digital filter circuit 124 retains the data in the registers CH2_1 to CH2_4 (i.e., the second sampled data).

[0072] The present invention does not limit the number of bits of the sampled data. In one possible embodiment, the number of bits of the sampled data is related to the number of times the digital filter circuit 124 performs the sampling operation. For example, assume that the digital filter circuit 124 performs 34 sampling operations on the input data SIDA. In this example, the sampled data has 34 bits.

[0073] Figure 3 A possible embodiment of the digital filter circuit of the present invention. The digital filter circuit 124 includes an integrator circuit 310, a frequency reduction circuit 320 and a comb filter circuit 330. The integrator circuit 310 includes integrators 311 and 312. The present invention does not limit the number of integrators. In another possible embodiment, the integrator circuit 310 has more integrators.

[0074] The integrator 311 includes an adder AD_1, selection circuits SEL_1, SEL_2, and registers RG_1, RG_2. The adder AD_1 adds the input data SIDA and a temporary value V_1 to generate a calculated value C_1. The selection circuit SEL_1 uses the calculated value C1 as the output value O_1 or O_2 according to the control signal SC. For example, when the control signal SC meets a preset state (such as a low level), the selection circuit SEL_1 uses the calculated value C1 as the output value O_1. When the control signal SC does not meet the preset state, the selection circuit SEL_1 uses the calculated value C1 as the output value O_2.

[0075] The registers RG_1 and RG_2 are coupled to the selection circuit SEL_1. When the selection circuit SEL_1 uses the calculated value C_1 as the output value O_1, the register RG_1 stores the output value O_1. When the selection circuit SEL_1 uses the calculated value C_1 as the output value O_2, the register RG_2 stores the output value O_2.

[0076] The selection circuit SEL_2 is coupled to the registers RG_1 and RG_2. The selection circuit SEL_2 reads the register RG_1 or RG_2 according to the control signal SC. For example, when the control signal SC meets a preset state, the selection circuit SEL_2 reads the register RG_1. The selection circuit SEL_2 uses the output value O_1 stored in the register RG_1 as the temporary value V_1, and provides the temporary value V_1 to the adder AD_1. When the control signal SC does not meet the preset state, the selection circuit SEL_2 reads the register RG_2. The selection circuit SEL_2 uses the output value O_2 stored in the register RG_2 as the temporary value V_1, and provides the temporary value V_1 to the adder AD_1.

[0077] The integrator 312 is connected in series with the integrator 311, and includes an adder AD_2, selection circuits SEL_3, SEL_4, and registers RG_3, RG_4. The adder AD_2 adds the calculated value C_1 and the stored value V_2 to generate a calculated value C_2. The selection circuit SEL_3 uses the calculated value C_2 as an output value O_3 or O_4 according to the control signal SC. For example, when the control signal SC meets a preset state (such as a low level), the selection circuit SEL_3 uses the calculated value C2 as the output value O_3. When the control signal SC does not meet the preset state, the selection circuit SEL_3 uses the calculated value C2 as the output value O_4.

[0078] The registers RG_3 and RG_4 are coupled to the selection circuit SEL_3. When the selection circuit SEL_3 uses the calculated value C_2 as the output value O_3, the register RG_3 stores the output value O_3. When the selection circuit SEL_3 uses the calculated value C_2 as the output value O_4, the register RG_4 stores the output value O_4.

[0079] The selection circuit SEL_4 reads the register RG_3 or RG_4 according to the control signal SC. For example, when the control signal SC meets a preset state, the selection circuit SEL_4 reads the register RG_3. The selection circuit SEL_4 uses the output value O_3 stored in the register RG_3 as the temporary value V_2, and provides the temporary value V_2 to the adder AD_2. When the control signal SC does not meet a preset state, the selection circuit SEL_4 reads the register RG_4. The selection circuit SEL_4 uses the output value O_4 stored in the register RG_4 as the temporary value V_2, and provides the temporary value V_2 to the adder AD_2.

[0080] The down-conversion circuit 320 performs a down-conversion sampling operation on the calculated value C_2 to generate a processed value PV. The comb filter circuit 330 receives the processed value PV and includes comb filters 331 and 332. In this embodiment, the number of comb filters is the same as the number of integrators. The present invention does not limit the number of comb filters. In other embodiments, the comb filter circuit 330 may have more comb filters.

[0081] The comb filter 331 includes a subtractor SB_1, selection circuits SEL_5, SEL_6, registers RG_5 and RG_6. The subtractor SB_1 subtracts the processing value PV from the temporary value V3 to generate a calculated value C3. The selection circuit SEL_5 uses the processing value PV as the output value O_5 or O_6 according to the control signal SC. For example, when the control signal SC meets a preset state (such as a low level), the selection circuit SEL_5 uses the processing value PV as the output value O_5. When the control signal SC does not meet the preset state, the selection circuit SEL_5 uses the processing value PV as the output value O_6.

[0082] The registers RG_5 and RG_6 are coupled to the selection circuit SEL_5. When the selection circuit SEL_5 uses the processing value PV as the output value O_5, the register RG_5 stores the output value O_5. When the selection circuit SEL_5 uses the processing value PV as the output value O_6, the register RG_6 stores the output value O_6.

[0083] The selection circuit SEL_6 is coupled to the registers RG_5 and RG_6. The selection circuit SEL_6 reads the register RG_5 or RG_6 according to the control signal SC. For example, when the control signal SC meets a preset state, the selection circuit SEL_6 reads the register RG_5. The selection circuit SEL_6 uses the output value O_5 stored in the register RG_5 as the temporary value V_3, and provides the temporary value V_3 to the subtractor SB_1. When the control signal SC does not meet a preset state, the selection circuit SEL_6 reads the register RG_6. The selection circuit SEL_6 uses the output value O_6 stored in the register RG_6 as the temporary value V_3, and provides the temporary value V_3 to the subtractor SB_1.

[0084] The comb filter 332 includes a subtractor SB_2, selection circuits SEL_7, SEL_8, registers RG_7 and RG_8. The subtractor SB_2 subtracts the calculated value C_3 from the stored value V_4 to generate a calculated value C_4. The selection circuit SEL_7 uses the calculated value C_3 as an output value O_7 or O_8 according to the control signal SC. For example, when the control signal SC meets a preset state (such as a low level), the selection circuit SEL_7 uses the calculated value C_3 as an output value O_7. When the control signal SC does not meet the preset state, the selection circuit SEL_7 uses the calculated value C_3 as an output value O_8.

[0085] The registers RG_7 and RG_8 are coupled to the selection circuit SEL_7. When the selection circuit SEL_7 uses the calculated value C_3 as the output value O_7, the register RG_7 stores the output value O_7. When the selection circuit SEL_7 uses the calculated value C_3 as the output value O_8, the register RG_8 stores the output value O_8.

[0086] The selection circuit SEL_8 is coupled to the registers RG_7 and RG_8. The selection circuit SEL_8 reads the register RG_7 or RG_8 according to the control signal SC. For example, when the control signal SC meets a preset state, the selection circuit SEL_8 reads the register RG_7. The selection circuit SEL_8 uses the output value O_7 stored in the register RG_7 as the temporary value V_4, and provides the temporary value V_4 to the subtractor SB_2. When the control signal SC does not meet a preset state, the selection circuit SEL_8 reads the register RG_8. The selection circuit SEL_8 uses the output value O_8 stored in the register RG_8 as the temporary value V_4, and provides the temporary value V_4 to the subtractor SB_2.

[0087] In one possible embodiment, the digital filter circuit 124 directly uses the calculated value C_4 as the output data SODA. In another possible embodiment, the digital filter circuit 124 further includes a gain adjustment circuit 340. The gain adjustment circuit 340 may shift the calculated value C_4 to generate a shift data GADA. In one possible embodiment, the gain adjustment circuit 340 may use the higher 24 bits of the calculated value C_4 as the shift data GADA. In this example, the shift data GADA is used as the output data SODA.

[0088] In some embodiments, the input data SIDA is 1-bit data, and the calculated values ​​C_1-C_4 are multi-bit data, such as 32 bits. In addition, the number of bits of the displacement data GADA (eg, 24 bits) may be less than the number of bits of the calculated values ​​C_1-C_4.

[0089] Figure 4 This is a schematic diagram of the operation of the analog-to-digital conversion circuit of the present invention. Figure 1 During the operation period 410, the receiving circuit 110 uses the analog signal AIN_1 of the channel 111 as the output signal SO. Therefore, the digital filter circuit 124 performs a sampling operation and a conversion operation on the input data SIDA.

[0090] In a stable period 411, the digital filter circuit 124 samples the input data SIDA multiple times to generate multiple first sampling results, and stores the first sampling results in a first temporary storage circuit. The present invention does not limit the number of sampling times of the digital filter circuit 124. In a possible embodiment, the digital filter circuit 124 performs 24 sampling operations on the input data SIDA. In a conversion period 412, the digital filter circuit 124 converts the first sampling results to generate output data SODA.

[0091] During the operation period 420, the receiving circuit 110 uses the analog signal AIN_2 of the channel 112 as the output signal SO. Therefore, the digital filter circuit 124 performs a sampling operation and a conversion operation on the input data SIDA. During a stable period 421, the digital filter circuit 124 samples the input data SIDA multiple times to generate multiple second sampling results, and stores the second sampling results in a second temporary storage circuit. In a possible embodiment, the digital filter circuit 124 retains the first sampling result stored in the first temporary storage circuit. During a conversion period 422, the digital filter circuit 124 converts the second sampling result to generate the output data SODA.

[0092] During the operation period 430, the receiving circuit 110 uses the analog signal AIN_1 of the channel 111 as the output signal SO. Since the digital filter circuit 124 retains the sampling result of the previous analog signal AIN_1, the digital filter circuit 124 performs a fewer number of sampling operations. For example, during the operation period 430, the digital filter circuit 124 performs 8 sampling operations. Since the number of sampling operations is reduced, the digital filter circuit 124 quickly provides the output data SODA.

[0093] During operation period 440, the receiving circuit 110 again uses the analog signal AIN_2 of the channel 112 as the output signal SO. Since the digital filter circuit 124 retains the sampling result of the previous analog signal AIN_2, the digital filter circuit 124 only performs a smaller number of sampling operations. Therefore, the power consumption of the digital filter circuit 124 is reduced. Furthermore, since the digital filter circuit 124 quickly provides the output data SODA, the performance of the digital filter circuit 124 can be increased.

[0094] During the operation period 450, the receiving circuit 110 uses the analog signal AIN_1 of the channel 111 as the output signal SO. During the operation period 450, the number of sampling operations performed by the digital filter circuit 124 is less than the number of sampling operations performed during the operation period 410. Therefore, the digital filter circuit 124 can quickly provide the output data SODA. Similarly, during the operation period 460, the receiving circuit 110 uses the analog signal AIN_2 of the channel 112 as the output signal SO. During the operation period 460, the number of sampling operations performed by the digital filter circuit 124 is less than the number of sampling operations performed during the operation period 420. Therefore, the digital filter circuit 124 can quickly provide the output data SODA.

[0095] Figure 5 The control method of the present invention is a flow chart of the control method of the present invention. The control method of the present invention is applicable to an analog-to-digital converter. The control method of the present invention can exist through a program. When the program is loaded and executed by a machine, the machine becomes an analog-to-digital converter or a digital filter circuit for implementing the present invention.

[0096] First, a first analog input and a second analog input are received (step S511). In one possible embodiment, the first and second analog signals are continuously and alternately used as output signals. The present invention does not limit the sources of the first and second analog inputs. In one possible embodiment, the first analog input is provided by a first sensing circuit. The first sensing circuit detects a physical characteristic (such as temperature, humidity) or an electrical characteristic (voltage, current, frequency), and uses the detection result as the first analog input. In another possible embodiment, the second analog input is provided by a second sensing circuit. The second sensing circuit detects a physical characteristic or an electrical characteristic, and uses the detection result as the second analog input. In some embodiments, the physical characteristic or electrical characteristic detected by the first sensing circuit may be the same as or different from the physical characteristic or electrical characteristic detected by the second sensing circuit.

[0097] Determine whether a control signal meets a preset state (step S512). When the control signal meets the preset state (such as a low level), use the first analog signal as an output signal (step S513). Then, convert the output signal to generate an input data (step S514). In a possible embodiment, step S514 converts the output signal from an analog format to a digital format.

[0098] Then, the input data is oversampled to generate a plurality of first sampling results (step S515). In one possible embodiment, the bit number of the output data is less than the bit number of one of the first sampling results. Then, the plurality of first sampling results are stored (step S516). In one possible embodiment, the first sampling result is stored in a first temporary storage circuit. Then, according to the first sampling result, an output data is generated (step S517), and then the process returns to step S512. In one possible embodiment, step S517 uses one of the plurality of first sampling results as the output data.

[0099] When the control signal does not meet a preset state, the second analog signal is used as an output signal (step S518). Then, the output signal is converted to generate an input data (step S519). In a possible embodiment, step S519 converts the output signal from an analog format to a digital format.

[0100] Then, the input data is oversampled to generate a plurality of second sampling results (step S520). In one possible embodiment, the number of bits of the output data is less than the number of bits of one of the second sampling results. Then, the plurality of second sampling results are stored (step S521). In one possible embodiment, the second sampling result is stored in a second temporary storage circuit. The first and second temporary storage circuits are independent of each other. Then, according to the second sampling result, an output data is generated (step S522), and then the process returns to step S512. In one possible embodiment, step S522 uses one of the plurality of second sampling results as the output data.

[0101] In some embodiments, when the second sampling result is stored in step 521, the first sampling result is retained in the first temporary storage circuit. Similarly, when the first sampling result is stored in step 516, the second sampling result is retained in the second temporary storage circuit.

[0102] It should be understood that when an element or layer is referred to as being "coupled" to another element or layer, it can be directly coupled or connected to the other element or layer, or there can be other elements or layers interposed therebetween. Conversely, if an element or layer is "connected" to another element or layer, there can be no other elements or layers interposed therebetween.

[0103] The control method of the present invention, or a specific form or part thereof, may exist in the form of a program. The program may be stored in a physical medium, such as a floppy disk, an optical disk, a hard disk, or any other machine-readable (such as computer-readable) storage medium, or a computer program product not limited to an external form, wherein when the program is loaded and executed by a machine, such as a computer, the machine becomes used to participate in the analog-to-digital conversion circuit and digital filtering circuit of the present invention. The program may also be transmitted through some transmission media, such as wires or cables, optical fibers, or any transmission mode, wherein when the program is received, loaded and executed by a machine, such as a computer, the machine becomes used to participate in the analog-to-digital conversion circuit and digital filtering circuit of the present invention. When implemented in a general-purpose processing unit, the program combines with the processing unit to provide a unique device that operates similarly to an application-specific logic circuit.

[0104] Unless otherwise defined, all words (including technical and scientific words) herein are generally understood by those skilled in the art to which the present invention belongs. In addition, unless expressly indicated, the definitions of words in general dictionaries should be interpreted as consistent with the meanings in articles in the relevant technical field, and should not be interpreted as ideal or overly formal. Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0105] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the definition of the claims.

Claims

1. An analog-to-digital conversion circuit, characterized in that: include: a receiving circuit, receiving a first analog input and a second analog input, and according to a control signal, using the first or second analog input as an output signal; as well as A delta-sigma analog-to-digital converter converts the output signal to generate output data, and includes: a differential amplifier for amplifying a difference between the output signal and a reference signal to generate an amplified signal; an integrator, accumulating the amplified signal to generate an integrated signal; a quantizer, quantizing the integrated signal to generate an input data; a digital-to-analog conversion circuit, converting the input data to generate the reference signal; and A digital filter circuit oversamples the input data according to the control signal to generate the output data.

2. The analog-to-digital conversion circuit according to claim 1, wherein: When the control signal meets a preset state: The receiving circuit uses the first analog input as the output signal; The digital filter circuit oversamples the input data to generate a plurality of first sampling results, and stores the plurality of first sampling results in a first temporary storage circuit; and The digital filter circuit generates the output data according to the plurality of first sampling results; When the control signal does not meet the preset state: The receiving circuit uses the second analog input as the output signal; The digital filter circuit oversamples the input data to generate a plurality of second sampling results, and stores the plurality of second sampling results in a second temporary storage circuit; and The digital filter circuit generates the output data according to the plurality of second sampling results.

3. The analog-to-digital conversion circuit according to claim 2, characterized in that: While the digital filter circuit generates the output data according to the first sampling results, the second temporary storage circuit still stores the second sampling results.

4. The analog-to-digital conversion circuit according to claim 2, characterized in that: The digital filter circuit includes: An integrator circuit, comprising a plurality of integrators, the plurality of integrators are connected in series, and each integrator temporarily stores the plurality of first sampling results and the plurality of second sampling results at the same time; A comb filter circuit, comprising a plurality of comb filters, the plurality of comb filters are connected in series, and each comb filter temporarily stores the plurality of first sampling results and the plurality of second sampling results at the same time; and A frequency reduction circuit is coupled between the integrator circuit and the comb filter circuit.

5. The analog-to-digital conversion circuit according to claim 2, characterized in that: The digital filter circuit includes: An integrator circuit comprising: a first integrator, comprising: a first adder for adding the input data and a first temporary storage value to generate a first calculation value; a first selection circuit, which uses the first calculated value as a first output value or a second output value according to the control signal; a first register storing the first output value; a second register for storing the second output value; a second selection circuit, which selects the first output value stored in the first register or the second output value stored in the second register as the first temporary storage value according to the control signal; a second integrator, connected in series with the first integrator, and comprising; a second adder for adding the first calculated value and a second temporary value to generate a second calculated value; a third selection circuit, which uses the second calculated value as a third output value or a fourth output value according to the control signal; a third register for storing the third output value; a fourth register for storing the fourth output value; a fourth selection circuit, which selects the third output value stored in the third register or the fourth output value stored in the fourth register as the second temporary value according to the control signal; a down-conversion circuit for down-conversion-sampling the second calculated value to generate a processed value; A comb filter circuit comprising: A first comb filter, comprising: a first subtractor, subtracting the processed value from a third temporary value to generate a third calculated value; a fifth selection circuit, which uses the processed value as a fifth output value or a sixth output value according to the control signal; a fifth register for storing the fifth output value; a sixth register for storing the sixth output value; a sixth selection circuit, which selects the fifth output value stored in the fifth register or the sixth output value stored in the sixth register as the third temporary value according to the control signal; a second comb filter, comprising: a fourth subtractor, subtracting the third calculated value from a fourth temporary value to generate a fourth calculated value; a seventh selection circuit, which uses the third calculated value as a seventh output value or an eighth output value according to the control signal; a seventh register for storing the seventh output value; an eighth register for storing the eighth output value; An eighth selection circuit uses the seventh output value stored in the seventh register or the eighth output value stored in the eighth register as the fourth temporary value according to the control signal.

6. The analog-to-digital conversion circuit according to claim 1, wherein: Also includes: A first channel receives the first analog input generated by a first sensing circuit and provides the first analog input to the receiving circuit; A second channel receives the second analog input generated by a second sensing circuit and provides the second analog input to the receiving circuit.

7. A digital filter circuit, characterized in that: Oversampling an input data to generate an output data, comprising: An integrator circuit comprising: a first integrator, comprising: a first adder for adding the input data and a first temporary storage value to generate a first calculation value; a first selection circuit, which uses the first calculated value as a first output value or a second output value according to a control signal; a first register storing the first output value; a second register for storing the second output value; a second selection circuit, which selects the first output value stored in the first register or the second output value stored in the second register as the first temporary storage value according to the control signal; a second integrator, connected in series with the first integrator, and comprising; a second adder for adding the first calculated value and a second temporary value to generate a second calculated value; a third selection circuit, which uses the second calculated value as a third output value or a fourth output value according to the control signal; a third register for storing the third output value; a fourth register for storing the fourth output value; a fourth selection circuit, which selects the third output value stored in the third register or the fourth output value stored in the fourth register as the second temporary value according to the control signal; a down-conversion circuit for down-conversion-sampling the second calculated value to generate a processed value; A comb filter circuit comprising: A first comb filter, comprising: a first subtractor, subtracting the processed value from a third temporary value to generate a third calculated value; a fifth selection circuit, which uses the processed value as a fifth output value or a sixth output value according to the control signal; a fifth register for storing the fifth output value; a sixth register for storing the sixth output value; a sixth selection circuit, which selects the fifth output value stored in the fifth register or the sixth output value stored in the sixth register as the third temporary value according to the control signal; a second comb filter, comprising: a fourth subtractor, subtracting the third calculated value from a fourth temporary value to generate a fourth calculated value; a seventh selection circuit, which uses the processed value as a seventh output value or an eighth output value according to the control signal; a seventh register for storing the seventh output value; an eighth register for storing the eighth output value; An eighth selection circuit uses the seventh output value stored in the seventh register or the eighth output value stored in the eighth register as the fourth temporary value according to the control signal.

8. The digital filter circuit according to claim 7, characterized in that: When the control signal meets a preset state: The first selection circuit uses the first calculated value as the first output value; The second selection circuit uses the first output value stored in the first register as the first temporary value; The third selection circuit uses the second calculated value as the third output value; The fourth selection circuit uses the third output value stored in the third register as the second temporary value; The fifth selection circuit uses the processed value as the fifth output value; The sixth selection circuit uses the fifth output value stored in the fifth register as the third temporary value; The seventh selection circuit uses the third calculated value as the seventh output value; The eighth selection circuit uses the seventh output value stored in the seventh register as the fourth temporary value.

9. The digital filter circuit according to claim 8, characterized in that: When the control signal does not meet the preset state: The first selection circuit uses the first calculated value as the second output value; The second selection circuit uses the second output value stored in the second register as the first temporary value; The third selection circuit uses the second calculated value as the fourth output value; The fourth selection circuit uses the fourth output value stored in the fourth register as the second temporary value; The fifth selection circuit uses the processed value as the sixth output value; The sixth selection circuit uses the sixth output value stored in the sixth register as the third temporary value; The seventh selection circuit uses the third calculated value as the eighth output value; The eighth selection circuit uses the eighth output value stored in the eighth register as the fourth temporary value.

10. A control method, characterized in that: Suitable for an analog-to-digital converter, and comprising: Receiving a first analog input generated by a first sensing circuit; receiving a second analog input generated by a second sensing circuit; According to a control signal, the first or second analog signal is used as an output signal; Converting the output signal to generate input data, wherein the output signal is in analog format and the output data is in digital format; When the first analog signal is used as the output signal: Oversampling the input data to generate a plurality of first sampling results; Storing the plurality of first sampling results in a first temporary storage circuit; Generate the output data according to the plurality of first sampling results; When the second analog signal is used as the output signal: Oversampling the input data to generate a plurality of second sampling results; Storing the plurality of second sampling results in a second temporary storage circuit; The output data is generated according to the plurality of second sampling results.

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