Analog-to-digital converter fault diagnosis method and device

Abstract

The invention relates to the technical field of circuit detection, and provides an analog-to-digital converter fault diagnosis method and device. The method comprises the following steps: acquiring a first binary numerical value corresponding to a first differential acquisition channel through an analog-to-digital converter; acquiring a second binary numerical value corresponding to the second differential acquisition channel through an analog-to-digital converter; judging whether the first binary numerical value and the second binary numerical value are complementary or not; if yes, determining that the analog-to-digital converter has no clamping fault; and if not, determining that the analog-to-digital converter has a clamping fault. According to the invention, the corresponding signal values of the first differential acquisition channel and the second differential acquisition channel which are connected with the preset power supply in opposite modes are respectively acquired, whether the signal values are complementary is judged, if the signal values are complementary, the current analog-to-digital converter has no clamping fault, and if the signal values are not complementary, the current analog-to-digital converter has the clamping fault. According to the method, efficient clamping fault diagnosis is completed through clear and simple judgment, an additional standard analog-to-digital converter is not needed, the cost is low, and implementation is easy.

Description

Technical Field

[0001] The present application relates to the field of circuit detection technology, and in particular to a method and device for diagnosing faults of analog-to-digital converters. Background Art

[0002] ADC (Analog-to-Digital Converter) is an electronic conversion element that converts analog signals into digital signals for output. The basic principle is to sample the input analog signal at a specified time interval and compare it with a series of standard digital signals. The digital signals gradually converge until the two signals are equal, and finally a binary number representing the signal is obtained.

[0003] After receiving the analog signal, the ADC has to go through a series of complex signal processing. Due to the complexity of signal processing, a bit stuck fault may occur inside the ADC, that is, regardless of the value of the input analog signal, the value of the bit with the stuck fault in the output binary number remains unchanged. The detection of this bit stuck fault usually requires another normal standard ADC as a control group, and the same analog signal is input into the ADC to be tested and the standard ADC respectively. The output results of the ADC to be tested and the standard ADC are compared to see if they are consistent. Multiple control tests are performed to complete the bit stuck diagnosis of the ADC to be tested. This diagnostic method requires the configuration of a standard ADC, and the detection is time-consuming, making it difficult to quickly complete the stuck diagnosis.

[0004] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve. Summary of the invention

[0005] In view of this, an embodiment of the present application provides an analog-to-digital converter fault diagnosis method and device to solve the problems of high detection cost, cumbersome and time-consuming in the prior art.

[0006] In a first aspect of an embodiment of the present application, a method for diagnosing a fault of an analog-to-digital converter is provided, which is applied to a controller, wherein the controller is connected to an output end of the analog-to-digital converter, a first pin of a first differential acquisition channel of the analog-to-digital converter is connected to a positive electrode of a preset power supply, a second pin of the first differential acquisition channel is connected to a negative electrode of the preset power supply, a first pin of a second differential acquisition channel of the analog-to-digital converter is connected to the negative electrode, and a second pin of the second differential acquisition channel is connected to the positive electrode, the method comprising:

[0007] Acquire a first binary value corresponding to the first differential acquisition channel through an analog-to-digital converter;

[0008] Acquire a second binary value corresponding to the second differential acquisition channel through an analog-to-digital converter;

[0009] Determining whether the first binary value and the second binary value are complementary;

[0010] If so, make sure the analog-to-digital converter has no stuck position fault;

[0011] If not, determine that the analog-to-digital converter has a stuck fault.

[0012] In a second aspect of an embodiment of the present application, a fault diagnosis device for an analog-to-digital converter is provided, which is applied to a controller, wherein the controller is connected to the output end of the analog-to-digital converter, a first pin of a first differential acquisition channel of the analog-to-digital converter is connected to the positive electrode of a preset power supply, a second pin of the first differential acquisition channel is connected to the negative electrode of the preset power supply, a first pin of a second differential acquisition channel of the analog-to-digital converter is connected to the negative electrode, and a second pin of the second differential acquisition channel is connected to the positive electrode, and the device comprises:

[0013] An acquisition module, used to acquire a first binary value corresponding to the first differential acquisition channel through an analog-to-digital converter, and also used to acquire a second binary value corresponding to the second differential acquisition channel through the analog-to-digital converter;

[0014] The judgment module is used to judge whether the first binary value and the second binary value are complementary. If so, it is determined that the analog-to-digital converter has no stuck position fault; if not, it is determined that the analog-to-digital converter has a stuck position fault.

[0015] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the computer program.

[0016] According to a fourth aspect of an embodiment of the present application, a readable storage medium is provided, which stores a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0017] Compared with the prior art, the beneficial effects of the embodiments of the present application include at least the following: the embodiments of the present application respectively collect corresponding signal values ​​from the first differential acquisition channel and the second differential acquisition channel that are connected to the preset power supply in opposite ways, and determine whether the collected first binary value and the second binary value are complementary. If they are complementary, the current analog-to-digital converter does not have a stuck position fault; if they are not complementary, the current analog-to-digital converter has a stuck position fault. This method completes efficient stuck position fault diagnosis with clear and concise judgments, does not require an additional standard analog-to-digital converter, and can complete self-test of the stuck position fault with only the analog-to-digital converter to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 It is a schematic diagram of an application scenario of an embodiment of the present application;

[0020] Figure 2 It is a flowchart of a method for diagnosing faults of an analog-to-digital converter provided in an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of the internal structure of an analog-to-digital converter provided in an embodiment of the present application;

[0022] Figure 4 It is a structural schematic diagram of an analog-to-digital converter fault diagnosis device provided in an embodiment of the present application;

[0023] Figure 5 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0025] A method and device for diagnosing faults of an analog-to-digital converter according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 1 is a schematic diagram of an application scenario of an embodiment of the present application. The application scenario includes a controller 101, an analog-to-digital converter 102, and a preset power supply 103. The controller 101 is connected to the output end of the analog-to-digital converter 102. The first pin p11 of the first differential acquisition channel of the analog-to-digital converter 102 is connected to the positive electrode V+ of the preset power supply 103. The second pin p12 of the first differential acquisition channel is connected to the negative electrode V- of the preset power supply 103. The first pin p21 of the second differential acquisition channel of the analog-to-digital converter 102 is connected to the negative electrode V-, and the second pin P22 of the second differential acquisition channel is connected to the positive electrode V+.

[0027] The preset power supply 103 is used to provide a stable voltage, so that there is a stable voltage difference between the positive electrode V+ and the negative electrode V-, which can be collected by the differential acquisition channel of the analog-to-digital converter 102. The analog-to-digital converter 102 includes a plurality of differential acquisition channels, each of which includes two pins, which are used to connect two voltage bits respectively. The analog-to-digital converter 102 will obtain the voltage difference between the two voltage bits through the differential acquisition channel and convert the voltage difference from an analog signal to a digital signal and output it. The controller 101 is connected to the output end of the analog-to-digital converter 102 to receive the corresponding digital signal. The controller 101 can be implemented by an MCU (Microcontroller Unit), a CPU (Central Processing Unit, CPU), a CPLD (Complex Programmable Logic Device), an FPGA (Field-Programmable Gate Array) or other programmable logic devices. When the controller 101 is an MCU, it can be connected to the analog-to-digital converter through an SPI (Serial Peripheral interface, serial peripheral device interface).

[0028] Figure 2 It is a flow chart of an analog-to-digital converter fault diagnosis method provided in an embodiment of the present application. Figure 2 The fault diagnosis method of analog-to-digital converter can be Figure 1 The controller is executed. Figure 2 As shown, the analog-to-digital converter fault diagnosis method includes:

[0029] S201: Acquire a first binary value corresponding to a first differential acquisition channel through an analog-to-digital converter;

[0030] S202: Acquire a second binary value corresponding to a second differential acquisition channel through an analog-to-digital converter;

[0031] S203: Determine whether the first binary value and the second binary value are complementary;

[0032] S204: If yes, determine that the analog-to-digital converter has no stuck position fault;

[0033] S205: If not, determine that a stuck fault occurs in the analog-to-digital converter.

[0034] It is understandable that the voltage difference collected by the first differential acquisition channel and the second differential acquisition channel corresponds to the same preset power supply, but due to the different positive and negative poles of the connected preset power supply, the voltage difference collected by the first differential acquisition channel and the second differential acquisition channel has the same value and opposite sign. For the analog-to-digital converter, when the analog signal has the same value and opposite sign, the binary value of the converted digital signal should be complementary, that is, the first binary value and the second binary value should be complementary. This complementary principle is used as the basis for judging the stuck position fault. If it is complementary, there is no stuck position fault. If it is not complementary, a stuck position fault occurs. This complementary judgment requires that both 0 and 1 appear on each code position, thereby ensuring that each code value of each code position on the analog-to-digital converter is detected, thereby achieving a comprehensive stuck position fault inspection in a quick and concise manner.

[0035] Typically, a 0R resistor may be added in series when the positive or negative pole of a preset power source is connected to the first pin or the second pin. The position of the 0R resistor facilitates replacement of an ammeter to measure a specific current, serving as a detection interface for the wiring circuit.

[0036] It is known that the binary value output by the analog-to-digital converter is a preset number of code values ​​arranged according to the code bits. Here, the preset number is the number of code bits of the analog-to-digital converter. The number of code bits is also the internal bit position, which is a fixed parameter of the analog-to-digital converter. The common number of code bits is 8, 16, 24, 32, etc. It can be understood that for the judgment of whether the first binary value and the second binary value are complementary, it is usually judged whether the two code values ​​on each same code bit are complementary in the order of the code bit arrangement. At this time, not only the judgment result of whether the first binary value and the second binary value are complementary can be obtained, but also the specific position of the non-complementary fault code bit can be further obtained. Therefore, the first binary value and the second binary value both include the preset number of code values ​​arranged according to the code bits. The process of judging whether the first binary value and the second binary value are complementary includes:

[0037] Perform complementary judgment on each code value in the first binary value and the code value in the second binary value corresponding to the same code position one by one;

[0038] If the code values ​​of the first binary value and the code values ​​of the second binary value of all code bits are complementary, then it is determined that the first binary value and the second binary value are complementary;

[0039] If there is any code position where the code value of the first binary value and the code value of the second binary value are not complementary, it is determined that the first binary value and the second binary value are not complementary, and the code position corresponding to the non-complementarity of the code value of the first binary value and the code value of the second binary value is a fault code position.

[0040] Taking a 24-bit analog-to-digital converter as an example, its internal conversion process is as follows: Figure 3 As shown, VIN0-VINCOM are the input pins of each acquisition channel, and the internal circuit for data processing mainly includes PVD (Precision Voltage Divider), multiplexer MUX, 24BIT Σ-Δ modulator, digital filter Digital Filter, serial interface Serial Interface, etc.

[0041] Assuming that the reference voltage of the reference power supply inside the analog-to-digital converter is 2.5V, the reference power supply is used as the preset power supply in this embodiment, and the embodiment of this method is executed. At this time, the collection voltage of the first differential collection channel is +2.5V, and the collection voltage of the second differential collection channel is -2.5V.

[0042] For the differential acquisition channel, the input signal will be converted into a binary number by the analog-to-digital converter. The specific value of the binary number can be calculated according to the quantization formula, which includes:

[0043] CODE=2 N-1 (VIN×0.1÷VREF+1);

[0044] Among them, CODE is the calculation result, VIN is the input parameter, N is the number of code bits of the analog-to-digital converter, and VREF is the voltage of the reference power supply.

[0045] It can be understood that the conversion principle of the analog-to-digital converter is the quantization formula. Therefore, based on the quantization formula, the theoretical value of the first binary value corresponding to the first differential acquisition channel obtained by the analog-to-digital converter can be calculated, specifically:

[0046] CODE1=2 23 (2.5×0.1÷2.5+1)=9227468,

[0047] At this time, CODE1 is the theoretical value of the first binary value in decimal. Converting it into binary obtains the first binary value CODE1-B=1000 1100 1100 1100 1100 1100.

[0048] Similarly, based on the quantization formula, the theoretical value of the second binary value corresponding to the second differential acquisition channel obtained by the analog-to-digital converter can be calculated, specifically:

[0049] CODE2=2 23 (-2.5×0.1÷2.5+1)=7549747,

[0050] At this time, CODE2 is the theoretical value of the second binary value in decimal. Converting it into binary obtains the second binary value CODE2-B=0111 0011 0011 0011 0011 0011.

[0051] These two theoretical values ​​should be complementary, as shown below. Obviously, the code values ​​of CODE1-B and CODE2-B at any same code position are complementary:

[0052] CODE1-B=1000 1100 1100 1100 1100 1100,

[0053] CODE2-B=0111 0011 0011 0011 0011 0011.

[0054] Furthermore, based on the above theory, the actual first binary value DATA1-B and the second binary value DATA2-B are obtained, and the code value of each code position of the first binary value and the code value of the corresponding unified code position are judged complementary one by one, so as to determine whether there is a stuck position fault and determine the fault code position. Assume that the first binary value DATA1-B and the second binary value DATA2-B are as follows:

[0055] DATA1-B=1000 1100 1100 1100 1100 1100,

[0056] DATA2-B=0111 0010 0011 0011 0011 0011.

[0057] When comparing the code bits one by one, it can be found that the first binary value and the second binary value of the eighth code bit from left to right are not complementary, and this code bit is a fault code bit.

[0058] In fact, the determination of the stuck position fault in this embodiment does not require understanding of the quantitative formula, obtaining the voltage of the reference power supply in the analog-to-digital converter, or using the voltage of the preset power supply as calculation data. It is only necessary to determine that the positive and negative voltages of the preset power supply are both within the acquisition range of the analog-to-digital converter to be tested. The actual calculation and determination only use the first binary number system and the second binary value obtained as the calculation objects, and the calculation strategy is complementary determination. The determination of the entire method is extremely simple and efficient.

[0059] Furthermore, it is known that in order to reduce the cost of using the device, the preset power supply in this embodiment can reuse the original reference power supply in the analog-to-digital converter. At this time, the voltage of the reference power supply itself is known as the fixed parameter of the analog-to-digital converter, and it can be further determined whether the first binary value or the second binary value of the voltage corresponding to the reference power supply collected through the first differential acquisition channel or the second differential acquisition channel is the same as the fixed parameter of the reference power supply. Specifically, the preset power supply is the reference power supply of the analog-to-digital converter; the method also includes:

[0060] When the analog-to-digital converter has no stuck position fault, a first difference between the first binary value and the first standard value is calculated, and a second difference between the second binary value and the second standard value is calculated;

[0061] Determine whether the absolute value of the first difference is greater than the error threshold or the absolute value of the second difference is greater than the error threshold;

[0062] If so, it is determined that the analog-to-digital converter has an accuracy error fault.

[0063] It can be understood that the first standard value and the second standard value are both theoretical values ​​corresponding to the first differential acquisition channel and the second differential acquisition channel when the analog-to-digital converter is working normally. The theoretical values ​​can be determined by the quantization formula of the analog-to-digital converter. Specifically, the first standard value is calculated by the quantization formula of the analog-to-digital converter with the voltage of the reference power supply as the input parameter; the second standard value is calculated by the quantization formula with the opposite of the voltage of the reference power supply as the input parameter; the quantization formula is determined by the number of code bits of the analog-to-digital converter and the voltage of the reference power supply.

[0064] Furthermore, the quantitative formula is as follows:

[0065] CODE=2 N-1 (VIN×0.1÷VREF+1);

[0066] Among them, CODE is the calculation result, VIN is the input parameter, N is the number of code bits of the analog-to-digital converter, and VREF is the voltage of the reference power supply.

[0067] It can be understood that the first binary value and the second binary value are both binary, and the first standard value and the second standard value differ in the calculation details according to the theoretical calculation. For example, the result obtained when calculating according to the above quantization formula is decimal. At this time, in order to ensure that the binary number system corresponding to the differential acquisition channel and the standard value can be normally calculated, these numbers need to be unified to the same system, such as unified to binary or unified to decimal, which is not limited here. Specifically, before calculating the first difference between the first binary value and the first standard value and calculating the second difference between the second binary value and the second standard value, it also includes:

[0068] The first binary value, the first standard value, the second binary value and the second standard value are unified into the same base.

[0069] It can be understood that, in fact, according to the quantization formula, when calculating the first standard value and the second standard value, the input parameter and the voltage of the reference power supply are reduced and eliminated, and the calculation result is the product of 2 to the N-1th power and the constant term, and the constant term corresponding to the first standard value is 1.1, and the constant term of the second standard value is 0.9. In other words, the calculation of the first standard value and the second standard value is not interfered by the reference power supply, and no matter what the actual voltage of the current reference power supply is, the first standard value and the second standard value remain unchanged. Therefore, taking the first standard value and the second standard value as the standard, if the first binary value collected by the actual differential acquisition channel is not equal to the first standard value, or the second binary value is not equal to the second standard value, it is considered that there is an error in the analog-to-digital converter, but the accuracy error of the analog-to-digital converter is objectively present, and further judge whether the actual error is too large, that is, judge whether the absolute value of the first difference between the first binary value collected by the actual differential acquisition channel and the first standard value, and the absolute value of the second difference between the second binary value and the second standard value are greater than the error threshold. If so, it is considered that the current analog-to-digital converter has a large accuracy error, and it is determined that there is an accuracy error fault.

[0070] It is understandable that, in order to improve the use efficiency of the analog-to-digital converter, an analog-to-digital converter usually includes multiple acquisition channels, and in this embodiment, any two of them can be selected as the first differential acquisition channel and the second differential acquisition channel to detect the stuck fault. On this basis, corresponding acquisition can also be performed on other acquisition channels at the same time, or they can be replaced by other differential acquisition channels when the first differential acquisition channel and the second differential acquisition channel may fail. Specifically, the remaining differential acquisition channels of the analog-to-digital converter are first-class channels or second-class channels, wherein the first pins of the first-class channels are all connected to the positive electrode, the second pins of the first-class channels are all connected to the negative electrode, the first pins of the second-class channels are all connected to the negative electrode, and the second pins of the second-class channels are all connected to the positive electrode. The method also includes:

[0071] Obtain the binary values ​​corresponding to the remaining differential acquisition channels through the analog-to-digital converter;

[0072] Determining whether a channel detection condition is satisfied based on the first binary value, the second binary value, and all the binary values, the channel detection condition comprising: the binary values ​​of all first-category channels are the same as the first binary value and the binary values ​​of all second-category channels are the same as the second binary value;

[0073] If not, it is determined that a channel failure occurs in the analog-to-digital converter.

[0074] It can be understood that for the same analog-to-digital converter, when the voltage differences collected by different differential acquisition channels are the same, the analog-to-digital converter should theoretically output the same binary value, so the binary value of the first type of channel should be the same as the first binary value, and the binary value of the second type of channel should be the same as the second binary value. If there are different situations, it can be considered that the analog-to-digital converter has a channel failure, and the location of the failure can be further located based on the difference in specific values.

[0075] The method of the embodiment of the present application collects corresponding signal values ​​from the first differential acquisition channel and the second differential acquisition channel that are connected to a preset power supply in opposite ways, respectively, and determines whether the collected first binary value and the second binary value are complementary. If they are complementary, the current analog-to-digital converter does not have a stuck position fault; if they are not complementary, the current analog-to-digital converter has a stuck position fault. The method completes efficient stuck position fault diagnosis with clear and concise judgments, does not require an additional standard analog-to-digital converter, and can complete the self-test of the stuck position fault with only the analog-to-digital converter to be tested.

[0076] All the above optional technical solutions can be combined in any way to form optional embodiments of the present application, and will not be described in detail here. It should be understood that the size of the sequence number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0077] The following is an embodiment of the device of the present application, which can be used to execute the embodiment of the method of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the method of the present application.

[0078] Figure 4 1 is a schematic diagram of an analog-to-digital converter fault diagnosis device provided by an embodiment of the present application. The device is applied to a controller, the controller is connected to the output end of the analog-to-digital converter, the first pin of the first differential acquisition channel of the analog-to-digital converter is connected to the positive electrode of the preset power supply, the second pin of the first differential acquisition channel is connected to the negative electrode of the preset power supply, the first pin of the second differential acquisition channel of the analog-to-digital converter is connected to the negative electrode, and the second pin of the second differential acquisition channel is connected to the positive electrode, such as Figure 4 As shown, the analog-to-digital converter fault diagnosis device includes:

[0079] The acquisition module 401 is used to acquire a first binary value corresponding to the first differential acquisition channel through an analog-to-digital converter, and is also used to acquire a second binary value corresponding to the second differential acquisition channel through the analog-to-digital converter;

[0080] The judgment module 402 is used to judge whether the first binary value and the second binary value are complementary. If so, it is determined that the analog-to-digital converter has no stuck position fault. If not, it is determined that the analog-to-digital converter has a stuck position fault.

[0081] The device of the embodiment of the present application collects corresponding signal values ​​from the first differential acquisition channel and the second differential acquisition channel that are connected to a preset power supply in opposite ways, respectively, and determines whether the collected first binary value and the second binary value are complementary. If they are complementary, the current analog-to-digital converter does not have a stuck position fault; if they are not complementary, the current analog-to-digital converter has a stuck position fault. This method completes efficient stuck position fault diagnosis with clear and concise judgments, does not require an additional standard analog-to-digital converter, and can complete self-test of the stuck position fault with only the analog-to-digital converter to be tested.

[0082] In an exemplary embodiment, the first binary value and the second binary value both include a preset number of code values ​​arranged according to code positions, and the process of the determination module 402 determining whether the first binary value and the second binary value are complementary includes:

[0083] Perform complementary judgment on each code value in the first binary value and the code value in the second binary value corresponding to the same code position one by one;

[0084] If the code values ​​of the first binary value and the code values ​​of the second binary value of all code bits are complementary, then it is determined that the first binary value and the second binary value are complementary;

[0085] If there is any code position where the code value of the first binary value and the code value of the second binary value are not complementary, it is determined that the first binary value and the second binary value are not complementary, and the code position corresponding to the non-complementarity of the code value of the first binary value and the code value of the second binary value is a fault code position.

[0086] In an exemplary embodiment, the preset power supply is a reference power supply of the analog-to-digital converter; the determination module 402 is further configured to:

[0087] When the analog-to-digital converter has no stuck position fault, a first difference between the first binary value and the first standard value is calculated, and a second difference between the second binary value and the second standard value is calculated;

[0088] Determine whether the absolute value of the first difference is greater than the error threshold or the absolute value of the second difference is greater than the error threshold;

[0089] If so, it is determined that the analog-to-digital converter has an accuracy error fault.

[0090] In an exemplary embodiment, the first standard value is calculated by a quantization formula of an analog-to-digital converter using a voltage of a reference power supply as an input parameter;

[0091] The second standard value is calculated by a quantitative formula using the inverse of the voltage of the reference power source as an input parameter;

[0092] The quantization formula is determined by the number of code bits of the analog-to-digital converter and the voltage of the reference power supply.

[0093] In an exemplary embodiment, the quantization formula is specifically:

[0094] CODE=2 N-1 (VIN×0.1÷VREF+1);

[0095] Among them, CODE is the calculation result, VIN is the input parameter, N is the number of code bits of the analog-to-digital converter, and VREF is the voltage of the reference power supply.

[0096] In an exemplary embodiment, before the determination module 402 calculates the first difference between the first binary value and the first standard value and calculates the second difference between the second binary value and the second standard value, it is further configured to:

[0097] The first binary value, the first standard value, the second binary value and the second standard value are unified into the same base.

[0098] In an exemplary embodiment, the remaining differential acquisition channels of the analog-to-digital converter are first-category channels or second-category channels, wherein the first pins of the first-category channels are all connected to the positive electrode, the second pins of the first-category channels are all connected to the negative electrode, the first pins of the second-category channels are all connected to the negative electrode, and the second pins of the second-category channels are all connected to the positive electrode;

[0099] The acquisition module 401 is also used to acquire binary values ​​corresponding to the remaining differential acquisition channels through an analog-to-digital converter;

[0100] The judgment module 402 is also used to judge whether the channel detection condition is met based on the first binary value, the second binary value and all the binary values. The channel detection condition includes: the binary values ​​of all first-category channels are the same as the first binary value and the binary values ​​of all second-category channels are the same as the second binary value. If not, it is determined that a channel failure occurs in the analog-to-digital converter.

[0101] Figure 5 Schematic diagram of an electronic device 5 provided in an embodiment of the present application. Figure 5 As shown, the electronic device 5 of this embodiment includes: a processor 501, a memory 502, and a computer program 503 stored in the memory 502 and executable on the processor 501. When the processor 501 executes the computer program 503, the steps in the above-mentioned method embodiments are implemented. Alternatively, when the processor 501 executes the computer program 503, the functions of the modules / units in the above-mentioned device embodiments are implemented.

[0102] The electronic device 5 may be a desktop computer, a notebook, a PDA, a cloud server, or other electronic device. The electronic device 5 may include, but is not limited to, a processor 501 and a memory 502. Those skilled in the art will appreciate that Figure 5 The electronic device 5 is merely an example and does not limit the electronic device 5 , and may include more or less components than those shown in the figure, or different components.

[0103] The processor 501 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0104] The memory 502 may be an internal storage unit of the electronic device 5, for example, a hard disk or memory of the electronic device 5. The memory 502 may also be an external storage device of the electronic device 5, for example, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 5. The memory 502 may also include both an internal storage unit of the electronic device 5 and an external storage device. The memory 502 is used to store computer programs and other programs and data required by the electronic device.

[0105] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0106] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium, such as a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. The computer program may include computer program code, which may be in source code form, object code form, executable file or some intermediate form. The readable storage medium may include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc.

[0107] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for diagnosing faults of an analog-to-digital converter, characterized in that: Applied to a controller, the controller is connected to the output end of an analog-to-digital converter, a first pin of a first differential acquisition channel of the analog-to-digital converter is connected to a positive electrode of a preset power supply, a second pin of the first differential acquisition channel is connected to a negative electrode of the preset power supply, a first pin of a second differential acquisition channel of the analog-to-digital converter is connected to the negative electrode, and a second pin of the second differential acquisition channel is connected to the positive electrode, the method comprising: Acquire a first binary value corresponding to the first differential acquisition channel through the analog-to-digital converter; Acquire a second binary value corresponding to the second differential acquisition channel through the analog-to-digital converter; determining whether the first binary value and the second binary value are complementary; If yes, determine that the analog-to-digital converter has no stuck position fault; If not, it is determined that a stuck fault occurs in the analog-to-digital converter.

2. The method for diagnosing faults of an analog-to-digital converter according to claim 1, characterized in that: The first binary value and the second binary value both include a preset number of code values ​​arranged according to code positions, and the process of determining whether the first binary value and the second binary value are complementary includes: Performing complementary judgment on each code value in the first binary value and the code value in the second binary value corresponding to the same code position one by one; If the code values ​​of the first binary value and the code values ​​of the second binary value of all code bits are complementary, then determining that the first binary value and the second binary value are complementary; If there is any code position where the code value of the first binary value and the code value of the second binary value are not complementary, it is determined that the first binary value and the second binary value are not complementary, and the code position corresponding to the non-complementary code value of the first binary value and the code value of the second binary value is a fault code position.

3. The method for diagnosing faults of an analog-to-digital converter according to claim 1, characterized in that: The preset power supply is a reference power supply of the analog-to-digital converter; the method further includes: When the analog-to-digital converter has no stuck position fault, calculating a first difference between the first binary value and a first standard value, and calculating a second difference between the second binary value and a second standard value; Determine whether the absolute value of the first difference is greater than an error threshold or the absolute value of the second difference is greater than the error threshold; If so, it is determined that the analog-to-digital converter has a precision error fault.

4. The method for diagnosing faults of an analog-to-digital converter according to claim 3, characterized in that: The first standard value is calculated by a quantization formula of the analog-to-digital converter using the voltage of the reference power supply as an input parameter; The second standard value is calculated by the quantization formula with the inverse of the voltage of the reference power supply as an input parameter; The quantization formula is determined by the number of code bits of the analog-to-digital converter and the voltage of the reference power supply.

5. The method for diagnosing faults of an analog-to-digital converter according to claim 4, characterized in that: The quantification formula is specifically: CODE=2 N-1 (VIN×0.1÷VREF+1); Wherein, CODE is the calculation result, VIN is the input parameter, N is the number of code bits of the analog-to-digital converter, and VREF is the voltage of the reference power supply.

6. The method for diagnosing faults of an analog-to-digital converter according to claim 3, characterized in that: Before calculating a first difference between the first binary value and the first standard value and calculating a second difference between the second binary value and the second standard value, the method further includes: The first binary value, the first standard value, the second binary value and the second standard value are unified into the same base.

7. The method for diagnosing faults of an analog-to-digital converter according to any one of claims 1 to 6, characterized in that: The remaining differential acquisition channels of the analog-to-digital converter are first-category channels or second-category channels, wherein the first pins of the first-category channels are all connected to the positive electrode, the second pins of the first-category channels are all connected to the negative electrode, the first pins of the second-category channels are all connected to the negative electrode, and the second pins of the second-category channels are all connected to the positive electrode, and the method further includes: Obtaining binary values ​​corresponding to the remaining differential acquisition channels through the analog-to-digital converter; Determining whether a channel detection condition is satisfied based on the first binary value, the second binary value, and all the binary values, the channel detection condition comprising: the binary values ​​of all the first-category channels are the same as the first binary value and the binary values ​​of all the second-category channels are the same as the second binary value; If not, it is determined that a channel failure occurs in the analog-to-digital converter.

8. An analog-to-digital converter fault diagnosis device, characterized in that: Applied to a controller, the controller is connected to the output end of an analog-to-digital converter, a first pin of a first differential acquisition channel of the analog-to-digital converter is connected to the positive electrode of a preset power supply, a second pin of the first differential acquisition channel is connected to the negative electrode of the preset power supply, a first pin of a second differential acquisition channel of the analog-to-digital converter is connected to the negative electrode, and a second pin of the second differential acquisition channel is connected to the positive electrode, the device comprises: an acquisition module, configured to acquire a first binary value corresponding to the first differential acquisition channel through the analog-to-digital converter, and further configured to acquire a second binary value corresponding to the second differential acquisition channel through the analog-to-digital converter; The judgment module is used to judge whether the first binary value and the second binary value are complementary. If so, it is determined that the analog-to-digital converter has no stuck position fault; if not, it is determined that the analog-to-digital converter has a stuck position fault.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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