Self-excitation protection nanosecond control method and device of transmitting system, storage medium and electronic equipment

By using the self -stimulus protection FPGA dynamic adjustment timing in the radio frequency communication transmission system, the contradiction between radio frequency self -excitation and component anti -burning protection and the performance improvement of the transmitting system is solved, and the protection of high response and precision meta -device is achieved.

CN119363133APending Publication Date: 2025-01-24SOUTHWEST CHINA RES INST OF ELECTRONICS EQUIP
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Patent Information

Application Number
CN202411480819.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-10-23
Publication Date
2025-01-24

AI Technical Summary

Technical Problem

In the field of RF communication, there is a contradiction between RF self-excitation and component burn-out protection in modern transmitting systems and the improvement of overall transmitting system performance, making it difficult to protect high responsiveness and precision and high-cost components.

Method used

By self -stress protection FPGA -based transmitting system parameter configuration to generate system -level self -stimulating protection original timing, and adjust according to the internal architecture of the transmitting system and the full system radiation link situation, dynamic adaptive burning protection adjustment adjustment, generate component -level self -excitement Protective output timing to achieve nano -second control.

Benefits of technology

Improve the response efficiency of the launch system and the anti -burning protection capacity of components, and enhance the response capacity of the launch system and the self -excitation capacity of the component.

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Abstract

The embodiment of the invention provides a self-excitation protection nanosecond-level control method and device for a transmitting system, a storage medium and electronic equipment, and relates to the technical field of radio frequency communication application, and the method comprises the steps that a self-excitation protection FPGA generates a preliminary system-level self-excitation protection original time sequence based on transmitting state parameter configuration of the transmitting system; adjusting and generating a component-level self-excitation protection time sequence based on the system-level self-excitation protection original time sequence according to the internal architecture of the transmitting system and the radio frequency link condition of the whole system; according to the design characteristics of the transmitting system, performing dynamic self-adaptive burnout protection adjustment on the component-level self-excitation protection time sequence, and generating a component-level self-excitation protection output time sequence; and self-excitation protection related components in the transmitting system perform self-excitation protection control based on the component-level self-excitation protection output time sequence. The method has the advantages of low cost, high robustness, miniaturization, high stability, low delay and the like.
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Description

Technical Field

[0001] The present application relates to the field of radio frequency communication application technology, and in particular to a method, device, storage medium and electronic device for nanosecond level control of self-excitation protection of a transmitting system. Background Art

[0002] In the field of RF communications, with the improvement of the capabilities of RF components such as power amplifiers and antennas in modern transmission systems, and the continuous development of precision and integration of electronic components, the contradiction between the internal RF self-excitation and component burn-out protection of high-power transmission systems and the improvement of the overall transmission system performance has become increasingly obvious. Summary of the invention

[0003] The embodiments of the present application provide a nanosecond level control method, device, storage medium and electronic device for self-excitation protection of a transmitting system, so as to improve the response efficiency of a high-responsiveness transmitting system and enhance the protection against burnout of high-precision and high-cost components inside the transmitting system, thereby improving the responsiveness of the transmitting system and enhancing the self-excitation and burnout protection capabilities of the components.

[0004] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0005] According to a first aspect of an embodiment of the present application, a method for nanosecond control of self-excitation protection of a transmitting system is provided, comprising:

[0006] The self-excitation protection FPGA generates a preliminary system-level self-excitation protection original timing based on the transmission state parameter configuration of the transmission system;

[0007] According to the internal architecture of the transmitting system and the radio frequency link conditions of the whole system, the component-level self-excitation protection timing is adjusted based on the original timing of the system-level self-excitation protection;

[0008] According to the design characteristics of the transmitting system, dynamically and adaptively adjust the component-level self-excitation protection timing to generate a component-level self-excitation protection output timing;

[0009] Each self-excitation protection related component in the transmitting system performs self-excitation protection control based on the component-level self-excitation protection output timing.

[0010] In some embodiments of the present application, based on the aforementioned solution, the configuration of generating a preliminary system-level self-excitation protection original timing sequence based on the transmission state parameter configuration of the transmission system includes:

[0011] Parse the self-excitation protection control command packet sent by the transmitting system to the self-excitation protection FPGA to determine the transmitting state parameters of the transmitting system;

[0012] The self-excitation protection FPGA generates a preliminary system-level self-excitation protection original timing according to the transmission state parameter configuration.

[0013] In some embodiments of the present application, based on the aforementioned solution, the method of adjusting and generating a component-level self-excitation protection timing based on the system-level self-excitation protection original timing according to the internal architecture of the transmitting system and the RF link status of the entire system includes:

[0014] According to the delay amount currently set in the transmitting system, the delay logic circuit formed by the LUT resources inside the transmitting system delays the original timing of the system-level self-excitation protection;

[0015] According to the trailing edge stretching amount currently set for the transmitting system, the delayed system-level self-excitation protection original timing is trailing-edge stretched, and then the component-level self-excitation protection timing is outputted.

[0016] In some embodiments of the present application, based on the aforementioned solution, each self-excitation protection related component in the transmitting system performs self-excitation protection control based on the component-level self-excitation protection output timing, including:

[0017] The component-level self-excitation protection output timing is level-converted and sent to each self-excitation protection related component in the transmitting system;

[0018] Each self-excitation protection related component in the transmitting system performs self-excitation protection control based on the component-level self-excitation protection output timing after level conversion.

[0019] In some embodiments of the present application, based on the aforementioned scheme, the respective excitation protection related components in the transmitting system include: frequency conversion components, switch components, power amplifier related components and antenna related components.

[0020] According to a second aspect of an embodiment of the present application, there is provided a nanosecond control device for self-excitation protection of a transmitting system, comprising:

[0021] A first generating unit is used to generate a preliminary system-level self-excitation protection original timing sequence based on the transmission state parameter configuration of the transmission system;

[0022] The second generating unit is used to adjust and generate the component-level self-excitation protection timing based on the system-level self-excitation protection original timing according to the internal architecture of the transmitting system and the radio frequency link status of the whole system;

[0023] A third generating unit is used to dynamically and adaptively adjust the component-level self-excitation protection timing according to the design characteristics of the transmitting system to generate a component-level self-excitation protection output timing;

[0024] A control unit is used to perform self-excitation protection control based on the component-level self-excitation protection output timing.

[0025] According to a third aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein the storage medium stores computer instructions, and when the computer instructions are executed on a computer, the computer executes the method according to the first aspect.

[0026] According to a fourth aspect of the embodiments of the present application, there is provided an electronic device, including: a memory and a processor;

[0027] The memory is used to store computer instructions;

[0028] The processor is used to call the computer instructions stored in the memory so that the electronic device executes the method as described in the first aspect.

[0029] This application has the advantages of low cost, high robustness, miniaturization, strong stability and low latency.

[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0032] Figure 1 A schematic flow chart of a method for controlling self-excitation protection of a transmitting system in nanoseconds according to an embodiment of the present application is shown;

[0033] Figure 2 A schematic block diagram showing the principle of a method for controlling self-excitation protection of a transmitting system in nanoseconds according to an embodiment of the present application is shown;

[0034] Figure 3 A schematic diagram of the principle of adjusting the original timing sequence of system-level self-excitation protection according to an embodiment of the present application is shown;

[0035] Figure 4 A block diagram of a nanosecond control device for self-excitation protection of a transmitting system according to an embodiment of the present application is shown;

[0036] Figure 5 A block diagram of an electronic device according to an embodiment of the present application is shown;

[0037] Figure 6A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0039] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0040] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0041] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0042] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] Some embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0044] In response to the demands of modern RF transceiver systems for increased transmission power, high transmission response speed requirements, and high RF protection requirements for high-cost precision electronic components, and in order to comprehensively improve the efficiency of self-excitation protection of the transmission system and significantly shorten the self-excitation protection time, and to provide refined operating means for the initial investigation of the entire RF link of the transmission system, an embodiment of the present application proposes a nanosecond control method for self-excitation protection of the transmission system.

[0045] See also Figure 1 , shows a flow chart of a method for nanosecond level control of self-excitation protection of a transmitting system according to an embodiment of the present application.

[0046] like Figure 1 As shown, a nanosecond level control method for self-excitation protection of a transmitting system is presented, which specifically includes steps S100 to S400.

[0047] refer to Figure 1 , step S100, the self-excitation protection FPGA generates a preliminary system-level self-excitation protection original timing based on the transmission state parameter configuration of the transmission system.

[0048] In some feasible embodiments, based on the above scheme, the generating of a preliminary system-level self-excitation protection original timing sequence based on the transmission state parameter configuration of the transmission system includes:

[0049] Parse the self-excitation protection control command packet sent by the transmitting system to the self-excitation protection FPGA to determine the transmitting state parameters of the transmitting system;

[0050] The self-excitation protection FPGA generates a preliminary system-level self-excitation protection original timing according to the transmission state parameter configuration.

[0051] It should be noted that the transmission state parameters include but are not limited to protection timing phase, width, self-excitation protection mutual correlation parameters, adaptive anti-burning various levels of function enabling parameters, etc.

[0052] Continue to refer Figure 1 , step S200, according to the internal architecture of the transmitting system and the radio frequency link status of the whole system, the component-level self-excitation protection timing is adjusted based on the original timing of the system-level self-excitation protection.

[0053] In some feasible embodiments, based on the above scheme, the method of adjusting and generating the component-level self-excitation protection timing based on the system-level self-excitation protection original timing according to the internal architecture of the transmitting system and the RF link status of the whole system includes:

[0054] According to the delay amount currently set in the transmitting system, the delay logic circuit formed by the LUT resources inside the transmitting system delays the original timing of the system-level self-excitation protection;

[0055] According to the trailing edge stretching amount currently set for the transmitting system, the delayed system-level self-excitation protection original timing is trailing-edge stretched, and then the component-level self-excitation protection timing is outputted.

[0056] Continue to refer Figure 1 , step S300, according to the design characteristics of the transmitting system, dynamically adaptively adjust the component-level self-excitation protection timing to generate a component-level self-excitation protection output timing.

[0057] It should be noted that the purpose of dynamically adaptively adjusting the component-level self-excitation protection timing to prevent the central control unit from mistakenly sending unreasonable parameters, which may lead to irreversible damage to the internal components of the transmitting system.

[0058] Continue to refer Figure 1 , step S400, each self-excitation protection related component in the transmitting system performs self-excitation protection control based on the component-level self-excitation protection output timing.

[0059] In some feasible embodiments, based on the above scheme, each self-excitation protection related component in the transmitting system performs self-excitation protection control based on the component-level self-excitation protection output timing, including:

[0060] The self-excitation protection FPGA performs level conversion on the component-level self-excitation protection output timing and sends it to each self-excitation protection related component in the transmitting system;

[0061] Each self-excitation protection related component in the transmitting system performs self-excitation protection control based on the component-level self-excitation protection output timing after level conversion.

[0062] For example, see Figure 2 , showing a principle schematic block diagram of a nanosecond level control method for self-excitation protection of a transmitting system.

[0063] like Figure 2 As shown:

[0064] 1) The user sends a self-excitation protection control command packet to the self-excitation protection FPGA through the central control unit such as the software and operating system related to the transmission system. The self-excitation protection FPGA determines the protection timing phase, width, self-excitation protection mutual correlation parameters, adaptive anti-burning various functions and enabling parameters issued by the system through the command packet parser (the time-related parameter unit is based on the design of the transmission system, and the parameter unit is between 3 and 10ns);

[0065] 2) The self-excitation protection FPGA generates a preliminary system-level self-excitation protection original timing according to the transmission state parameter configuration of the transmission system;

[0066] 3) According to the internal architecture of the transmission system and the RF link of the whole system, as well as the current control parameters of the central control unit, multiple copies of the original timing are generated and the phase, width, delay, etc. between the copies of the timing are adjusted to generate the component-level self-excitation protection timing. For details, see Figure 3 ;

[0067] 4) According to the design characteristics of the transmitting system, the component-level self-excitation protection timing is dynamically and adaptively adjusted for burnout protection to avoid the central control unit mistakenly sending unreasonable parameters, which may cause irreversible damage to the internal components of the transmitting system. The component-level self-excitation protection output timing is generated, and the delay and trailing edge widening processing logic circuit design method of the component-level self-excitation protection output timing and the delay and trailing edge widening processing logic circuit design method of the component-level self-excitation protection timing are generated (see Figure 3 ) are substantially the same;

[0068] 5) The self-excitation protection FPGA performs necessary level conversion and other low-level interface operations on the component-level self-excitation protection output timing and sends it to each self-excitation protection related component in the transmitting system, which is synchronized with the RF transmission.

[0069] In summary, the method provided in the embodiment of the present application can achieve nanosecond-level control of self-excitation protection by using only one low-cost small FPGA without using other hardware or modules.

[0070] Specifically, the method provided in the embodiment of the present application has the following advantages:

[0071] (1) Low latency: All contents of this method are implemented through FPGA circuits, which effectively shortens the transmission state switching delay and waiting time of the transmission system;

[0072] (2) Fine control: This method uses FPGA to perform timing processing, can perform nanosecond-level control based on the clock, and can finely adjust the self-excitation protection time of the transmitting system;

[0073] (3) Low cost: This method can be implemented with only a small FPGA and related simple peripheral interface circuits, which is low cost;

[0074] (4) High stability: This method implements all method contents through FPGA circuits, and the output timing has only extremely low jitter of a few nanoseconds or even picoseconds, which has highly stable consistency for the self-excitation protection of the entire system;

[0075] (5) High robustness: This method can design an adaptive anti-burnout algorithm based on the design architecture characteristics of different launch systems through the characteristics of FPGA programmable circuits. It can effectively prevent the central control unit of the launch system from causing serious error control due to various misoperations, command packet errors, unreasonable parameter configuration, software-level bugs, operating system-level problems, etc., which in turn cause permanent and irreversible burning of high-cost and high-precision components inside the system.

[0076] The following describes an embodiment of the device of the present application, which can be used to implement a method for controlling the self-excitation protection of a transmitting system in the above embodiment of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the above method of the present application.

[0077] Reference Figure 4 As shown, a nanosecond control device 400 for self-excitation protection of a transmitting system according to an embodiment of the present application includes:

[0078] The first generating unit 401 is used to generate a preliminary system-level self-excitation protection original timing sequence based on the transmission state parameter configuration of the transmission system;

[0079] The second generating unit 402 is used to adjust and generate a component-level self-excitation protection timing sequence based on the system-level self-excitation protection original timing sequence according to the internal architecture of the transmitting system and the radio frequency link status of the whole system;

[0080] The third generating unit 403 is used to dynamically and adaptively adjust the component-level self-excitation protection timing according to the design characteristics of the transmitting system to generate a component-level self-excitation protection output timing;

[0081] The control unit 404 is used to perform self-excitation protection control based on the component-level self-excitation protection output timing.

[0082] like Figure 5 As shown, an embodiment of the present application also provides an electronic device 500, including a memory 510, a processor 520, and a computer program 511 stored in the memory 510 and executable on the processor, and when the processor 520 executes the computer program 511, the steps of the above-mentioned method for nanosecond control of self-excitation protection of a transmitting system are implemented.

[0083] Since the electronic device introduced in this embodiment is a device used to implement a nanosecond control device for self-excitation protection of a transmitting system in the embodiment of the present application, based on the method introduced in the embodiment of the present application, technical personnel in this field can understand the specific implementation method of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by technical personnel in this field to implement the method in the embodiment of the present application is within the scope of protection of this application.

[0084] During the specific implementation process, when the computer program 511 is executed by a processor, any implementation method in the embodiments corresponding to the first aspect can be implemented.

[0085] Figure 6 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown.

[0086] It should be noted that Figure 6 The computer system 600 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0087] like Figure 6 As shown, the computer system 600 includes a central processing unit (CPU) 601, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 602 or the program loaded from the storage part 608 to the random access memory (RAM) 603, such as executing the method described in the above embodiment. In the RAM 603, various programs and data required for system operation are also stored. The CPU 601, ROM 602 and RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0088] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed so that a computer program read therefrom is installed into the storage section 608 as needed.

[0089] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication section 609, and / or installed from a removable medium 611. When the computer program is executed by a central processing unit (CPU) 601, various functions defined in the system of the present application are executed.

[0090] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by an instruction execution system, device or device or used in combination with it. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0091] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0092] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0093] As another aspect, the present application also provides a computer program product or a computer program, the computer program product or the computer program including computer instructions, the computer instructions being stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes a method for controlling the self-excitation protection of a transmitting system in nanoseconds as described in the above embodiment.

[0094] As another aspect, the present application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements a method for controlling the self-excitation protection of a transmitting system in nanoseconds as described in the above embodiment.

[0095] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0096] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the implementation methods of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the implementation methods of the present application.

[0097] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. It should be understood that the present application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A nanosecond control method for self-excitation protection of a transmitting system, characterized in that: include: The self-excitation protection FPGA generates a preliminary system-level self-excitation protection original timing based on the transmission state parameter configuration of the transmission system; According to the internal architecture of the transmitting system and the radio frequency link conditions of the whole system, the component-level self-excitation protection timing is adjusted based on the original timing of the system-level self-excitation protection; According to the design characteristics of the transmitting system, dynamically and adaptively adjust the component-level self-excitation protection timing to generate a component-level self-excitation protection output timing; Each self-excitation protection related component in the transmitting system performs self-excitation protection control based on the component-level self-excitation protection output timing.

2. The method according to claim 1, characterized in that The generating of a preliminary system-level self-excitation protection original timing sequence based on the transmitting state parameter configuration of the transmitting system includes: Parse the self-excitation protection control command packet sent by the transmitting system to the self-excitation protection FPGA to determine the transmitting state parameters of the transmitting system; The self-excitation protection FPGA generates a preliminary system-level self-excitation protection original timing according to the transmission state parameter configuration.

3. The method according to claim 1, characterized in that The method of adjusting and generating a component-level self-excitation protection timing sequence based on the system-level self-excitation protection original timing sequence according to the internal architecture of the transmitting system and the radio frequency link status of the whole system includes: According to the delay amount currently set in the transmitting system, the delay logic circuit formed by the LUT resources inside the transmitting system delays the original timing of the system-level self-excitation protection; According to the trailing edge stretching amount currently set for the transmitting system, the delayed system-level self-excitation protection original timing is trailing-edge stretched, and then the component-level self-excitation protection timing is outputted.

4. The method according to claim 1, characterized in that Each self-excitation protection related component in the transmitting system performs self-excitation protection control based on the component-level self-excitation protection output timing, including: The self-excitation protection FPGA performs level conversion on the component-level self-excitation protection output timing and sends it to each self-excitation protection related component in the transmitting system; Each self-excitation protection related component in the transmitting system performs self-excitation protection control based on the component-level self-excitation protection output timing after level conversion.

5. The method according to claim 1, characterized in that The excitation protection related components in the transmitting system include: frequency conversion components, switch components, power amplifier related components and antenna related components.

6. A nanosecond control device for self-excitation protection of a transmitting system, characterized in that: include: A first generating unit is used to generate a preliminary system-level self-excitation protection original timing sequence based on the transmission state parameter configuration of the transmission system; The second generating unit is used to adjust and generate the component-level self-excitation protection timing based on the system-level self-excitation protection original timing according to the internal architecture of the transmitting system and the radio frequency link status of the whole system; A third generating unit is used to dynamically and adaptively adjust the component-level self-excitation protection timing according to the design characteristics of the transmitting system to generate a component-level self-excitation protection output timing; A control unit is used to perform self-excitation protection control based on the component-level self-excitation protection output timing.

7. A computer-readable storage medium, characterized in that: The storage medium stores computer instructions, and when the computer instructions are executed on a computer, the computer is enabled to execute the method according to any one of claims 1 to 5.

8. An electronic device, characterized in that: include: Memory and processor; The memory is used to store computer instructions; The processor is used to call the computer instructions stored in the memory so that the electronic device executes the method as described in any one of claims 1-5.