Repeater near-end machine, system and input power detection method thereof

Abstract

The invention belongs to the technical field of digital optical fiber repeaters. The invention provides a repeater near-end machine with an input power self-checking function. The repeater near-end machine comprises an antenna I, a duplexer I, a low-noise power amplifier I, a radio frequency power amplifier I, a broadband transceiver chip I, an FPGA I and an optical module I, the first antenna is connected with the first duplexer, the first duplexer is connected with the first low-noise power amplifier and the first radio frequency power amplifier, the first low-noise power amplifier and the first radio frequency power amplifier are connected with the first broadband transceiving chip, the first broadband transceiving chip is connected with the first FPGA, and the first FPGA is connected with the first optical module. The FPGA I reads the real-time chip port input power stored by the broadband transceiver chip I, and calculates the real-time input power of the near-end machine in combination with the power correction coefficient; the real-time input power is a difference value between the real-time chip port input power and the power correction coefficient. Therefore, the input power detection of the antenna port of the digital optical fiber repeater is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of digital optical fiber repeater stations, and in particular relates to a near-end machine of a repeater station, a system and an input power detection method thereof. Background Art

[0002] Digital fiber repeater, also called fiber repeater or fiber repeater, is a device that uses optical fiber as a transmission medium to extend the coverage of mobile communication networks and enhance signal quality. It usually consists of three parts: near-end machine, optical fiber and far-end machine. The near-end machine is located at the base station side. The antenna of the near-end machine receives the RF signal from the base station and converts the RF signal into an intermediate frequency signal through a down-converter. The intermediate frequency signal is modulated onto the laser through a modulator to convert the electrical signal into an optical signal. The modulated optical signal is sent to the far-end machine through an optical fiber. The optical signal is transmitted in the optical fiber, which has the advantages of low loss, high bandwidth, and strong anti-interference ability, making it suitable for long-distance transmission. The far-end machine is located in the coverage area. The optical receiver of the far-end machine receives the optical signal and converts it back into an electrical signal. The intermediate frequency signal is converted back into an RF signal through an up-converter so that it can be transmitted through the antenna. The amplified RF signal is transmitted through the antenna of the far-end machine to cover the target area, thereby expanding the coverage of the mobile network.

[0003] Input power detection of repeaters is an important part of maintaining and managing mobile communication networks. Input power detection can help maintenance personnel understand the signal strength received by the repeater, which is a prerequisite for ensuring that the repeater can correctly amplify and forward the signal. If the input power is too low, the repeater may not work properly; if the input power is too high, it may cause equipment overload and damage the hardware. By monitoring the input power, the repeater can be optimized to achieve the best signal coverage and quality. Appropriate input power can ensure the stability and clarity of the signal and improve the performance of the network. Continuous monitoring of input power can detect abnormal conditions in time, such as a sudden increase in input power, which may indicate interference or hardware failure. Timely measures can prevent equipment damage. When there is a problem with the network, the input power detection result can serve as an important basis for fault diagnosis.

[0004] In the prior art, the scheme for implementing input power self-checking in a repeater is to use a coupler at the near-end machine to couple a signal to a detector for signal detection, which will increase the hardware cost. Another scheme is to use FPGA to periodically accumulate the square of the digital signal amplitude for digital intermediate frequency or digital baseband signals, and store the accumulated result in the register of the field programmable gate array FPGA. The processor ARM queries the value of this register through the I2C bus. The processor ARM converts the queried power value into a value in dBm and subtracts it from a power calibration value to obtain the input and output power of the system digital intermediate frequency, and also the input and output power of the system analog intermediate frequency and radio frequency. The algorithm of this scheme is complex and consumes FPGA resources, increasing the cost of FPGA hardware selection. Summary of the invention

[0005] The present invention aims to solve the problem that the input power detection of the antenna port of the digital optical fiber repeater in the prior art requires additional hardware cost, the algorithm is complex and consumes FPGA resources. A near-end machine of the repeater, a system and an input power detection method thereof are provided, so as to realize the real-time detection of the input power of the antenna port of the digital optical fiber repeater without additionally increasing the hardware cost.

[0006] The present invention provides a near-end repeater with an input power self-checking function, characterized in that it comprises an antenna, a duplexer, a low-noise power amplifier, a radio frequency power amplifier, a broadband transceiver chip, an FPGA, and an optical module; the antenna is connected to the duplexer, the duplexer is respectively connected to the low-noise power amplifier and the radio frequency power amplifier, the low-noise power amplifier and the radio frequency power amplifier are respectively connected to the broadband transceiver chip, the broadband transceiver chip is connected to the FPGA, and the FPGA is connected to the optical module;

[0007] The antenna 1 is used to receive input information from a signal source and realize the transmission of uplink and downlink signals between the base station and the near-end device;

[0008] The duplexer 1 is used to separate the uplink signal from the downlink signal to prevent mutual interference; and transmit the downlink signal to the low noise power amplifier 1, while receiving the uplink signal transmitted by the radio frequency power amplifier 1;

[0009] The low noise power amplifier 1 is used to amplify the downlink signal, reduce the introduced noise, and transmit it to the broadband transceiver chip 1;

[0010] The broadband transceiver chip 1 is used to receive the downlink RF signal transmitted from the low-noise power amplifier 1, perform down-conversion processing on the downlink RF signal to obtain the intermediate frequency baseband signal and then transmit it; at the same time, it is used to up-convert the intermediate frequency baseband signal transmitted from the remote machine to the RF signal, and transmit it to the RF power amplifier 1 after processing; at the same time, it is also used to detect the chip port input power in real time and store it;

[0011] The RF power amplifier 1 is used to receive the uplink signal transmitted from the broadband transceiver chip 1, amplify the uplink signal, and transmit it to the duplexer 1;

[0012] The FPGA 1 is used to embed the baseband signal into the protocol frame to achieve efficient transmission and formatting of the baseband signal to adapt to the communication protocol standard; it is used to ensure that when a near-end machine is cascaded with multiple remote machines, the timing of sending and receiving signals between the remote machines is consistent and the clock is synchronized; it is also used to read the real-time chip port input power stored in the broadband transceiver chip 1, and calculate the real-time input power of the antenna 1 in combination with the preset power correction coefficient; the real-time input power is the difference between the real-time chip port input power and the power correction coefficient;

[0013] The optical module one is used to perform photoelectric conversion on the uplink signal and the downlink signal, and communicate with the remote machine through the optical fiber. There is at least one optical module one.

[0014] In some real-time examples, the power correction factor calculation formula is as follows:

[0015] X = P1-P2;

[0016] Wherein, X is the power correction coefficient, P1 is the chip port input power, and P2 is the input power of the signal source corresponding to the chip port input power.

[0017] In some real-time examples, the broadband transceiver chip 1 is a broadband transceiver chip with an internal RSSI detection function, and the broadband transceiver chip 1 is AD9363, AD9371 or ADRV9009.

[0018] The present invention also provides an input power detection method for the above-mentioned near-end machine, comprising the following steps:

[0019] Step 1: Calculate the near-end power detection range based on the dynamic detection range of the broadband transceiver chip 1, the gain of the low-noise power amplifier 1, and the gain of the duplexer 1;

[0020] Step 2: Control the signal source to send an input signal that meets the near-end power detection range to the repeater, detect the chip port input power of the broadband transceiver chip 1 at this time, calculate the power correction coefficient, and send it to FPGA 1; the power correction coefficient calculation formula is as follows:

[0021] X = P1-P2;

[0022] Where X is the power correction coefficient, P1 is the chip port input power; P2 is the signal source input signal power;

[0023] Step 3: The broadband transceiver chip detects the input power of the chip port in real time and stores it;

[0024] Step 4: FPGA reads the real-time chip port input power stored in broadband transceiver chip 1, and calculates the real-time input power of the near-end machine in combination with the power correction coefficient; the real-time input power is the difference between the real-time chip port input power and the power correction coefficient.

[0025] The present invention also provides a repeater system with an input power self-checking function, wherein the near-end machine is connected to the far-end machine via an optical fiber, and the near-end machine is the repeater near-end machine with an input power self-checking function as described in any one of the above items.

[0026] In some real-time examples, the remote machine includes antenna two, duplexer two, low-noise power amplifier two, RF power amplifier two, broadband transceiver chip two, FPGA two and optical module two; antenna two is connected to duplexer two, duplexer two is respectively connected to low-noise power amplifier two and RF power amplifier two, low-noise power amplifier two and RF power amplifier two are respectively connected to broadband transceiver chip two, broadband transceiver chip two is connected to FPGA two, and FPGA two is connected to optical module two.

[0027] In some real-time examples, the broadband transceiver chip 2 is a broadband transceiver chip with an internal RSSI detection function, and the broadband transceiver chip is AD9363, AD9371 or ADRV9009.

[0028] The present invention also provides an input power detection method for the above-mentioned repeater system, comprising the following steps:

[0029] Step 1: Calculate the near-end power detection range based on the dynamic detection range of the broadband transceiver chip 1, the gain of the low-noise power amplifier 1, and the gain of the duplexer 1;

[0030] Step 2: Control the signal source to send an input signal that meets the near-end power detection range to the repeater, detect the chip port input power of the broadband transceiver chip 1 at this time, calculate the power correction coefficient, and send it to FPGA 1; the power correction coefficient calculation formula is as follows:

[0031] X = P1-P2;

[0032] Where X is the power correction coefficient, P1 is the chip port input power; P2 is the signal source input signal power;

[0033] Step 3: The broadband transceiver chip detects the input power of the chip port in real time and stores it;

[0034] Step 3: FPGA reads the real-time chip port input power stored in broadband transceiver chip 1, and calculates the real-time input power of the repeater system in combination with the power correction coefficient; the real-time input power is the difference between the real-time chip port input power and the power correction coefficient.

[0035] The present invention also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor executes the steps of the input power detection method of the repeater system as described above.

[0036] The present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the input power detection method of the repeater system as described above when executing the computer program.

[0037] The beneficial effect of the present invention is that the near-end machine in the digital optical fiber repeater detects the real-time chip port input power of its own broadband transceiver chip and combines the pre-calculated power correction coefficient to realize the input power detection of the antenna port of the digital optical fiber repeater. The present invention can realize the input power detection of the antenna port of the repeater without adding new hardware, and the algorithm is very simple and does not occupy FPGA resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 , a structural diagram of a digital optical fiber repeater system in a specific implementation manner of the present invention. DETAILED DESCRIPTION

[0039] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] like Figure 1 As shown, in this example, a repeater system with input power self-detection function is provided, and the near-end machine is connected to the far-end machine through an optical fiber. The present invention uses ADI's broadband transceiver IC (such as AD9363, AD9371 and ADRV9009, etc.) to design a digital optical fiber repeater, and uses the internal RSSI detection function of the chip to realize the input power detection of the repeater antenna port without increasing the hardware cost.

[0041] The near-end device of the repeater station includes an antenna 1, a duplexer 1, a low-noise power amplifier (LNA) 1, a radio frequency power amplifier (PA) 1, a broadband transceiver chip 1, an FPGA 1, and an optical module 1; the antenna 1 is connected to the duplexer 1, the duplexer 1 is respectively connected to the low-noise power amplifier 1 and the radio frequency power amplifier 1, the low-noise power amplifier 1 and the radio frequency power amplifier 1 are respectively connected to the broadband transceiver chip 1, the broadband transceiver chip 1 is connected to the FPGA 1, and the FPGA 1 is connected to the optical module (SFP) 1. As mentioned above, the broadband transceiver chip 1 is a broadband transceiver IC of ADI (such as AD9363, AD9371 or ADRV9009, etc.).

[0042] Among them, antenna 1 is used to receive the input information of the signal source to realize the transmission of uplink and downlink signals between the base station and the near-end machine. Duplexer 1 is used to separate the uplink signal from the downlink signal to prevent mutual interference; and transmit the downlink to the low-noise power amplifier 1, and at the same time receive the uplink signal transmitted by the radio frequency power amplifier 1. Low-noise power amplifier 1 is used to amplify the downlink signal, reduce the introduced noise, and transmit it to the broadband transceiver chip 1. Broadband transceiver chip 1 is used to receive the downlink radio frequency signal transmitted by the low-noise power amplifier 1, down-convert it to obtain the intermediate frequency baseband signal and then transmit it; at the same time, it is used to up-convert the intermediate frequency baseband signal transmitted by the remote machine to the radio frequency signal, and transmit it to the radio frequency power amplifier 1 after processing; at the same time, it is also used to detect the chip port input power in real time and store it. Radio frequency power amplifier 1 is used to receive the uplink signal transmitted by the broadband transceiver chip 1, amplify the uplink signal, and transmit it to the duplexer 1. FPGA 1 is used to embed the baseband signal into the protocol frame to achieve efficient transmission and formatting of the baseband signal to adapt to the communication protocol standard; it is used to ensure that when a near-end machine is cascaded with multiple remote machines, the timing of sending and receiving signals between the remote machines is consistent and the clock is synchronized. In order to achieve power detection, in this example, FPGA 1 is also used to read the real-time chip port input power stored in broadband transceiver chip 1, and calculate the real-time input power of antenna 1 in combination with the preset power correction coefficient; the real-time input power is the difference between the real-time chip port input power and the power correction coefficient. Optical module 1 is used to perform photoelectric conversion on the uplink signal and the downlink signal, and communicate with the remote machine through optical fiber. There is at least one optical module 1.

[0043] The detection method of the near-end machine is as follows. First, the signal source is used to calculate the power correction coefficient. Specifically, the signal source is controlled to output any sine wave, LTE or NR fixed power signal that meets the requirements of the near-end machine's operating frequency range and the detection power range as an input signal to the near-end machine. The chip port input power of the broadband transceiver chip 1 is detected at this time to calculate the power correction coefficient (the default value is 0). The correction coefficient calculation formula is: X=P1-P2. Among them, X is the power correction coefficient, P1 is the chip port input power; P2 is the input power of the input signal. After the correction coefficient is confirmed, it is sent to FPGA 1 for storage and use. Among them, the detection power range of the repeater is determined by the dynamic detection range of the broadband transceiver chip 1, the gain of the low-noise power amplifier 1, and the gain of the duplexer 1. Preferably, when calculating the detection power range of the repeater, the internal cable loss can be further considered to ensure the accuracy of the detection power range of the repeater.

[0044] When working, the broadband transceiver chip performs real-time detection and storage of the chip port input power. The FPGA reads the RSSI power detection register value of the broadband transceiver chip through the SPI interface, converts the chip port real-time input power, and calculates the real-time input power of the near-end machine in combination with the power correction coefficient. The real-time input power is the difference between the real-time chip port input power and the power correction coefficient.

[0045] The remote end of the repeater station includes antenna 2, duplexer 2, low-noise power amplifier 2, radio frequency power amplifier 2, broadband transceiver chip 2, FPGA 2 and optical module 2; the antenna 2 is connected to the duplexer 2, the duplexer 2 is respectively connected to the low-noise power amplifier 2 and the radio frequency power amplifier 2, the low-noise power amplifier 2 and the radio frequency power amplifier 2 are respectively connected to the broadband transceiver chip 2, the broadband transceiver chip 2 is connected to the FPGA 2, and the FPGA 2 is connected to the optical module 2.

[0046] The input power of the repeater is the input power of the near-end machine, so the detection method of the input power of the repeater is consistent with the above-mentioned detection method of the input power of the near-end machine.

[0047] Example

[0048] In this paper, the receive power measurement is performed in the digital domain using the AD9371 chip as an example. Due to the interdependence between AGC (Automatic Gain Control) and power measurement, the power measurement duration and measurement position are variable.

[0049] Power measurement position API function setting path:

[0050] device->rx->rxAgcCtrl->rxPwrAgc->pmdMeasConfig

[0051] In this example, pmdMeasConfig=2(dec) uses the signal output at RFIR as the power detection position.

[0052] Power measurement sample number API function setting path:

[0053] device->rx->rxAgcCtrl->rxPwrAgc->pmdMeasDuration

[0054] In this example, pmdMeasConfig=8(dec), and the number of measurement samples is 8*2^8.

[0055] The power measurement resolution of the AD9371 chip is 0.25dB, and the power measurement dynamic range is 40dB. Therefore, the power detection range of the receiving channel is 0 to -40dBFs, which is converted to -8 to -48dBm (AD93710dBFs input corresponds to -8dBm). In this example, the gain of the near-end LNA module plus the duplexer is 25dB, which can detect an input signal of -33 to -73dBm at the antenna port. Furthermore, considering parameters such as internal cable loss, the actual detection power range after calibration is -31 to -71dBm.

[0056] The specific steps for testing the input power of the near-end machine and the repeater are as follows:

[0057] First, the control signal source inputs -70dBm NR TM3.1A signal to the repeater. Then, FPGA-1 reads the RSSI register value inside the AD9371 chip through the SPI interface and converts the chip port input power to -47dBm.

[0058] Then, the correction coefficient is calculated as X=-47+70=23.

[0059] The power correction coefficient 23 is passed to FPGA 1 through the host computer software, and the calculation formula Pcal=RSSI-23 is updated.

[0060] After that, when the repeater works normally, the real-time chip port input power of the AD9371 chip is monitored in real time, and the real-time input power of antenna 1 is calculated by combining the above formula, thereby realizing the input power detection of the near-end machine and the repeater.

[0061] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0062] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A near-end repeater with input power self-checking function, characterized in that: It includes an antenna 1, a duplexer 1, a low-noise power amplifier 1, a radio frequency power amplifier 1, a broadband transceiver chip 1, an FPGA 1 and an optical module 1; the antenna 1 is connected to the duplexer 1, the duplexer 1 is respectively connected to the low-noise power amplifier 1 and the radio frequency power amplifier 1, the low-noise power amplifier 1 and the radio frequency power amplifier 1 are respectively connected to the broadband transceiver chip 1, the broadband transceiver chip 1 is connected to the FPGA 1, and the FPGA 1 is connected to the optical module 1; The antenna 1 is used to receive input information from a signal source and realize the transmission of uplink and downlink signals between the base station and the near-end device; The duplexer 1 is used to separate the uplink signal from the downlink signal to prevent mutual interference; and transmit the downlink signal to the low noise power amplifier 1, while receiving the uplink signal transmitted by the radio frequency power amplifier 1; The low noise power amplifier 1 is used to amplify the downlink signal, reduce the introduced noise, and transmit it to the broadband transceiver chip 1; The broadband transceiver chip 1 is used to receive the downlink RF signal transmitted from the low-noise power amplifier 1, perform down-conversion processing on the downlink RF signal to obtain the intermediate frequency baseband signal and then transmit it; at the same time, it is used to up-convert the intermediate frequency baseband signal transmitted from the remote machine to the RF signal, and transmit it to the RF power amplifier 1 after processing; at the same time, it is also used to detect the chip port input power in real time and store it; The RF power amplifier 1 is used to receive the uplink signal transmitted from the broadband transceiver chip 1, amplify the uplink signal, and transmit it to the duplexer 1; The FPGA 1 is used to embed the baseband signal into the protocol frame to achieve efficient transmission and formatting of the baseband signal to adapt to the communication protocol standard; It is used to ensure that when a near-end machine is cascaded with multiple remote machines, the timing of sending and receiving signals between the remote machines is consistent and the clock is synchronized; it is also used to read the real-time chip port input power stored in the broadband transceiver chip 1, and calculate the real-time input power of the antenna 1 in combination with the preset power correction coefficient; The real-time input power is the difference between the real-time chip port input power and the power correction coefficient; The optical module one is used to perform photoelectric conversion on the uplink signal and the downlink signal, and communicate with the remote machine through the optical fiber. There is at least one optical module one.

2. The near-end repeater with input power self-checking function according to claim 1, characterized in that: The power correction coefficient calculation formula is as follows: X = P1-P2; Wherein, X is the power correction coefficient, P1 is the chip port input power, and P2 is the input power of the signal source corresponding to the chip port input power.

3. The near-end repeater with input power self-checking function according to claim 2, characterized in that: The broadband transceiver chip one is a broadband transceiver chip with an internal RSSI detection function, and the broadband transceiver chip one is AD9363, AD9371 or ADRV9009.

4. The input power detection method for the near-end device according to any one of claims 1 to 3, characterized in that: The following steps are involved: Step 1: Calculate the near-end power detection range based on the dynamic detection range of the broadband transceiver chip 1, the gain of the low-noise power amplifier 1, and the gain of the duplexer 1; Step 2: Control the signal source to send an input signal that meets the near-end power detection range to the repeater, detect the chip port input power of the broadband transceiver chip 1 at this time, calculate the power correction coefficient, and send it to FPGA 1; the power correction coefficient calculation formula is as follows: X = P1-P2; Where X is the power correction coefficient, P1 is the chip port input power; P2 is the signal source input signal power; Step 3: The broadband transceiver chip detects the input power of the chip port in real time and stores it; Step 4: FPGA reads the real-time chip port input power stored in broadband transceiver chip 1, and calculates the real-time input power of the near-end machine in combination with the power correction coefficient; the real-time input power is the difference between the real-time chip port input power and the power correction coefficient.

5. A repeater system with input power self-checking function, wherein the near-end unit is connected to the far-end unit via an optical fiber, characterized in that: The near-end unit is a repeater near-end unit with an input power self-checking function as claimed in any one of claims 1 to 3.

6. A repeater system with input power self-checking function according to claim 5, characterized in that: The remote device is characterized in that it includes antenna two, duplexer two, low-noise power amplifier two, radio frequency power amplifier two, broadband transceiver chip two, FPGA two and optical module two; antenna two is connected to duplexer two, duplexer two is respectively connected to low-noise power amplifier two and radio frequency power amplifier two, low-noise power amplifier two and radio frequency power amplifier two are respectively connected to broadband transceiver chip two, broadband transceiver chip two is connected to FPGA two, and FPGA two is connected to optical module two.

7. A repeater system with input power self-checking function according to claim 6, characterized in that: The broadband transceiver chip 2 is a broadband transceiver chip with an internal RSSI detection function, and the broadband transceiver chip is AD9363, AD9371 or ADRV9009.

8. The input power detection method for the repeater system according to any one of claims 5 to 7, characterized in that: The following steps are involved: Step 1: Calculate the near-end power detection range based on the dynamic detection range of the broadband transceiver chip 1, the gain of the low-noise power amplifier 1, and the gain of the duplexer 1; Step 2: Control the signal source to send an input signal that meets the near-end power detection range to the repeater, detect the chip port input power of the broadband transceiver chip 1 at this time, calculate the power correction coefficient, and send it to FPGA 1; the power correction coefficient calculation formula is as follows: X = P1-P2; Where X is the power correction coefficient, P1 is the chip port input power; P2 is the signal source input signal power; Step 3: The broadband transceiver chip detects the input power of the chip port in real time and stores it; Step 3: FPGA reads the real-time chip port input power stored in broadband transceiver chip 1, and calculates the real-time input power of the repeater system in combination with the power correction coefficient; the real-time input power is the difference between the real-time chip port input power and the power correction coefficient.

9. A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the steps of the input power detection method of the repeater system according to claim 8.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the input power detection method of the repeater system as claimed in claim 8 are implemented.

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