Memory, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a memory, a manufacturing method thereof and a memory system. The memory includes a memory cell including a memory element and a gate element arranged in a stacked manner; the first dielectric layer is arranged on the side wall of the storage unit and covers the side wall of the storage element and the side wall of the gating element in the storage unit; wherein the first dielectric layer comprises a two-dimensional material, and the two-dimensional material has anisotropic thermal conductivity.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, including but not limited to a memory and a manufacturing method thereof, and a memory system. Background Art

[0002] Phase Change Memory (PCM) is considered to be one of the most promising next-generation semiconductor storage technologies. PCM uses the difference in conductivity of the phase change layer when it transforms between the crystalline state and the amorphous state to store data; the crystalline state exhibits low resistance and the amorphous state exhibits high resistance. The process of the phase change layer transforming from the amorphous state to the crystalline state is the programming process, which can also be called the SET process; the process of the phase change layer transforming from the crystalline state to the amorphous state is the erasing process, which can also be called the RESET process. Since PCM relies on the electrothermal effect to work, heat conduction becomes a technical problem that needs to be solved in PCM. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a memory and a method for manufacturing the same, and a memory system.

[0004] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, comprising: a memory unit, comprising a stacked memory element and a gating element; a first dielectric layer arranged on a side wall of the memory unit, the first dielectric layer covering the side wall of the memory element and the side wall of the gating element in the memory unit; wherein the first dielectric layer comprises a two-dimensional material, and the two-dimensional material has anisotropic thermal conductivity.

[0006] In some embodiments, the first dielectric layer has a first thermal conductivity along a stacking direction, and the first dielectric layer has a second thermal conductivity along any direction perpendicular to the stacking direction, and the first thermal conductivity is greater than the second thermal conductivity.

[0007] In some embodiments, the first dielectric layer includes a multilayer structure, atoms in the same layer are connected by chemical bonds, and atoms in different layers are connected by van der Waals forces; wherein the rate at which heat is conducted along atoms in the same layer is greater than the rate at which heat is conducted along atoms in different layers.

[0008] In some embodiments, the first dielectric layer includes at least one of hexagonal boron nitride, two-dimensional aluminum nitride, two-dimensional gallium nitride, two-dimensional tungsten sulfide, and two-dimensional molybdenum sulfide.

[0009] In some embodiments, the thickness of the first dielectric layer is less than 10 nm.

[0010] In some embodiments, the memory further includes: a second dielectric layer disposed between the side wall of the storage unit and the first dielectric layer; and / or a third dielectric layer disposed on the side wall of the storage unit and the first dielectric layer disposed between the side wall of the storage unit and the third dielectric layer.

[0011] In some embodiments, the memory cell includes a first electrode layer, a phase change layer, a second electrode layer, a gating layer, and a third electrode layer that are stacked; wherein the first electrode layer, the phase change layer, and the second electrode layer together form the memory element, and the second electrode layer, the gating layer, and the third electrode layer together form the gating element.

[0012] In some embodiments, the memory also includes: a plurality of first conductive structures extending along a first direction and coupled to the first electrode layer; a plurality of second conductive structures extending along a second direction and coupled to the third electrode layer; wherein the storage unit is arranged between the first conductive structure and the second conductive structure, and the first dielectric layer is respectively connected to the first conductive structure and the second conductive structure.

[0013] In a second aspect, an embodiment of the present disclosure provides a memory system, comprising: a memory as described in the above technical solution; and a controller coupled to the memory and configured to control the memory.

[0014] In a third aspect, an embodiment of the present disclosure provides a method for manufacturing a memory, the method comprising: forming a memory unit, the memory unit comprising a stacked memory element and a gating element; forming a first dielectric layer on a side wall of the memory unit, the first dielectric layer covering the side wall of the memory element and the side wall of the gating element in the memory unit; wherein the first dielectric layer comprises a two-dimensional material, and the two-dimensional material has anisotropic thermal conductivity.

[0015] The disclosed embodiments provide a memory and a manufacturing method thereof, and a memory system. The memory includes: a memory unit, including a stacked memory element and a gating element; a first dielectric layer provided on the side wall of the memory unit, the first dielectric layer covering the side wall of the memory element and the gating element in the memory unit; wherein the first dielectric layer includes a two-dimensional material, and the two-dimensional material has anisotropic thermal conductivity. In the disclosed embodiments, the first dielectric layer formed by the two-dimensional material covers the side wall of the memory unit, and the two-dimensional material has anisotropic thermal conductivity. On the one hand, the target memory unit in the operating state can maintain a certain temperature, increase the RESET volume fraction of the memory, and help distinguish the SET state from the RESET state; on the other hand, the heat of the target memory unit in the operating state is not easy to diffuse to the adjacent memory unit, resulting in the crystalline-amorphous state inversion of the memory element in the adjacent memory unit, which helps to improve the write error (Write Disturb, WD) and improve the reliability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Figure (a) shows the temperature of each storage unit after using low thermal conductivity material to form a barrier layer. Figure 1 The middle (b) figure shows the temperature of each storage unit after forming a barrier layer using a high thermal conductivity material;

[0017] Figure 2 Figures (a), (b), and (c) are the temperatures corresponding to different lateral positions of the top, middle, and bottom of the phase change layer in the memory cell, respectively;

[0018] Figure 3 A schematic diagram of a memory provided for some embodiments of the present disclosure;

[0019] Figure 4A A schematic diagram of the structure of hexagonal boron nitride provided in an embodiment of the present disclosure;

[0020] Figure 4B A schematic diagram of the structure of aluminum nitride provided in an embodiment of the present disclosure;

[0021] Figure 4C A schematic diagram of the structure of tungsten sulfide provided in an embodiment of the present disclosure;

[0022] Figure 5 A diagram of various property parameters of hexagonal boron nitride provided in an embodiment of the present disclosure;

[0023] Figure 6 A schematic diagram of a memory provided for other embodiments of the present disclosure;

[0024] Figure 7 A block diagram of a memory system provided for an embodiment of the present disclosure;

[0025] Figure 8 A schematic flow chart of a method for manufacturing a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0027] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0028] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0029] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0030] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0033] Phase change memory is a new type of non-volatile memory. Phase change memory relies on the Joule heat of current to operate the phase change layer in the storage unit to transform between the crystalline state (low resistance state) and the amorphous state (high resistance state), thereby realizing the mutual transformation between the SET state and the RESET state. Phase change memory includes a storage unit, and the storage unit includes a first electrode layer, a phase change layer, a second electrode layer, a gating layer and a third electrode layer arranged in a stacked manner; a linear barrier layer (Liner) arranged on the side wall of the storage unit. The linear barrier layer is a one-layer or multi-layer structure arranged at the side wall of the storage unit, and its functions include but are not limited to protecting the phase change layer / gating layer during the process, preventing oxidation, keeping the phase change layer / gating layer warm or quickly dissipating heat, etc.

[0034] Here, various directions that may be involved in the following description are defined. The stacking direction of the first electrode layer, the phase change layer, the second electrode layer, the gating layer, and the third electrode layer stacked in the memory cell is defined as the Z direction. The intersecting X direction and Y direction are defined in a plane perpendicular to the Z direction. In some embodiments, the X direction and the Y direction may be perpendicular to each other, so that the X direction, the Y direction, and the Z direction are perpendicular to each other.

[0035] In order to improve the storage density, the phase change memory usually adopts a storage array structure. Since there is a certain critical distance (CD) deviation in the manufacturing process of the memory, in order to ensure that the phase change memories of different critical sizes can achieve a significant distinction in resistance between the SET state and the RESET state, a larger RESET current needs to be used during the operation of the phase change memory. However, the Joule heat of the larger RESET current will cause thermal disturbances to the phase change layer in the memory cell adjacent to the target memory cell in the operating state, causing the phase change layer in the adjacent memory cell to reverse from crystalline to amorphous state, causing write errors, thereby reducing the reliability of the data stored in the phase change memory. Here, the adjacent memory cells and the target memory cell are adjacent in the X direction or in the Y direction.

[0036] At present, materials with low thermal conductivity, such as silicon oxide materials, are commonly used as linear barrier layer materials, which can be understood as a thermal insulation material. This type of linear barrier layer material mainly blocks heat conduction through low thermal conductivity, prevents heat from being conducted to adjacent storage units, and improves write errors of phase change memory.

[0037] Figure 1 Figure (a) shows the temperature of each storage unit after using low thermal conductivity material to form a barrier layer. Figure 1 As shown in Figure (a), the current during the RESET process is 155μA, and the thermal conductivity of the linear barrier layer is 0.5W / (m·K). When a low thermal conductivity material is used to form a barrier layer, the simulation results show that the temperature of the target storage unit is 1135K, and the temperatures of the adjacent storage units are 469K, 466K, 470K, and 467K, respectively. In other words, when a larger current is used during the RESET process, the barrier layer formed by the low thermal conductivity material can keep the target storage unit warm, so that the temperature of the target storage unit is higher, and it also strengthens the thermal disturbance of the adjacent storage unit, so that the highest temperature of the adjacent storage unit reaches 470K, which exceeds the crystallization temperature of the phase change layer, which easily causes the phase change layer in the adjacent storage unit to undergo a crystalline-amorphous inversion, causing a write error, thereby reducing the reliability of the phase change memory.

[0038] Figure 1Figure (b) shows the temperature of each storage unit after using a high thermal conductivity material to form a barrier layer. Figure 1 As shown in Figure (b), the current during the RESET process is 155μA, and the thermal conductivity of the linear barrier layer is 20W / (m·K). When a high thermal conductivity material is used to form the barrier layer, the simulation results show that the temperature of the target storage unit is 1013K, and the temperatures of the adjacent storage units are 361K, 358K, 361K, and 358K, respectively. Figure 1 As shown in Figure (a), a barrier layer is formed by using a low thermal conductivity material. Figure 1 As shown in Figure (b), a barrier layer is formed by using a high thermal conductivity material. When the current during the RESET process is the same, Figure 1 As shown in Figure (b), the temperature of the adjacent memory cells is about 360 K, which helps to improve write errors and improve the reliability of the phase change memory. Therefore, increasing the thermal conductivity of the linear barrier layer can avoid the crystalline-amorphous state inversion of the phase change layer in the adjacent memory cells, which helps to improve write errors and thus improve the reliability of the phase change memory.

[0039] Figure 2 Figures (a), (b), and (c) are the temperatures corresponding to different lateral positions of the top, middle, and bottom of the phase change layer in the memory cell, respectively. Figure 2 As shown in Figure (a), the horizontal axis is the horizontal position, which refers to the position along the X direction or the Y direction, and the vertical axis is the temperature. Figure 2 Figure (a) in the middle shows two curves of temperature changing with lateral position. The difference between the two curves is that the thermal conductivity of the material forming the barrier layer is different. Select the vertical coordinate temperature as 640K, draw a dotted line parallel to the horizontal axis, the dotted line and the curve corresponding to the low thermal conductivity material forming the barrier layer intersect at two points, the horizontal coordinates of the two points are P1 and P2, where P1 is less than P2; the dotted line and the curve corresponding to the high thermal conductivity material forming the barrier layer intersect at two points, the horizontal coordinates of the two points are P3 and P4, where P3 is less than P4. Therefore, when the low thermal conductivity material forms the barrier layer, the size difference between the lateral positions at a temperature of 640K is (P2-P1); when the high thermal conductivity material forms the barrier layer, the size difference between the lateral positions at a temperature of 640K is (P4-P3). Since (P2-P1) is greater than (P4-P3), the thermal conductivity of the linear barrier layer increases, and the size (or radius) corresponding to the same temperature decreases, resulting in a decrease in the volume fraction of the RESET state, which leads to a decrease in the overall resistance value of the RESET state and a weakened ability to distinguish between the SET state and the RESET state. Figure 2 Similar analysis results can be obtained in Figures (b) and (c).

[0040] In summary, increasing the thermal conductivity of the linear barrier layer can prevent the crystalline-amorphous state inversion of the phase change layer in the adjacent memory cell, which helps to improve write errors and enhance the reliability of the phase change memory. However, reducing the thermal conductivity of the linear barrier layer helps to increase the volume fraction of the RESET state, which helps to distinguish the SET state from the RESET state.

[0041] Therefore, how to select a material with suitable thermal conductivity as a barrier layer becomes a technical problem that needs to be solved urgently.

[0042] refer to Figure 3 , Figure 3 Schematic diagram of a memory provided by some embodiments of the present disclosure. Figure 3 As shown, an embodiment of the present disclosure provides a memory, which includes: a memory unit 102, including a stacked memory element 104 and a gating element 106; a first dielectric layer 118 arranged on the side wall of the memory unit 102, the first dielectric layer 118 covers the side wall of the memory element 104 and the side wall of the gating element 106 in the memory unit 102; wherein the first dielectric layer 118 includes a two-dimensional material, and the two-dimensional material has anisotropic thermal conductivity.

[0043] Here, the storage element 104 and the gating element 106 are stacked and arranged along the Z direction, and the storage element 104 and the gating element 106 are electrically connected. The storage element 104 is configured to store data, and the gating element 106 is configured to control the operation of the storage element 104, and the storage element 104 is selected or deselected according to the voltage applied to the gating element 106. More specifically, if the voltage applied to the gating element 106 is greater than or equal to the preset voltage, the gating element 106 is in the on state, and the storage element 104 can be selected; if the voltage applied to the gating element 106 is less than the preset voltage, the gating element 106 is in the off state, and the storage element 104 can be deselected.

[0044] In some embodiments, the memory cell 102 includes a first electrode layer 108, a phase change layer 110, a second electrode layer 112, a gating layer 114, and a third electrode layer 116 stacked along the Z direction; wherein the first electrode layer 108, the phase change layer 110, and the second electrode layer 112 together form the memory element 104, and the second electrode layer 112, the gating layer 114, and the third electrode layer 116 together form the gating element 106.

[0045] Here, the second electrode layer 112 may be shared by the memory element 104 and the gate element 106 .

[0046] Here, the first electrode layer 108, the second electrode layer 112 and the third electrode layer 116 can be used to transmit electrical signals and can include conductive materials, such as metal materials, metal nitrides or any combination thereof. The metal material can be, for example, platinum (Pt), tungsten (W), aluminum (Al), copper (Cu) or titanium (Ti). In some embodiments, the first electrode layer 108, the second electrode layer 112 and the third electrode layer 116 can include carbon electrodes.

[0047] Here, the phase change layer 110 may include a phase change material. The phase change material may be an alloy of a chalcogenide compound, for example, a germanium antimony telluride compound (Ge-Sb-Te compound, GST), a germanium antimony compound, an indium germanium telluride compound, an aluminum selenide telluride compound, an indium selenide telluride compound, an aluminum indium selenide telluride compound, etc. In this embodiment, taking the material of the phase change layer 110 as GST as an example, the GST material can realize a reversible transition between an amorphous state and a crystalline state. In the amorphous state, the GST material has a short-range atomic energy level and a low free electron density, so that it has a high resistivity; in the crystalline state, the GST material has a long-range atomic energy level and a high free electron density, so that it has a low resistivity. The memory uses the resistance difference between different phases of phase change materials to realize information storage. By applying different voltage or current pulse signals to the phase change layer, the phase change material undergoes a physical phase change, that is, a reversible phase change occurs between the crystalline state (low resistance state) and the amorphous state (high resistance state), thereby realizing the writing and erasing operations of information to store data.

[0048] Here, the gating layer 114 may include a threshold switch material, such as an Ovonic Threshold Switching (OTS) material. The OTS material may be a chalcogenide material, such as GeSeAs, GeTeAs, GeSeTeSe, GeSe, SeAs, GeTe, SiTe, etc. The bidirectional threshold switch uses an electrical signal to control the switch of the gating device. When the applied electrical signal is higher than the threshold voltage, the OTS material changes from a high resistance state to a low resistance state, and the OTS is in an on state; when the electrical signal is removed, the OTS material changes from a low resistance state to a high resistance state, and the OTS is in an off state. The gating layer 114 is used to control the current flowing through the phase change layer 110, and remains in an on state when the phase change layer 110 is erased and written, and remains in an off state after the erase and write operation is completed, so as to avoid read-write crosstalk between storage cells.

[0049] Here, the orthographic projection shape of the storage unit 102 on the XY plane can be a circle, a quadrilateral, or other shapes. Alternatively, the cross-sectional shape of the storage unit 102 perpendicular to the Z direction can be a circle, a quadrilateral, or other shapes. The present disclosure has no special limitation on the orthographic projection shape (or cross-sectional shape) of the storage unit 102.

[0050] In some embodiments, the memory 100 further includes: a plurality of first conductive structures 120 extending along a first direction (i.e., X direction) and coupled to the first electrode layer 108; a plurality of second conductive structures 122 extending along a second direction (i.e., Y direction) and coupled to the third electrode layer 116; wherein the storage unit 102 is disposed between the first conductive structure 120 and the second conductive structure 122, and the first dielectric layer 118 is respectively connected to the first conductive structure 120 and the second conductive structure 122.

[0051] Here, the memory 100 may include a plurality of memory cells 102, and the plurality of memory cells 102 may be arranged in an array along the X direction and the Y direction. The first conductive structure 120 extends along the X direction, and the plurality of first conductive structures 120 are arranged in parallel with each other. The first electrode layer 108 in the plurality of memory cells 102 arranged along the X direction may be coupled to the same first conductive structure 120. The second conductive structure 122 extends along the Y direction, and the plurality of second conductive structures 122 are arranged in parallel with each other. The third electrode layer 116 in the plurality of memory cells 102 arranged along the Y direction may be coupled to the same second conductive structure 122. Here, the first conductive structure 120 may extend along the X direction and be arranged in parallel with each other, and the second conductive structure 122 may extend along the Y direction and be arranged in parallel with each other. The memory cell 102 is arranged at the intersection between the first conductive structure 120 and the second conductive structure 122, and the first dielectric layer 118 is arranged on the sidewall of the memory cell 102, and the two ends of the first dielectric layer 118 arranged opposite to each other along the Z direction are in contact with the first conductive structure 120 and the second conductive structure 122, respectively.

[0052] Here, the first conductive structure 120 and the second conductive structure 122 may include a conductive material, for example, a metal material.

[0053] like Figure 3 As shown, in some embodiments, the first dielectric layer 118 has a first thermal conductivity along the Z direction, and the first dielectric layer 118 has a second thermal conductivity along any direction perpendicular to the Z direction, and the first thermal conductivity is greater than the second thermal conductivity.

[0054] Here, the first dielectric layer 118 may be disposed on the sidewall of the storage unit 102 , and the first dielectric layer 118 may surround the sidewall of the storage unit 102 . Figure 3 It is shown that the first dielectric layer 118 covers the side walls of the storage element 104 and the side walls of the selection element 106 in the storage unit 102, and the first dielectric layer 118 is in contact with the first electrode layer 108, the phase change layer 110, the second electrode layer 112, the selection layer 114 and the third electrode layer 116 stacked along the Z direction.

[0055] Here, the first dielectric layer 118 includes a two-dimensional material, and the two-dimensional material has anisotropic thermal conductivity. The first dielectric layer 118 has a first thermal conductivity along the Z direction, and the first thermal conductivity represents the rate at which heat in the storage unit 102 is conducted to the first conductive structure 120 and the second conductive structure 122 along the Z direction; the first dielectric layer 118 has a second thermal conductivity along any direction perpendicular to the Z direction, and the second thermal conductivity represents the rate at which heat in the storage unit 102 is conducted to adjacent storage units 102 along the X direction and the Y direction.

[0056] In the disclosed embodiment, the first dielectric layer has anisotropic thermal conductivity, and the first dielectric layer has a first thermal conductivity along the Z direction, so that the heat of the target storage unit in operation can be quickly transferred to the first conductive structure and the second conductive structure along the Z direction; the first dielectric layer has a second thermal conductivity along any direction perpendicular to the Z direction, so that the heat of the target storage unit is difficult to be transferred to the adjacent storage unit along the X direction and the Y direction. Therefore, the target storage unit in operation can maintain a certain temperature, increase the RESET volume fraction of the memory, and help distinguish the SET state from the RESET state; and the heat of the target storage unit in operation is not easy to diffuse to the adjacent storage unit, causing the phase change layer in the adjacent storage unit to undergo a crystalline-amorphous inversion, which helps to improve write errors and improve the reliability of the memory.

[0057] In some embodiments, the first dielectric layer 118 includes a multi-layer structure, where atoms in the same layer are connected by chemical bonds (e.g., covalent bonds), and atoms in different layers are connected by van der Waals forces; wherein the rate at which heat is conducted along atoms in the same layer is greater than the rate at which heat is conducted along atoms in different layers.

[0058] In some embodiments, the first dielectric layer 118 includes at least one of hexagonal boron nitride (BN), two-dimensional aluminum nitride (AlN), two-dimensional gallium nitride (GaN), two-dimensional tungsten sulfide (WS2), and two-dimensional molybdenum sulfide (MoS2).

[0059] Here, the first dielectric layer 118 includes a two-dimensional layered material. The microstructure of the first dielectric layer 118 is described below by taking the first dielectric layer 118 including hexagonal boron nitride as an example.

[0060] refer to Figure 4A , Figure 4A The schematic diagram of the structure of hexagonal boron nitride provided in the embodiment of the present disclosure is shown in FIG. Figure 4A As shown, hexagonal boron nitride has a layered structure, and the boron atoms and nitrogen atoms in the same layer are connected by covalent bonds ( Figure 4A The covalent bond has a larger bond energy and is more stable. The atoms in different layers are bound by van der Waals forces ( Figure 4AThe first thermal conductivity is the rate at which heat is conducted along atoms in the same layer, and the second thermal conductivity is the rate at which heat is conducted along atoms in different layers. Here, the direction in which heat is conducted along atoms in the same layer is referred to as the in-plane direction, and the direction in which heat is conducted along atoms in different layers is referred to as the out-of-plane direction.

[0061] In addition, reference Figure 4B and Figure 4C , Figure 4B A schematic diagram of the structure of aluminum nitride provided in an embodiment of the present disclosure, Figure 4C A schematic diagram of the structure of tungsten sulfide provided in an embodiment of the present disclosure. Two-dimensional aluminum nitride and tungsten sulfide also have similar structures and can have anisotropic thermal conductivity.

[0062] refer to Figure 5 , Figure 5 The following is a diagram of various property parameters of hexagonal boron nitride provided in the embodiment of the present disclosure. Figure 5 As shown, there is a significant difference in the thermal conductivity of hexagonal boron nitride in the in-plane direction and out-of-plane direction, that is, it has a higher in-plane thermal conductivity and a lower out-of-plane thermal conductivity, which helps to quickly conduct heat in the in-plane direction. Hexagonal boron nitride has a large resistivity, which can prevent the current from being conducted along the first dielectric layer formed by hexagonal boron nitride during the SET process and the RESET process, causing erroneous operation. The first dielectric layer formed by hexagonal boron nitride has good oxidation resistance and stability, which can prevent the performance of the memory from changing due to oxidation and other reasons during the manufacturing process of the semiconductor and the later use process, resulting in reduced reliability and life of the memory.

[0063] like Figure 3 As shown, in some embodiments, the thickness of the first dielectric layer 118 is less than 10 nm. Here, the thickness of the first dielectric layer 118 refers to the dimension of the first dielectric layer 118 along the X direction or the Y direction perpendicular to the Z direction.

[0064] In some embodiments, the memory 100 further includes: a second dielectric layer disposed between the sidewall of the storage unit and the first dielectric layer; and / or a third dielectric layer disposed on the sidewall of the storage unit and the first dielectric layer disposed between the sidewall of the storage unit and the third dielectric layer.

[0065] Here, the memory 100 may include: a second dielectric layer disposed between the sidewall of the memory cell 102 and the first dielectric layer 118. The second dielectric layer contacts the sidewall of the memory cell 102, so that the second dielectric layer covers the sidewall of the memory element 104 and the sidewall of the gating element 106 in the memory cell 102, and the first dielectric layer 118 covers the second dielectric layer. The first dielectric layer 118 includes a two-dimensional material having anisotropic thermal conductivity, and the second dielectric layer may include a material having isotropic thermal conductivity.

[0066] In the disclosed embodiment, the second dielectric layer is in direct contact with the side wall of the storage unit. The second dielectric layer may have good anti-oxidation properties, for example, to prevent oxidation of the phase change layer and the selection layer in the storage unit; and may also protect the outer side wall of the storage unit to avoid damage to the storage unit by external factors.

[0067] Here, the memory 100 may include: a first dielectric layer 118 disposed between the sidewall of the memory cell 102 and the third dielectric layer. The first dielectric layer 118 contacts the sidewall of the memory cell 102, so that the first dielectric layer 118 covers the sidewall of the memory element 104 and the sidewall of the gating element 106 in the memory cell 102, and the third dielectric layer covers the first dielectric layer. The first dielectric layer 118 includes a two-dimensional material having anisotropic thermal conductivity, and the third dielectric layer may include a material having isotropic thermal conductivity.

[0068] In the embodiment of the present disclosure, the third dielectric layer may, for example, have good hardness and strength, and can effectively prevent damage to the storage unit by subsequent etching and other processes. The third dielectric layer may also, for example, have good anti-oxidation properties, and further protect the outer sidewall of the storage unit. Both the second dielectric layer and the third dielectric layer can be used as a barrier layer disposed on the outer sidewall of the storage unit to protect the storage unit. The present disclosure does not specifically limit the specific material types of the second dielectric layer and the third dielectric layer.

[0069] Here, the side wall of the storage unit 102 can be provided with a single-layer dielectric layer or a multi-layer dielectric layer. The single-layer dielectric layer can be a first dielectric layer, and the first dielectric layer includes a two-dimensional material with anisotropic thermal conductivity; the multi-layer dielectric layer can include a first dielectric layer and other dielectric layers, and the first dielectric layer includes a two-dimensional material with anisotropic thermal conductivity, and the other dielectric layers include materials with isotropic thermal conductivity.

[0070] refer to Figure 6 , Figure 6 Schematic diagram of a memory provided by some other embodiments of the present disclosure. Figure 6As shown, the memory 200 includes: a plurality of first storage units 202 arranged in an array along the X direction and the Y direction, and the first storage unit 202 may include a first end and a second end arranged opposite to each other along the Z direction; a plurality of first conductive structures 206 extending along the X direction, and the first ends of the plurality of first storage units 202 arranged along the X direction are coupled to the same first conductive structure 206; a second conductive structure 208 extending along the Y direction, and the second ends of the plurality of first storage units 202 arranged along the Y direction are coupled to the same second conductive structure 208; A plurality of second storage units 204 are arranged in an array, and the second storage units 204 may include a third end and a fourth end arranged opposite to each other along the Z direction; a plurality of third conductive structures 210 extend along the Y direction, and the third ends of the plurality of second storage units 204 arranged along the Y direction are coupled to the same third conductive structure 210; a fourth conductive structure 212 extends along the X direction, and the fourth ends of the plurality of second storage units 204 arranged along the X direction are coupled to the same fourth conductive structure 212; wherein the second conductive structures 208 and the third conductive structures 210 are connected one-to-one.

[0071] Here, the memory 200 may include a first memory cell 202 and a second memory cell 204 stacked in the Z direction. The first conductive structure 206 may be referred to as a top bit line, the second conductive structure 208 may be referred to as a top word line, the third conductive structure 210 may be referred to as a bottom word line, and the fourth conductive structure 212 may be referred to as a bottom bit line.

[0072] Here, the sidewalls of the first storage unit 202 and the second storage unit 204 may be provided with a two-dimensional material having anisotropic thermal conductivity as the first dielectric layer. The first dielectric layer covering the first storage unit 202 and the second storage unit 204 may refer to Figure 3 The relevant description will not be repeated here.

[0073] refer to Figure 7 , Figure 7 A block diagram of a memory system provided by an embodiment of the present disclosure. Figure 7 As shown, an embodiment of the present disclosure provides a memory system, which includes: the memory 100 (or, the memory 200) as in the above technical solution; and a controller 302 coupled to the memory 100 and configured to control the memory 100.

[0074] refer to Figure 8 , Figure 8 A schematic flow chart of a method for manufacturing a memory provided in an embodiment of the present disclosure.

[0075] like Figure 8 As shown, the present disclosure provides a method for manufacturing a memory, the method comprising:

[0076] Step S810: forming a memory cell, wherein the memory cell includes a stacked memory element and a gating element;

[0077] Step S820: forming a first dielectric layer on the sidewall of the storage unit, the first dielectric layer covering the sidewall of the storage element and the sidewall of the gating element in the storage unit; wherein the first dielectric layer comprises a two-dimensional material, and the two-dimensional material has anisotropic thermal conductivity.

[0078] Exemplarily, forming a memory cell may include the following steps: forming a stacked structure, the stacked structure including a first electrode material layer, a phase change material layer, a second electrode material layer, a gating material layer and a third electrode material layer stacked in sequence; etching along the Z direction to form a first groove extending along the X direction and a second groove extending along the Y direction, the first groove and the second groove divide the stacked structure into a plurality of memory cells, and the plurality of memory cells are arranged in an array along the X direction and the Y direction. Among them, the etched first electrode material layer, the second electrode material layer and the third electrode material layer respectively form the first electrode layer, the second electrode layer and the third electrode layer, the etched phase change material layer forms the phase change layer, and the etched gating material layer forms the gating layer. The first electrode layer, the phase change layer and the second electrode layer together form a memory element, and the second electrode layer, the gating layer and the third electrode layer together form a gating element.

[0079] Here, a first dielectric layer is formed on the side wall of the storage unit. The first dielectric layer includes a two-dimensional material with anisotropic thermal conductivity. The in-plane direction of the two-dimensional material is the Z direction, which has a higher thermal conductivity; the out-of-plane direction of the two-dimensional material is the arrangement direction of the storage unit, that is, the X direction and the Y direction, which has a lower thermal conductivity.

[0080] Here, the process of forming the first dielectric layer may include but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), ion beam assisted-pulsed laser deposition (IA-PLD), ion beam deposition (IBD) or any combination thereof.

[0081] Illustratively, manufacturing the first dielectric layer of hexagonal boron nitride using a CVD process may include: introducing gaseous raw materials containing boron (B) and nitrogen (N) into a reaction chamber through a carrier gas, and chemically reacting the gaseous raw materials at high temperature to generate BN, wherein the boron source generally uses boron-containing compounds such as boron trifluoride (BF3), boron trichloride (BCl3), boron tribromide (BBr3) or diborane (B2H6), and the nitrogen source is generally ammonia (NH3) or nitrogen (N2).

[0082] Exemplarily, manufacturing the first dielectric layer of hexagonal boron nitride by using a PVD process may include: using a BN target and performing sputtering in a N2 atmosphere.

[0083] The embodiments of the present disclosure provide a memory and a manufacturing method thereof, and a memory system. The memory includes: a memory unit, including a stacked memory element and a gating element; a first dielectric layer provided on the side wall of the memory unit, the first dielectric layer covering the side wall of the memory element and the side wall of the gating element in the memory unit; wherein the first dielectric layer includes a two-dimensional material, and the two-dimensional material has anisotropic thermal conductivity. In the embodiments of the present disclosure, the first dielectric layer formed by the two-dimensional material covers the side wall of the memory unit, and the two-dimensional material has anisotropic thermal conductivity. On the one hand, the target memory unit in the operating state can maintain a certain temperature, increase the RESET volume fraction of the memory, and help distinguish the SET state from the RESET state; on the other hand, the heat of the target memory unit in the operating state is not easy to diffuse to the adjacent memory unit, resulting in the crystalline-amorphous state inversion of the memory element in the adjacent memory unit, which helps to improve write errors and improve the reliability of the memory.

[0084] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0085] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory, characterized in that: The memory comprises: A storage unit, comprising a storage element and a gating element arranged in a stacked manner; A first dielectric layer is arranged on the side wall of the storage unit, and the first dielectric layer covers the side wall of the storage element and the side wall of the gating element in the storage unit; wherein the first dielectric layer includes a two-dimensional material, and the two-dimensional material has anisotropic thermal conductivity.

2. The memory according to claim 1, characterized in that: The first medium layer has a first thermal conductivity along a stacking direction, and the first medium layer has a second thermal conductivity along any direction perpendicular to the stacking direction, and the first thermal conductivity is greater than the second thermal conductivity.

3. The memory according to claim 1 or 2, characterized in that: The first dielectric layer includes a multilayer structure, atoms in the same layer are connected by chemical bonds, and atoms in different layers are connected by van der Waals forces; wherein the rate at which heat is conducted along atoms in the same layer is greater than the rate at which heat is conducted along atoms in different layers.

4. The memory according to claim 3, characterized in that: The first dielectric layer includes at least one of hexagonal boron nitride, two-dimensional aluminum nitride, two-dimensional gallium nitride, two-dimensional tungsten sulfide and two-dimensional molybdenum sulfide.

5. The memory according to claim 1, characterized in that: The thickness of the first dielectric layer is less than 10 nm.

6. The memory according to claim 1, characterized in that: The memory also includes: A second dielectric layer is provided between the side wall of the storage unit and the first dielectric layer; and / or, The third dielectric layer is disposed on the side wall of the storage unit and the first dielectric layer is disposed between the side wall of the storage unit and the third dielectric layer.

7. The memory according to claim 1, characterized in that: The storage unit includes a first electrode layer, a phase change layer, a second electrode layer, a gating layer and a third electrode layer which are stacked; wherein the first electrode layer, the phase change layer and the second electrode layer together form the storage element, and the second electrode layer, the gating layer and the third electrode layer together form the gating element.

8. The memory according to claim 7, characterized in that: The memory also includes: A plurality of first conductive structures extending along a first direction and coupled to the first electrode layer; A plurality of second conductive structures extending along a second direction and coupled to the third electrode layer; wherein the storage unit is arranged between the first conductive structure and the second conductive structure, and the first dielectric layer is connected to the first conductive structure and the second conductive structure respectively.

9. A memory system, characterized in that: The memory system comprises: The memory as claimed in any one of claims 1 to 8; and A controller coupled to the memory and configured to control the memory.

10. A method for manufacturing a memory, characterized in that: The method comprises: forming a memory cell, the memory cell comprising a memory element and a gating element arranged in a stacked manner; A first dielectric layer is formed on the sidewall of the storage unit, and the first dielectric layer covers the sidewall of the storage element and the sidewall of the gating element in the storage unit; wherein the first dielectric layer includes a two-dimensional material, and the two-dimensional material has anisotropic thermal conductivity.

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