SiC power MOSFET device and manufacturing method

Abstract

The invention relates to the technical field of power semiconductor devices, in particular to a SiC power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof, and the cellular structure of the device sequentially comprises a substrate, an N-epitaxial layer, a polysilicon gate layer, an isolation layer and a metal layer from bottom to top; two bilaterally symmetrical Pwell layers are arranged in the surface of the N-epitaxial layer; the N + layer is arranged on the Pwell layer; the P + layer is arranged on the N + layer; the surface of the N-epitaxial layer is internally provided with an alternating structure of a cross section A and a cross section B; the structure of the section A is as follows: the boundaries of the opposite sides of the two pwell layers are in the shapes of arcs bent inwards and straight bottom edge boundaries connected with the arcs; the structure of the section B is as follows: the boundaries of the two pwell layers are arc-shaped which are bent inwards; groove structures are arranged on the two sides of the cellular structure. The invention has a double-section alternating structure, can shorten the path of hole current passing through the lower part of the source region, and improves the dynamic latch-up resistance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a SiC power MOSFET device and a manufacturing method thereof. Background Art

[0002] In order to further improve the performance of devices under high voltage and high power and break the theoretical limitations of silicon materials, the third-generation semiconductor materials represented by silicon carbide (SiC) and gallium nitride (GaN) have attracted widespread attention. They can achieve good device performance over a wide temperature range and are considered to be an ideal choice to replace existing silicon materials in the field of power devices. SiC is a group IV-IV compound semiconductor material with a breakdown electric field ten times that of Si material and a thermal conductivity almost three times that of Si material. Wider band gaps, higher thermal conductivity, and larger critical breakdown electric fields allow SiC power devices to operate in higher temperature environments and achieve higher current density and blocking voltage. High saturation drift velocity and mobility can increase the switching frequency of the device.

[0003] Silicon carbide (SiC) power devices include diodes, junction field effect transistors (JFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), etc. SiC power MOSFET devices have attracted widespread attention due to their high voltage blocking capability, high temperature working capability, and low on-resistance. The technical challenges that such devices may face include improving device reliability and stability, reducing manufacturing costs, and optimizing device performance.

[0004] Dynamic latch-up is a failure mode in SiC MOSFET power semiconductor devices, which usually occurs during the device shutdown process. When the device attempts to shut down, if the parasitic NPN transistor (formed by the source region, drain region and substrate of the MOSFET) is accidentally turned on, current will continue to flow, making the device unable to shut down successfully. In order to increase the device (the cell structure of the SiC MOSFET power semiconductor device in the prior art is as follows Figure 1As shown in the figure, 200-epitaxial layer, 300-Pwell layer, 400-N+ layer, 600-polysilicon gate layer, 700-isolation layer; the dotted arrow indicates the flow path of the hole current) is used to reduce the lateral resistance during the shutdown process by injecting concentrated boron under the source region (lateral resistance refers to the resistance encountered when the current flows laterally between the source region and the drain region of the device. By injecting concentrated boron under the source region, the resistance of this region can be reduced, so that during the shutdown process, the resistance encountered by the hole current provided by the p-type region flowing through this region is reduced) to prevent the hole current from flowing through the lateral resistance and generating a voltage drop (or potential difference) higher than the NPN parasitic transistor conduction. When the device is turned off, if the lateral resistance is high, the hole current flowing through the resistance will generate a large voltage drop. That is to say, if this voltage drop is large enough, it may exceed the turn-on voltage of the parasitic NPN transistor, causing the transistor to turn on, thereby triggering dynamic latching. Therefore, by reducing the lateral resistance, this voltage drop can be reduced, the parasitic transistor is prevented from turning on, and the device's ability to resist dynamic latching can be improved. However, the injected concentrated boron will diffuse into the channel region of the power semiconductor device when activated, resulting in an increase in the voltage value of the device. In addition, since the hole current has a long path under the N+ layer, the existing structure has limited ability to improve the resistance to dynamic latching. Summary of the invention

[0005] In order to further improve the technical problem of the dynamic latch resistance of SiC MOSFET power semiconductor devices, a SiC power MOSFET device and a manufacturing method are provided. The device structure of the present invention has a double cross-section alternating structure, which can shorten the path of hole current passing through the bottom of the source region and improve the dynamic latch resistance of the device.

[0006] In order to achieve the above objectives, the present invention is implemented by the following technical solutions:

[0007] A SiC power MOSFET device, the cell structure of which includes, from bottom to top, an N++ type SiC substrate, an N-epitaxial layer, a polysilicon gate layer, an isolation layer, and a metal layer;

[0008] Two left-right symmetrical Pwell layers are arranged on the surface of the N-epitaxial layer, and a JFET region is formed between the two Pwell layers; an N+ layer is arranged on the Pwell layer, and a P+ layer is arranged on the N+ layer;

[0009] The surface of the N-epitaxial layer has an alternating structure of cross sections A and B;

[0010] The structure of the cross section A: the cross section of the JFET region is a trapezoidal shape that is narrow at the top and wide at the bottom, and the two opposite side boundaries of the two pwell layers are both in an arc shape that bends inward, and have a straight bottom edge boundary connected to the arc;

[0011] The structure of the cross section B: the boundaries of the two pwell layers are both in an arc shape that bends inwards;

[0012] Both sides of the cellular structure have groove structures.

[0013] Further, in the structure of the cross section A: the Pwell layer wraps the N+ layer and the P+ layer, and the boundary between the P+ layer and the N+ layer forms two stacked squares;

[0014] In the structure of the cross section B: the Pwell layer wraps the N+ layer and the P+ layer inside, the boundary of the P+ layer and the boundary of the N+ layer are arc-shaped, and the arc-shaped boundary of the N+ layer wraps the arc-shaped boundary of the P+ layer inside.

[0015] Further, in the cross section A and the cross section B, the depth of the Pwell layer>the depth of the N+ layer>the depth of the P+ layer;

[0016] The depth of the Pwell layer in the section A is the same as that in the section B, and the depth of the Pwell layer is 0.5 μm-1.5 μm;

[0017] The depth of the N+ layer in the section A is the same as that in the section B, and the depth of the N+ layer is 0.3 μm-0.8 μm;

[0018] The depth of the P+ layer in the section A is the same as that in the section B, and the depth of the P+ layer is 0.1 μm-0.3 μm.

[0019] Furthermore, the concentration of aluminum ions injected into the Pwell layer is 1×10 17 -1×10 19 cm -3 The nitrogen ion concentration injected into the N+ layer is 1×10 18 -1×10 20 cm -3 The aluminum ion concentration injected into the P+ layer is 1×10 18 -1×10 20 cm -3 .

[0020] Furthermore, the depth of the trench structure exceeds the depth of the P+ layer and reaches or exceeds the depth of the N+ layer, and does not exceed the depth of the Pwell layer.

[0021] Furthermore, the depth of the groove structure is 0.1 μm-0.5 μm, and a metal layer is provided in the groove structure.

[0022] Furthermore, the thickness of the N-epitaxial layer is 5 μm-20 μm, and the ion concentration is 10 13 -10 17 cm -3 ;

[0023] The thickness of the polysilicon gate layer on the surface of the N-epitaxial layer ranges from

[0024] The isolation layer completely covers the polysilicon gate layer;

[0025] The metal layer covers the cellular structure;

[0026] A drain electrode is also included under the N++ type SiC substrate.

[0027] The above method for preparing a SiC power MOSFET device comprises the following steps:

[0028] S1, growing an N-epitaxial layer of a desired thickness on an N++ type SiC substrate;

[0029] S2, photolithographically defining a barrier layer region on the N-epitaxial layer to form a first mask, and removing an undefined barrier layer region by etching to obtain a barrier layer region having a trapezoidal cross-sectional configuration that is narrow at the top and wide at the bottom, without removing the first mask;

[0030] S3, photolithography is performed to define through-regions on both sides of the barrier layer region with a trapezoidal cross-sectional configuration, forming a second mask, removing the defined through-regions by etching, and vertically etching the two sides of the trapezoidal cross-sectional configuration with a partial slope of the same width and length at the same interval, and the partial slope is the defined through-region; removing the second mask; due to the etching of the partial slopes of the two sides of the waist, a substrate with alternating cross-sections A and B is formed;

[0031] S4, since the first mask is not removed in S2, it can be used as a mask for ion implantation, and aluminum ions are implanted to a desired depth to form a Pwell layer; nitrogen ions are then implanted into the Pwell region to a desired depth to form an N+ layer; finally, aluminum ions are implanted into the N+ layer to a desired depth to form a P+ layer; since there is a through region in the barrier layer region, the structure of the boundary cross section formed by each ion layer is different during ion implantation, and after removing the first mask, the barrier layer region is etched away to the N-epitaxial layer, thereby obtaining an alternating structure with cross section A and cross section B in the N-epitaxial layer;

[0032] S5, sequentially forming a polysilicon gate layer and an isolation layer wrapping the polysilicon gate layer on the surface of the N-epitaxial layer in the JFET region;

[0033] S6, etching of active area trench structure;

[0034] S7. The entire metal layer is deposited, and the active metal region and the gate metal region are defined by photolithography. After etching, the active region electrode and the gate electrode are formed respectively to obtain a SiC power MOSFET device.

[0035] Furthermore, the height of the barrier layer region is The mesa width of the barrier layer region is The angle formed by the lower base and waist of the trapezoid ranges from 15° to 60°; the spacing between two adjacent barrier layer regions is

[0036] Furthermore, when etching the through region, the width of the waists on both sides etched away is 0.1-0.5 μm (i.e., the same width), and the same spacing between the waists on both sides is retained at 0.5-1.5 μm;

[0037] The angle of ion implantation is 0°, that is, the ions are implanted vertically into the material surface.

[0038] Furthermore, in S2, wet etching is used to remove the undefined barrier layer area, and the etching solution used in the wet etching is 30% to 40% by mass of NH 4 The F solution and the HF solution with a mass fraction of 40% to 50% are mixed at a volume ratio of 0-8:1, so that the ratio of the vertical etching rate to the horizontal etching rate is in the range of 1:0.55-3.8, and a barrier layer region with a cross-sectional configuration of a narrow upper part and a wide lower part and a trapezoidal bottom angle range of 15°-60° is realized. By optimizing and adjusting the above parameters, the lateral etching rate and the longitudinal etching rate are different during wet etching, forming a slope with a certain inclination angle.

[0039] Further, in S3, plasma dry etching is used to generate interval etching on the slopes of the waists on both sides of the barrier layer region to remove the defined through-region; the gas used to generate the plasma is CF 4 , CHF 3 , C 2 F 4 , SF 4 NF 3 , SF 6 , chlorine, hydrogen bromide, and by optimizing and adjusting the gas flow rate, etching parameters such as gas pressure, RF power and other conditions, these gases attack the side wall surface to form a passivation layer to protect the side from further etching, thereby forming anisotropically etched side wall shapes. The side wall protection mechanism ensures that the etching rate in the vertical direction is higher than the etching rate in the horizontal direction, thereby forming a substrate structure in which cross sections A and cross sections B alternate; the substrate structure of cross section A is a cross-sectional structure with a side wall slope of 80°-90°, and the substrate structure of cross section B is the same as the cross-sectional structure of the barrier layer region.

[0040] Beneficial technical effects:

[0041] The present invention designs a barrier layer with spaced transverse strip slopes on the epitaxial layer, and has two different cross-sections. Due to the simultaneous existence of the two different cross-sections, two structures of Pwell layer and N+ layer and P+ layer are formed on the two cross-sections by injecting different energies; these two simultaneously existing different cross-sectional structures can reduce the path of hole current under the N+ layer, so that most of the hole current flows through the path on the N+ layer, thereby greatly increasing the anti-latch capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is the flow path of the hole current in the cross-sectional view of the planar SiC MOSFET in the prior art;

[0043] Figure 2 The top view and cross-sectional view of the barrier layer region defined by photolithography on the surface of the N-epitaxial layer after the S2 step; Ⅰ is the top view structure, and Ⅱ is the cross-sectional structure;

[0044] Figure 3 is a schematic diagram of a top view structure of a substrate having alternating cross sections A and B formed after step S3;

[0045] Figure 4 Schematic diagram of the cross-sectional structure of the substrate of section A and the schematic diagram of the cross-sectional structure of the substrate of section B formed after step S3;

[0046] Figure 5 is a schematic diagram of the substrate structure of section A formed after step S4;

[0047] Figure 6 is a schematic diagram of the substrate structure of the cross section B formed after step S4;

[0048] Figure 7 Schematic diagram of the structure of the cross section A of the cell structure of the SiC power MOSFET device of the present invention;

[0049] Figure 8 Schematic diagram of the structure of the cross section B of the cell structure of the SiC power MOSFET device of the present invention;

[0050] 1-N++ type SiC substrate, 2-N-epitaxial layer, 3-Pwell layer, 4-N+ ​​layer, 5-P+ layer, 6-polysilicon gate layer, 7-isolation layer, 8-metal layer, 9-trench structure; 21-barrier layer region, 22-through region. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present invention will be described clearly and completely below in combination with the embodiments of the present invention and the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. All other embodiments obtained by ordinary technicians in this field without creative work based on the embodiments of the present invention are within the scope of protection of the present invention.

[0052] Unless otherwise specifically stated, the numerical value set forth in these embodiments does not limit the scope of the present invention. The technology and method known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology and method should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values.

[0053] In addition, it should be noted that the use of terms such as "first" and "second" to limit masks, etc. is only to facilitate the distinction between the substances used in each step. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0054] The experimental methods in the following examples without specifying specific conditions are usually measured in accordance with national standards; if there is no corresponding national standard, the method is carried out in accordance with the general standard requirements or general methods.

[0055] Example 1

[0056] A SiC power MOSFET device, the cell structure of the device is as follows Figure 7 and Figure 8 As shown, the following are arranged from bottom to top: a drain electrode (not shown in the figure), an N++ type SiC substrate 1, an N-epitaxial layer 2, a polysilicon gate layer 6, an isolation layer 7, and a metal layer 8;

[0057] Two bilaterally symmetrical Pwell layers 3 are arranged on the surface of the N- epitaxial layer 2, and a JFET region is formed between the two Pwell layers 3; an N+ layer 4 is arranged on the Pwell layer 3, and a P+ layer 5 is arranged on the N+ layer 4;

[0058] The surface of the N-epitaxial layer 2 has an alternating structure of cross sections A and B;

[0059] The structure of the cross section A is as follows Figure 7As shown: the cross section of the JFET region is a trapezoid that is narrow at the top and wide at the bottom, and the two opposite side boundaries of the pwell layers 3 are both arc-shaped and curved inward, and have a straight bottom edge boundary connected to the arc; the Pwell layer 3 wraps the N+ layer 4 and the P+ layer 5, and the boundary between the P+ layer 5 and the N+ layer 4 forms two stacked squares;

[0060] The structure of the cross section B is as follows Figure 8 As shown: the boundaries of the two pwell layers 3 are both in an arc shape that bends inward; the Pwell layer 3 wraps the N+ layer 4 and the P+ layer 5 inside, the boundary of the P+ layer 5 and the boundary of the N+ layer 4 are arc-shaped, and the arc-shaped boundary of the N+ layer 4 wraps the arc-shaped boundary of the P+ layer 5 inside;

[0061] The two sides of the cell structure are provided with groove structures 9, in which a metal layer 8 is deposited;

[0062] Wherein, the depth of the Pwell layer 3 is greater than the depth of the N+ layer 4 and greater than the depth of the P+ layer 5;

[0063] The depth of the Pwell layer 3 is 0.8 μm-1.5 μm, and the concentration of aluminum ions injected into the Pwell layer 3 is 1×10 17 -1×10 19 cm -3 ;

[0064] The depth of the N+ layer 4 is 0.4 μm-0.7 μm, and the concentration of nitrogen ions injected into the N+ layer 4 is 1×10 18 -1×10 20 cm -3 ;

[0065] The depth of the P+ layer 5 is 0.1 μm-0.3 μm, and the concentration of aluminum ions injected into the P+ layer 5 is 1×10 18 -1×10 20 cm -3 ;

[0066] The depth of the groove structure 9 exceeds the depth of the P+ layer 5 and reaches the depth of the N+ layer 4, and the depth of the groove structure 9 is 0.1-0.5 μm;

[0067] The thickness of the N-epitaxial layer 2 is 5 μm-20 μm, and the ion concentration range is 10 13 -10 17 The thickness of the polysilicon gate layer 6 on the surface of the N-epitaxial layer 2 is The isolation layer 7 completely covers the polysilicon gate layer 6 ; the metal layer 8 covers the cellular structure.

[0068] Example 2

[0069] The method for preparing a SiC power MOSFET device having an alternating structure of cross section A and cross section B in the above embodiment 1 comprises the following steps:

[0070] S1. growing an N-epitaxial layer 2 on an N++ type SiC substrate 1; the N-epitaxial layer 2 is usually prepared by CVD method, and the thickness is controlled by controlling CVD parameters such as temperature, pressure, time, etc., and the thickness is usually between 5 and 20 microns. The thickness range is to meet the needs of different semiconductor devices and ensure that the epitaxial layer can provide sufficient physical and electrical performance support;

[0071] S2, according to Figure 2 The top view structure shown ( Figure 2 Figure Ⅰ) and cross-sectional structure ( Figure 2 Ⅱ), a barrier layer region 21 is defined on the N-epitaxial layer 2 by photolithography, a first mask (usually a photoresist) is formed by conventional methods, and the undefined barrier layer region 21 is removed by wet etching, that is, a barrier layer region having a cross-sectional configuration of being narrow at the top and wide at the bottom is obtained, and the first mask is not removed;

[0072] By controlling the drying temperature (20°C-100°C) and drying time (10 seconds-10 minutes) of the first mask, and controlling the etching time (10 seconds-5 minutes), the etching solution used is 30%-40% NH 4 F solution and HF solution with a mass fraction of 40% to 50%, and the volume ratio of the two is controlled to be 6:1, so that the ratio of the vertical etching rate to the horizontal etching rate is in the range of 1:0.55-3.8, and the cross-sectional configuration is a trapezoidal barrier layer region 21 with a narrow upper and wide lower surface and a bottom inner angle range of 15°-60°;

[0073] The obtained height of the barrier layer region 21 is The mesa width of the barrier layer region 21 is The angle formed by the lower base and the waist of the trapezoid is in the range of 30°-60°; the spacing between two adjacent barrier layer regions 21 is

[0074] S3. According to Figure 3-Figure 4 The top view structure and cross-sectional structure of the present invention are as follows: a through-region 22 is defined by photolithography on both sides of the barrier layer region 21 having a trapezoidal cross-sectional configuration; a second mask is formed by conventional methods; the defined through-region 22 is removed by dry etching; and a portion of the slope having the same width and length is vertically etched from both sides of the trapezoidal cross-sectional waist at the same interval; the portion of the slope is the defined through-region 22;

[0075] When etching the through region 22, the same width of the waists etched away on both sides is 0.2μm-0.5μm, and the same spacing between the waists on both sides is 0.8μm-1.2μm; the second mask is removed by conventional methods;

[0076] Due to the etching of the partial slope of the waist on both sides, a base with alternating sections A and B is formed;

[0077] Plasma dry etching is used to generate interval etching on the slopes of the waists on both sides of the barrier layer region 21 to remove the defined through-region 22; the gas used to generate the plasma is CF 4 , CHF 3 , C 2 F 4 , SF 4 NF 3 , SF 6 , chlorine, hydrogen bromide, etc., by optimizing and adjusting the gas flow rate, etching parameters such as gas pressure, RF power and other conditions, these gases attack the side wall surface to form a passivation layer to protect the side from further etching, thereby forming anisotropically etched side wall shapes. The side wall protection mechanism ensures that the etching rate in the vertical direction is higher than the etching rate in the horizontal direction, thereby forming a substrate structure with alternating cross sections A and B;

[0078] The base structure of section A is a cross-sectional structure with a sidewall slope of 80°-90°, and the base structure of section B is the same as the cross-sectional structure of the barrier layer region, as shown in FIG. Figure 3 and Figure 4 As shown;

[0079] S4, since the first mask is not removed in S2, it can be used as a mask for ion implantation, and aluminum ions are implanted to form Pwell layer 3 (the angle of ion implantation is 0°, and after multiple implantations with different energies and different doses, a depth of 0.8μm-1.5μm and a concentration of 1×10 17 -1×10 19 cm -3 Pwell layer 3);

[0080] Then, nitrogen ions are injected into the Pwell region 3 to form an N+ layer 4 (the angle of ion injection is 0°, and after multiple injections with different energies and different doses, a layer with a depth of 0.4 μm to 0.7 μm and a concentration of 1×10 18 -1×10 20 cm -3 N+ layer 4);

[0081] Finally, aluminum ions are injected into the N+ layer 4 to form the P+ layer 5 (the angle of ion injection is 0°, and after multiple injections with different energies and different doses, a depth of 0.1μm-0.3μm and a concentration of 1×10 18 -1×10 20 cm -3 P+ layer 5);

[0082] Since the barrier layer region 21 has a penetration region 22, when ions are implanted, the structures of the boundary cross sections formed by each ion layer are different due to different depths and concentrations. After removing the first mask, the barrier layer region is etched away to the N-epitaxial layer, thereby obtaining an alternating structure of cross sections A and B in the surface of the N-epitaxial layer 2. The result is as follows: Figure 5 The cross-sectional structure A and Figure 6 The cross-sectional structure B is shown;

[0083] S5, grow a layer of N-epitaxial layer 2 on the JFET region by thermal oxidation. A silicon dioxide layer is formed to form a gate oxide, and then polysilicon is deposited on the gate oxide by PECVD to form a polysilicon gate layer 6;

[0084] Photolithography defines different areas of the polysilicon gate layer and etches away unnecessary polysilicon;

[0085] An insulating dielectric layer is deposited on the surface to serve as electrical isolation between polysilicon and metal. This insulating dielectric layer is the isolation layer 7.

[0086] S6, photolithography defines the hole layer in the active area and the hole layers on different polysilicon gate layers, and etches a trench structure 9 with a depth of 0.1-0.5 μm, wherein the depth of the trench structure exceeds the P+ layer 5 and reaches the N+ layer 4;

[0087] S7, depositing a layer of metal on the overall cellular structure to obtain a metal layer 8 (cross-sectional structure as shown in FIG. Figure 7 and Figure 8 As shown), the active metal region and the gate metal region are defined by photolithography, and the active region electrode and the gate electrode (not shown) are formed respectively after etching to obtain a SiC power MOSFET device.

[0088] The alternate transverse strip-shaped slope barrier layer was designed, and the alternating structure of the alternate section A and section B was formed by different injection energies. The hole current of the section A structure ( Figure 7 The middle dotted line shows the hole current) flows laterally to the P+ layer 5 on the N+ layer 4 in the cross-section B structure, reducing the hole current path under the N+ layer 4. Most of the hole current flows through the path on the N+ layer 4, thereby greatly increasing the device's anti-latch capability.

[0089] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A SiC power MOSFET device, characterized in that: The cell structure of the device includes, from bottom to top, an N++ type SiC substrate (1), an N-epitaxial layer (2), a polysilicon gate layer (6), an isolation layer (7), and a metal layer (8); Two bilaterally symmetrical Pwell layers (3) are arranged on the surface of the N-epitaxial layer (2), and a JFET region is formed between the two Pwell layers (3); an N+ layer (4) is arranged on the Pwell layer (3), and a P+ layer (5) is arranged on the N+ layer (4); The surface of the N-epitaxial layer (2) has an alternating structure of cross sections A and cross sections B; The structure of the cross section A: the cross section of the JFET region is a trapezoidal shape that is narrow at the top and wide at the bottom, and the two opposite side boundaries of the two pwell layers (3) are both in the shape of an arc that bends inwards, and have a straight bottom edge boundary connected to the arc; The structure of the cross section B: the boundaries of the two pwell layers (3) are both in the shape of an arc that bends inwards; Both sides of the cellular structure are provided with groove structures (9).

2. A SiC power MOSFET device according to claim 1, characterized in that: In the structure of the cross section A: the Pwell layer (3) wraps the N+ layer (4) and the P+ layer (5), and the boundary between the P+ layer (5) and the N+ layer (4) forms two stacked squares; In the structure of the cross section B: the Pwell layer (3) wraps the N+ layer (4) and the P+ layer (5) inside, the boundary of the P+ layer (5) and the boundary of the N+ layer (4) are arc-shaped, and the arc-shaped boundary of the N+ layer (4) wraps the arc-shaped boundary of the P+ layer (5) inside.

3. A SiC power MOSFET device according to claim 2, characterized in that: In the cross section A and the cross section B, the depth of the Pwell layer (3) is greater than the depth of the N+ layer (4) and greater than the depth of the P+ layer (5); The depth of the Pwell layer (3) in the section A is the same as that in the section B, and the depth of the Pwell layer (3) is 0.5 μm-1.5 μm; The depth of the N+ layer (4) in the section A is the same as that in the section B, and the depth of the N+ layer (4) is 0.3 μm-0.8 μm; The depth of the P+ layer (5) in the section A is the same as that in the section B, and the depth of the P+ layer (5) is 0.1 μm-0.3 μm.

4. A SiC power MOSFET device according to claim 3, characterized in that: The aluminum ion concentration injected into the Pwell layer (3) is 1×10 17 -1×10 19 cm -3 The nitrogen ion concentration injected into the N+ layer (4) is 1×10 18 -1×10 20 cm -3 The aluminum ion concentration injected into the P+ layer (5) is 1×10 18 -1×10 20 cm -3 .

5. A SiC power MOSFET device according to any one of claims 1 to 4, characterized in that: The depth of the groove structure (9) exceeds the depth of the P+ layer (5) and reaches or exceeds the depth of the N+ layer (4), but does not exceed the depth of the Pwell layer (3).

6. A SiC power MOSFET device according to claim 5, characterized in that: The depth of the groove is 0.1 μm-0.5 μm, and the groove structure (9) has a metal layer (8); the thickness of the N-epitaxial layer (2) is 5 μm-20 μm, and the ion concentration therein is 10 13 -10 17 cm -3 The thickness of the polysilicon gate layer (6) on the surface of the N-epitaxial layer (2) is in the range of The isolation layer (7) completely covers the polysilicon gate layer (6); The metal layer (8) covers the cellular structure; A drain electrode is also included below the N++ type SiC substrate (1).

7. A method for preparing a SiC power MOSFET device, characterized in that: The steps include: S1, growing an N-epitaxial layer (2) of a desired thickness on an N++ type SiC substrate (1); S2, photolithographically defining a barrier layer region (21) on the N-epitaxial layer (2), forming a first mask, and etching away the undefined barrier layer region (21), so as to obtain a barrier layer region (21) having a trapezoidal cross-sectional configuration that is narrow at the top and wide at the bottom, without removing the first mask; S3, photolithography is performed on both sides of the barrier layer region (21) with a trapezoidal cross-sectional configuration to define a through region (22), a second mask is formed, and the defined through region (22) is removed by etching, and partial slopes of the same width and length are vertically etched from both sides of the trapezoidal cross-sectional configuration at the same interval, and the partial slopes are the defined through region (22); and the second mask is removed; Due to the etching of the partial slope of the waist on both sides, a base with alternating sections A and B is formed; S4, since the first mask is not removed in S2, it is used as a mask for ion implantation, and aluminum ions are implanted to a desired depth to form a Pwell layer (3); Then, nitrogen ions are injected into the Pwell region (3) to a desired depth to form an N+ layer (4); finally, aluminum ions are injected into the N+ layer (4) to a desired depth to form a P+ layer (5); since a through region (22) exists in the barrier layer region, the boundary structures of the cross sections formed by the various ion layers are different during ion injection; after removing the first mask, the barrier layer region (21) is etched away to the N-epitaxial layer (2), thereby obtaining an alternating structure having cross sections A and cross sections B in the N-epitaxial layer (2); S5, sequentially forming a polysilicon gate layer (6) and an isolation layer (7) wrapping the polysilicon gate layer (6) on the surface of the N-epitaxial layer (2) in the JFET region; S6, etching the active area trench structure (9); S7, depositing the whole metal layer (8), and photolithography to define the active metal region and the gate metal region, and after etching to form the active region electrode and the gate electrode respectively, to obtain a SiC power MOSFET device.

8. The method for preparing a SiC power MOSFET device according to claim 7, characterized in that: The height of the barrier layer region (21) is The mesa width of the barrier layer region (22) is The angle formed by the lower base and the waist of the trapezoid is in the range of 15°-60°; the spacing between two adjacent barrier layer regions (21) is 9. The method for preparing a SiC power MOSFET device according to claim 8, characterized in that: When etching the through region (22), the same width of the waists etched away on both sides is 0.1-0.5 μm, and the same spacing between the waists on both sides is 0.5-1.5 μm; The angle during ion implantation is 0°.

10. The method for preparing a SiC power MOSFET device according to claim 7, characterized in that: In S2, wet etching is used to remove the undefined barrier layer region (21), wherein the etching solution used in the wet etching is a mixture of a 30% to 40% by mass NH4F solution and a 40% to 50% by mass HF solution in a volume ratio of 0-8:1, so that the ratio of the vertical etching rate to the horizontal etching rate is in the range of 1:0.55-3.8, and a barrier layer region (21) with a cross-sectional configuration of being narrow at the top and wide at the bottom and having a bottom inner angle range of 15°-60° is realized; In S3, plasma dry etching is used to generate interval etching on the slope of the waist on both sides of the barrier layer area (21) to remove the defined through-area (22); the gas used to generate the plasma is one or more of CF4, CHF3, C2F4, SF4, NF3, SF6, chlorine, and hydrogen bromide, and the vertical etching rate is controlled to be greater than the horizontal etching rate, thereby forming a substrate structure with alternating cross sections A and B; The base structure of the cross section A is a cross-sectional structure with a side wall slope of 80°-90°, and the base structure of the cross section B is the same as the cross-sectional structure of the barrier layer region (21).

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