Integrated circuit structure with through-stack heat spreader for bilateral devices

Abstract

Structures having a through-stack heat sink for a dual-sided device are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors and a plurality of metallization layers over the plurality of fin-based or nanowire-based transistors. A backside structure is underlying the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermally conductive via extends from a location at or below the bottom of the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure are in the field of integrated circuit structures and processing, and particularly to integrated circuit structures with through-stack heat sinks for double-sided devices. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the continued growth of the semiconductor industry. Scaling to smaller and smaller features enables the density of functional units to be increased on the limited footprint of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be incorporated on a chip, which helps to create products with increased capacity. However, the pursuit of greater and greater capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly important.

[0003] In the manufacture of integrated circuit devices, as device sizes continue to shrink, multi-gate transistors (e.g., tri-gate transistors) have become more popular. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to the lower cost of bulk silicon substrates and because they enable less complex tri-gate fabrication processes. On the other hand, when microelectronic device sizes are scaled to below the 10 nanometer (nm) node, maintaining mobility improvements and short channel control poses challenges in device fabrication. Nanowires used to fabricate devices provide improved short channel control.

[0004] However, scaling multi-gate and nanowire transistors is not without consequences. As the size of these fundamental building blocks of microelectronic circuitry decreases, and as the absolute number of fundamental building blocks fabricated in a given area increases, limitations on the photolithographic processes used to pattern these building blocks have become inevitable. In particular, there may be a tradeoff between the minimum size of a feature that is patterned in a semiconductor stack (the critical dimension) and the spacing between such features.

[0005] Another area driving innovation is the drive for high bandwidth (HBW) computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are shown according to embodiments of the present disclosure.

[0007] Figure 2A A cross-sectional view of a double-sided device according to an embodiment of the present disclosure is shown.

[0008] Figure 2BA cross-sectional view of a double-sided device including a through-stack heat sink is shown according to an embodiment of the present disclosure.

[0009] Figure 2C A cross-sectional view of another double-sided device including a through-stack heat sink according to another embodiment of the present disclosure is shown.

[0010] Figure 2D-2G Cross-sectional diagrams representing various operations in a method of fabricating a double-sided device including a through-stack heat sink are illustrated in accordance with an embodiment of the present disclosure.

[0011] Figure 3 A cross-sectional view of an integrated circuit structure with a transferred layer according to an embodiment of the present disclosure is shown.

[0012] Figure 4 A cross-sectional view of an integrated circuit structure with a nanowire logic layer and backside DRAM and power delivery according to an embodiment of the present disclosure is shown.

[0013] Figure 5A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0014] Figure 5B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0015] Fig. 6A A plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0016] Figure 6B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0017] Figure 7A-7J Cross-sectional views are illustrated of various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0018] Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0019] Fig. 9 A cross-sectional view taken through a nanowire and fin is shown for a non-endcap architecture (left hand side (a)) versus a self-aligned gate endcap (SAGE) architecture (right hand side (b)) according to an embodiment of the present disclosure.

[0020] Fig.10Cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure having a gate-all-around device are illustrated in accordance with an embodiment of the present disclosure.

[0021] Fig.11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0022] Fig. 11B The embodiment according to the present disclosure is shown Fig.11A A cross-sectional source or drain view of a nanowire-based integrated circuit structure taken along the aa' axis.

[0023] Fig. 11C The embodiment according to the present disclosure is shown Fig.11A A cross-sectional channel view of a nanowire-based integrated circuit structure taken along the bb' axis.

[0024] Fig.12 A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0025] Fig.13 An interposer including one or more embodiments of the present disclosure is shown.

[0026] Fig.14A A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0027] Fig. 14B A processing device according to one implementation of an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0028] An integrated circuit structure with a through-stack heat sink for a double-sided device is described. In the following description, many specific details are set forth, such as specific integration and material systems, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features (such as integrated circuit design layouts) are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0029] Certain terms may also be used in the following description for reference purposes only, and therefore are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "back," and "side" describe the orientation and / or position of portions of a component within a consistent but arbitrary reference system, which may be clearly understood by reference to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0030] Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses all processes up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0031] Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the fabrication stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0032] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although FEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to BEOL processing. Similarly, although BEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to FEOL processing.

[0033] One or more embodiments described herein are directed to patterned through-stack heat sinks (TSTs) for backside power delivery network (PDN) applications (e.g., for double-sided devices). In some embodiments, the device is a fin-based device. In other embodiments, the device is a nanowire-based device. It should be understood that references to nanowires herein may indicate nanowires or nanoribbons or even nanosheets unless otherwise specified.

[0034] To provide background, in a standard cell design, the diffusion placement and metal routing layers are designed around a power delivery scheme. This scheme can be through the front side bumps to the M0 and diffusion contacts, or in newer architectures it can be through the wafer back side metal which will be connected through vias that will contact the diffusion contacts located on the front side. When doing these operations, there is space allocated for power delivery, either on the front side metal or on the diffusion.

[0035] Traditionally, power is delivered from the front side interconnect. At the standard cell level, power can be delivered just on the top of the transistor or from the top or bottom cell boundary. The power delivered from the top or bottom cell boundary achieves a relatively short standard cell height and a slightly higher power network resistance. However, the front side power network shares the interconnect stack with the signal wiring, and reduces the signal wiring path. In addition, for high-performance design, the top or bottom cell boundary power metal wire must be wide enough to reduce the power network resistance and improve performance. This usually causes the cell height to increase. According to one or more embodiments of the present disclosure, power can be delivered from the back side of the wafer or substrate to solve area and performance problems. At the cell level, the wider metal 0 power at the top and bottom cell boundaries may no longer be needed, and therefore, the cell height can be reduced. In addition, the power network resistance can be significantly reduced, thereby bringing performance improvements. At the block and chip level, due to the removed power wiring, the front side signal wiring path increases, and due to very wide wires, large vias and reduced interconnect layers, the power network resistance is significantly reduced.

[0036] In earlier technologies, the power delivery network from bumps to transistors required a large amount of block resources. Such resource usage on the metal stack has in some process nodes lent itself to standard cell architectures with layout versioning or cell placement restrictions at the block level. In an embodiment, eliminating the power delivery network from the front-side metal stack allows for free translational cell placement in a block without power delivery complexity and placement-related delay timing variations.

[0037] As a comparison, Figure 1 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are shown according to embodiments of the present disclosure.

[0038] refer to Figure 1 , an interconnect stack 100 with front-side power delivery includes a transistor 102 and a signal and power delivery metallization 104. The transistor 102 includes a bulk substrate 106, a semiconductor fin 108, a terminal 110, and a device contact 112. The signal and power delivery metallization 104 includes a conductive via 114, a conductive line 116, and a metal bump 118.

[0039] Reference again Figure 1 , an interconnect stack 150 with backside power delivery includes a transistor 152, a frontside signal metallization 154A, and a power delivery metallization 154B. The transistor 152 includes a semiconductor nanowire or nanoribbon 158, a terminal 160 and a device contact 162, and a boundary deep via 163. The frontside signal metallization 154A includes a conductive via 164A and a conductive line 166A. The power delivery metallization 154B includes a conductive via 164B, a conductive line 166B, and a metal bump 168. It should be understood that in other embodiments, a backside power delivery network (BS-PDN) is implemented for a full-surround gate (GAA) device by using a direct contact from the backside to the epi (source or drain) (rather than through a via to the TCN).

[0040] To provide further context, one of the ultimate goals in standard cell design is to minimize the impact of power delivery on signal routing in terms of area, while maintaining a robust power delivery scheme that will have minimal voltage drop from the power supply. With front-side power delivery, a commercial standard cell architecture must allocate routing paths for power and ground from the top of the front-side stack to the first metal wiring layer M0. This approach will utilize metal wiring paths. This means that a tighter metal pitch is required to deliver power while routing the signals. A tighter metal pitch will result in higher capacitance and resistance, resulting in higher power consumption. In addition, due to the resistance, a larger voltage drop occurs from the top of the stack to the transistor source.

[0041] According to one or more embodiments described herein, a through-stack heat sink for a double-sided device is described.

[0042] To provide background, for technologies that employ back-side power delivery implementation, a bonding layer may be included between the interconnect stack and the carrier wafer facing the traditional heat sink in the die package. The bonding layer is a stack of dielectrics with poor heat transfer performance, and therefore thermal management is a problem for high-power, high-density applications. According to one or more embodiments described herein, the introduction of a through-stack thermal sink (TST) (also referred to herein as thermal vias) provides a heat sink and a heat dissipation path from the device down to the carrier wafer. Due to higher throttling temperature limits, TST improved thermal management can improve device performance. TST improved thermal management can improve thermomechanical reliability (due to differences in thermal expansion coefficients across the stack in the text).

[0043] According to an embodiment of the present disclosure, during the backside power delivery network (PDN) construction process, a lithography-etching-EPD-polishing sequence is used to insert the TST module. In an embodiment, the TST structure is designed to be placed near high-power devices. In an embodiment, the TST is a via-like 1-micron diameter structure etched through the entire device stack from the backside, filled with thermally conductive material and landed on a silicon carrier.

[0044] Advantages of implementing the embodiments described herein may include reducing the throttling temperature set point, which may have a significant impact on certain design use cases (e.g., single core turbo). Conventionally, a single core may experience a 2% performance loss when the throttling temperature limit is reduced by 5 degrees (100°C to 95°C). This trend may be more severe with technology scaling under isovoltage conditions due to the increase in power density with each generation. Therefore, with TST, a reduction of 6-7°C is considerable. In a specific embodiment, the maximum temperature of a single core turbo hotspot is reduced from 136°C to 128°C.

[0045] The detectability of the embodiments described herein may include reverse engineering. In one embodiment, the TST structure may be revealed as a continuous metal giant via across the entire stack. In one embodiment, its construction starts from the back side and lands at 2 to 4 microns on or within a silicon carrier. In one embodiment, EDS for Cu or W or polysilicon can identify its presence / function. In one embodiment, the structure may be surrounded by a liner (nitride or oxide) and may also be detected. In one embodiment, the structure may be floating or connected by a remaining metal layer, thereby also providing a ground contact function. However, it should be understood that the depth may not be critical. For example, in other embodiments, as long as the TST is not connected to an electrical contact located below the substrate (as with a 3DIC through-stack via), its role is to be used for heat or discharge (where the latter case will require a connection at the top).

[0046] As an exemplary but non-limiting structure that may benefit from the through-stack heat sink described in the following embodiments, Figure 2A A cross-sectional view of a double-sided device according to an embodiment of the present disclosure is shown.

[0047] refer to Figure 2A, the integrated circuit structure 200 includes a front side structure 204 and a back side structure 202, which may be separated by a dielectric layer 205. The front side structure 204 includes a device layer 206 and a plurality of metallization layers 208 located on the device layer 206. The structure 200 is supported by a Si (100) carrier wafer 210 and an intervening SiOx layer 211 of approximately 400 nm located on the front side structure 204. The back side structure 202 includes a stack of back side conductive structures 218.

[0048] about Figure 2A It should be understood that although a gate-all-around based transistor is depicted, embodiments may be applied to channels of any shape or material (e.g., fins, nanowires, nanoribbons, nanocombs / forks, etc.). Figure 2A It should be understood that although a single layer of transistors is shown, embodiments may be applied to multi-layer transistor architectures.

[0049] As an example of incorporating a through-stack heat sink, Figure 2B A cross-sectional view of a double-sided device including a through-stack heat sink is shown according to an embodiment of the present disclosure.

[0050] refer to Figure 2B , the integrated circuit structure 220 includes a front side structure 224 and a back side structure 222. The front side structure 224 includes a device layer 226 and a plurality of metallization layers 228 located on the device layer 226, and the device layer 226 and the plurality of metallization layers 228 can be separated by a bonding layer 227 (e.g., a dielectric bonding layer or a mixed metal and dielectric bonding layer). The structure 220 is supported by a carrier wafer or substrate 230 bonded to the front side structure 224. The back side structure 222 includes a stack of back side conductive structures. In an embodiment, the carrier wafer or substrate 230 is a silicon carrier wafer. The carrier wafer or substrate 230 can provide a main cooling path for the integrated circuit structure 220.

[0051] Reference again Figure 2B, the integrated circuit structure 220 includes a through-stack heat sink (TST) 232, which is also referred to herein as a thermal via. In an embodiment, the thermal via 232 includes a dielectric liner and a conductive filler, such as copper or tungsten or polysilicon filler. In an embodiment, the thermal via 232 is a through-silicon via (TSV) that is only thermally conductive. In an embodiment, the thermal via 232 does not electrically couple electrical features. In an embodiment, the thermal via 232 is electrically floating. In an embodiment, the thermal via 232 is coupled to ground. In an embodiment, the thermal via 232 is coupled to an electrical feature, but does not couple this electrical feature to another electrical feature. In an embodiment, the thermal via 232 extends from a position at or below the bottom of the device layer 226 to a position above the device layer 226 (in a direction taken from the back side of the front side structure), and more specifically, extends to a position on or into the carrier wafer or substrate 230.

[0052] In an embodiment, the device layer 226 includes a field effect transistor (FET), such as a nanowire-based or fin-based transistor. In one such embodiment, the FET is used for a logic cell. In an embodiment, the plurality of metallization layers 228 includes an increased metal layer and associated via layers. In an embodiment, the backside conductive structure 222 includes a plurality of backside metal layers and associated vias.

[0053] As another example of incorporating a through-stack heat sink, Figure 2C A cross-sectional view of another double-sided device including a through-stack heat sink according to another embodiment of the present disclosure is shown.

[0054] refer to Figure 2C , the integrated circuit structure 240 includes a front side structure 244 and a back side structure 242. The front side structure 244 includes a device layer 246 and a plurality of metallization layers 248 located on the device layer 246. The structure 240 is supported by a carrier wafer or substrate 250 (e.g., a silicon wafer or substrate) and an optional intermediate glue or bonding layer 251 located on the front side structure 244. The back side structure 242 includes a stack of back side conductive structures.

[0055] Reference again Figure 2C, the integrated circuit structure 240 includes a through stack heat sink (TST) 252, which is also referred to herein as a thermal via. In an embodiment, the thermal via 252 includes a dielectric liner 254 and a conductive filler 256, such as copper or tungsten or polysilicon filler. In an embodiment, the thermal via 252 is a through silicon via (TSV) that is only thermally conductive. In an embodiment, the thermal via 252 does not electrically couple electrical features. In an embodiment, the thermal via 252 is electrically floating. In an embodiment, the thermal via 252 is coupled to ground. In an embodiment, the thermal via 252 is coupled to one electrical feature (e.g., backside feature 258), but does not couple the one electrical feature 258 to another electrical feature. In an embodiment, the thermal via 252 extends from a position at or below the bottom of the device layer 246 (as shown) to a position above the device layer 246 (in a direction taken from the back side of the front side structure), and more specifically, to a position on or into the carrier wafer or substrate 250 (as shown).

[0056] In an embodiment, the device layer 246 includes a field effect transistor (FET), such as a fin-based (as shown) or nanowire-based transistor. In one such embodiment, the FET is used for a logic cell. In an embodiment, the plurality of metallization layers 248 include an increased metal layer and associated via layers. In an embodiment, the backside conductive structure 242 includes a plurality of backside metal layers and associated vias.

[0057] On the other hand, wafer bonding is an important and critical part of SOI technology. Typically, the bonding is achieved by direct bonding of two wafers to a SiO2 layer - first, at room temperature, by van der Waals forces, and then permanently by forming covalent bonds during annealing. The bonding layer is a stack of dielectrics with poor thermal transport properties, and is therefore a problem for thermal management in high-power, high-density applications. The bonded wafer is permanent, i.e., it not only needs to be retained for subsequent process operations, but also for field use. In an embodiment, the TST is a via-like structure that is etched from the back side through the entire device stack, through the bonding oxide layer and lands in the carrier wafer. In an embodiment, the TST is filled with a thermally conductive material to allow heat to be dissipated from the device to the carrier wafer.

[0058] In an embodiment, the flow sequence and process may include one or more of the following: (1) During the backside PDN construction, an integrated module is inserted after the backside metal layer and before the corresponding backside via level. The insertion of this module can be located anywhere within the backside construction, taking into account the final stack height to be etched and the post-wafer molding processing (alignment control - impact on contact resistance). (2) Deposition of a hard mask sequence. This sequence can consist of SiCN layers, ILD oxide, DLC carbon, SiARC. This sequence can be removed by processing. (3) The photolithographic pattern can expose a via / contact-like structure. Depending on the patterning requirements and process capabilities, the diameter can be variable, for example, a structure with a diameter of 0.5 microns to 10 microns (e.g., 1 micron diameter) can be implemented. (4) The area to be etched can be processed by removing the design of the metal layer drawing (except for the front-end polysilicon / W - the need for polishing density uniformity). The area where the TST lands can also be surrounded by a guard ring constructed from the front side. (5) Etching can remove the stack and land on a silicon carrier. The TST can land on a silicon carrier or continue to be recessed into it (2 to 5 μm). (6) Ashing and cleaning can remove remaining DLC ​​carbon (or photoresist if a simpler hard mask can be implemented). (7) Liner or linerless options are possible. In an embodiment, the liner material is silicon carbide, silicon nitride, silicon oxide, and polysilicon are viable liners. A liner may be required for integrity and stress management. The liner can also provide further contamination control. In an embodiment, the TST does not carry any signal. The final liner thickness can be a function of the final reliability and thermal results. In an embodiment, the linerless option can be used to enable the TST to be used for carrier contacts and simplify the process. (8) Barriers and EPDs can include the use of Cu. Barriers can be selected based on thickness and conditions to allow uniform deposition at the bottom and sidewalls of the TST. This can achieve correct EPD filling and ensure that there are no reliability issues. In an embodiment, the TST can be filled with any other thermally conductive film. Lower thermal conductivity can alleviate other integration limitations or reliability issues. (9) Polishing or etching back can be implemented to remove the thermally conductive film. Polishing can be set to consume the remaining hard mask (ILD oxide). Polishing can be set to stop on the SiCN stop film or remove it entirely. (10) A new SiCN stop film can be deposited and the flow can continue with backside via levels and additional backside processing.

[0059] As an exemplary process flow, Figure 2D-2G Cross-sectional diagrams representing various operations in a method of fabricating a double-sided device including a through-stack heat sink are illustrated in accordance with an embodiment of the present disclosure.

[0060] refer to Figure 2D, the starting structure 260 includes a front side structure 264 and a back side structure 262. The front side structure 264 includes a device layer 266 and a plurality of metallization layers 268 located on the device layer 266. The structure 260 is supported by a carrier wafer or substrate 270 (e.g., a silicon wafer or substrate) and an optional intermediate glue or bonding layer 271 located on the front side structure 244. The back side structure 262 includes a stack of back side conductive structures. As depicted, an interlayer dielectric layer 272 can be formed on the back side structure 262. At this stage, a patterned stack (e.g., a stack including a hard mask layer 274 and a photoresist layer 276 having openings 278 patterned therein) is formed over the back side structure 262.

[0061] In an embodiment, device layer 266 includes field effect transistors (FETs), such as fin-based (as shown) or nanowire-based transistors. In one such embodiment, the FETs are used for logic cells. In an embodiment, multiple metallization layers 268 include added metal layers and associated via layers. In an embodiment, backside conductive structure 262 includes multiple backside metal layers and associated vias.

[0062] refer to Figure 2E , using the patterned stack, an opening 280 is etched in structure 260. As depicted, the opening may extend into carrier wafer or substrate 270 to form patterned carrier wafer or substrate 270A.

[0063] refer to Figure 2F , a dielectric liner 282 and a conductive filler 284 are formed on Figure 2E On top of the structure in.

[0064] refer to Figure 2G , the dielectric liner 282 and the conductive filler 284 are planarized to form a through-stack heat sink (TST) 286, which is also referred to herein as a thermal via. In an embodiment, the thermal via 286 includes a dielectric liner 282A and a conductive filler 284A, such as copper or tungsten or polysilicon filler. In an embodiment, the thermal via 286 is a through-silicon via (TSV) that is only thermally conductive. In an embodiment, the thermal via 286 does not electrically couple electrical features. In an embodiment, the thermal via 286 is electrically floating. In an embodiment, the thermal via 286 is coupled to ground. In an embodiment, the thermal via 286 is coupled to one electrical feature, but does not couple the one electrical feature to another electrical feature. In an embodiment, the thermal via 286 extends from a position at or below the bottom of the device layer 266 (as shown) to a position above the device layer 266 (in a direction taken from the back side of the front side structure), and more specifically, to a position on or into the patterned carrier wafer or substrate 270A (as shown).

[0065] about Figure 2C-2G , it should be understood that although fin-based transistors are shown, embodiments may be applied to channels of any shape or material (e.g., all-around gate devices such as nanowires, nanoribbons, nanocombs, forked sheets, etc.). Figure 2C-2G It should be understood that although a single layer of transistors is shown, embodiments may be applied to multi-layer transistor architectures.

[0066] In embodiments, with respect to performance and layout impact, if the design approach for TST or other critical requirements is not improved, the layout impact may be significant. In embodiments, a 1×1 micron blockage due to TST (simulating 1 micron TST without guard rings at 20 μm pitch) may result in a 2.5% reduction in frequency or a 4.6% increase in power. In embodiments, TST is only required in hot spots, and not all design blocks are highly utilized. That said, in certain embodiments, this benefit may be achieved by doing critical floorplanning up front, rather than leaving it to a random approach.

[0067] To provide further context, in future technology versions using backside based silicon in 3D-IC scenarios, power delivery across the 3D stack and signal routing requires short micron-scale through-silicon heat sinks. In an embodiment, these TSTs are a natural extension of the embodiments described herein, covering 10 to 20 microns in thickness and the entire backside and frontside stack. In an embodiment, local thermal gradients are higher with the same power density per chiplet. In an embodiment, with critical 3D routing and floorplanning, design benefits can be extracted from both electrical and thermal considerations. In an embodiment, arrays of TSTs are placed around the core in areas without dense routing. In an embodiment, the core hotspots are close to its perimeter, and such placement can provide thermal benefits.

[0068] It should be understood that Figure 2B-2G The described through-stack heat sink embodiments can be implemented with or incorporated into various structures. As a non-limiting example, embodiments of the present disclosure effectively involve moving dynamic random access memory (DRAM) (e.g., based on the arrangement of 1 transistor 1 capacitor (1T1C) devices) to the back side of a substrate or wafer to act as a local cache. Embodiments can be implemented to directly benefit from the presence of backside power delivery to support high bandwidth. Embodiments can be implemented to include a close spacing layer inside the ID layer between interconnects for power. Implementations of the embodiments described herein can be detected using capacitors on the back side.

[0069] One or more embodiments described herein are directed to separating dynamic random access memory (DRAM) on the back side of a wafer or substrate. One or more embodiments described herein are directed to an integrated circuit structure having a nanowire memory layer and backside DRAM and power delivery. It should be understood that references to nanowires herein may indicate nanowires or nanoribbons or even nanosheets unless otherwise specified. One or more embodiments described herein are directed to an integrated circuit structure having a fin-based memory layer and backside DRAM and power delivery.

[0070] Thin film transistor (TFT) implementations on the front side can benefit from the through-stack heat sink embodiments described herein. As an example, Figure 3 A cross-sectional view of an integrated circuit structure with a transferred layer is shown.

[0071] refer to Figure 3 , the integrated circuit structure 300 includes a front side structure 304 located on a back side structure 302. The front side structure 304 includes a device layer 306 and a plurality of metallization layers 308 located on the device layer 306. The structure 300 can be supported by a carrier wafer 310 located on the front side structure 304. The back side structure 302 includes a stack of back side conductive structures 318 terminating at conductive bumps 312.

[0072] In an embodiment, the device layer 306 includes field effect transistors (FETs), such as nanowire-based (as shown) or fin-based transistors. In one such embodiment, the FETs are used for logic cells. In an embodiment, the device layer 306 also includes trench contacts (TCNs), gate contacts (GCNs), and contact vias (VCXs). In an embodiment, as depicted, the device layer 306 is located on a deep via (DV) layer of the front side structure 304. In an embodiment, the plurality of metallization layers 308 includes added metal layers (e.g., M0-M12) and associated via layers (e.g., Figure 3 V0-V3 marked in ).

[0073] In an embodiment, the backside structure 302 includes a plurality of backside metal layers (e.g., BM0-BM3) and associated vias. In an embodiment, the backside structure 302 includes one or more power structures, such as ground metal lines (e.g., GM0 and GM1). In an embodiment, the backside structure 302 includes structures 314 / 316 of a retainer and DRAM having III-V materials. The structures 314 / 316 include a device layer 314 and a layer 316 having one or more capacitor structures. Other layers may also be included, such as a layer including one or more metal-insulator-metal (MIM) capacitors.

[0074] As another exemplary but non-limiting structure that may benefit from the through-stack heat sink embodiments described herein, Figure 4 A cross-sectional view of an integrated circuit structure with a nanowire logic layer and backside DRAM and power delivery according to an embodiment of the present disclosure is shown. It should be understood that although Figure 4 Nanowires (or nanoribbons or nanosheets) are depicted in FIG, but fin-based architectures may also be used.

[0075] refer to Figure 4 , the integrated circuit structure 400 includes a front side structure 404 located on a back side structure 402. The front side structure 404 includes a device layer 406 and a plurality of metallization layers 408 located on the device layer 406. The structure 400 can be supported by a carrier wafer 410 located on the front side structure 404. The back side structure 402 includes a stack of back side conductive structures 418 terminating at conductive bumps 412.

[0076] In an embodiment, device layer 406 includes field effect transistors (FETs), such as nanowire-based (as shown) or fin-based transistors. In one such embodiment, the FETs are used for logic cells, such as nanowire-based transistors. The device layer 406 is a nanowire-based logic transistor. In an embodiment, device layer 406 also includes trench contacts (TCNs), gate contacts (GCNs), and contact vias (VCXs). In an embodiment, as depicted, device layer 406 is located on a deep via (DV) layer of front side structure 404. In an embodiment, multiple metallization layers 408 include added metal layers (e.g., M0-M12) and associated via layers (e.g., Figure 4 V0-V3 marked in ).

[0077] In an embodiment, the backside structure 402 includes a plurality of backside metal layers (e.g., BM0-BM3) and associated vias. In an embodiment, the backside structure 402 includes one or more power structures, such as a ground metal line (e.g., GM1). In an embodiment, the backside structure 402 includes a structure 416 of a DRAM device, such as a 1T-1C device (e.g., a transistor 416A and a capacitor 416B). In one embodiment, the capacitor 416B is along an axis that is the same as the width direction of the nanowire or fin of the FET of the device layer 406. In another embodiment, the capacitor 416B is along an axis that is the same as the length direction of the nanowire or fin of the FET of the device layer 406. It should be understood that as depicted, other layers may also be included, such as a layer including one or more metal-insulator-metal (MIM) capacitors.

[0078] Thus, according to an embodiment of the present disclosure, an integrated circuit structure 400 includes a frontside structure 404 including a device layer 406 having a plurality of nanowire-based transistors and a plurality of metallization layers 408 located above the nanowire-based transistors of the device layer 406. A backside structure 402 is located below the nanowire-based transistors of the device layer 406. The backside structure 402 includes a plurality of dynamic random access memory (DRAM) devices, for example, as depicted as portion 416.

[0079] In another aspect, contact over active gate (COAG) structures and processes are described, which can further enable a compact structure of a cell architecture including backside DRAM and power delivery, for example. One or more embodiments of the present disclosure are directed to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed over an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure are directed to a method of making a semiconductor structure or device having one or more gate contact structures formed over an active portion of a gate electrode of the semiconductor structure or device. The methods described herein can be used to reduce the standard cell area by enabling a gate contact to be formed over an active gate region. According to one or more embodiments, a tapered gate and trench contact are implemented to enable COAG fabrication. Embodiments can be implemented to achieve tight pitch patterning.

[0080] To provide further context for the importance of the COAG process scheme, in technologies where space and layout constraints are relaxed compared to current generations, a contact to a gate structure may be made by making contact with a portion of a gate electrode disposed over an isolation region. As an example, Figure 5A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0081] refer to Figure 5A, semiconductor structure or device 500A includes a diffusion or active region 504 disposed in substrate 502 and within isolation region 506. One or more gate lines (also referred to as poly lines) (e.g., gate lines 508A, 508B, and 508C) are disposed over diffusion or active region 504 and over a portion of isolation region 506. Source or drain contacts (also referred to as trench contacts) (e.g., contacts 510A and 510B) are disposed over source and drain regions of semiconductor structure or device 500A. Trench contact vias 512A and 512B provide contact to trench contacts 510A and 510B, respectively. A separate gate contact 514 and an overlying gate contact via 516 provide contact to gate line 508B. In contrast to the source or drain trench contacts 510A or 510B, from a plan view perspective, the gate contact 514 is disposed over the isolation region 506 but not over the diffusion or active region 504. In addition, neither the gate contact 514 nor the gate contact via 516 is disposed between the source or drain trench contacts 510A and 510B.

[0082] Figure 5B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown. Figure 5B , semiconductor structure or device 500B (eg, Figure 5A 50A) includes a non-planar diffusion or active region 504B (e.g., a fin structure) formed by a substrate 502 and located within an isolation region 506. A gate line 508B is disposed over the non-planar diffusion or active region 504B and over a portion of the isolation region 506. As shown, the gate line 508B includes a gate electrode 550 and a gate dielectric layer 552, as well as a dielectric cap layer 554. It can also be seen from this perspective that the gate contact 514 and the overlying gate contact via 516, as well as the overlying metal interconnect 560, are all disposed in an interlayer dielectric stack or layer 570. From Figure 5B It is also seen from the perspective of FIG. 5 that the gate contact 514 is disposed over the isolation region 506 , but is not disposed over the non-planar diffusion or active region 504B.

[0083] Reference again Figure 5A and Figure 5B, the arrangement of semiconductor structures or devices 500A and 500B, respectively, places the gate contact above the isolation region. Such an arrangement wastes layout space. However, placing the gate contact above the active area would require an extremely tight registration budget, or the gate size would have to be increased to provide sufficient space to land the gate contact. In addition, historically, contact with the gate above the diffusion region has been avoided due to the risk of drilling through other gate materials (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described herein solve the above-mentioned problems by providing a feasible method and resulting structure for making a contact structure that contacts a portion of the gate electrode formed above the diffusion or active region.

[0084] As an example, Fig. 6A FIG. 1 is a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure. Fig. 6A , semiconductor structure or device 600A includes a diffusion or active region 604 disposed in a substrate 602 and within an isolation region 606. One or more gate lines (e.g., gate lines 608A, 608B, and 608C) are disposed over the diffusion or active region 604 and over a portion of the isolation region 606. Source or drain trench contacts (e.g., trench contacts 610A and 610B) are disposed over the source and drain regions of the semiconductor structure or device 600A. Trench contact vias 612A and 612B provide contact to trench contacts 610A and 610B, respectively. Gate contact via 616 (which does not have an intervening separate gate contact layer) provides contact to gate line 608B. Figure 5A In contrast, from a plan view perspective, gate contact 616 is disposed over diffusion or active region 604 and between source or drain contacts 610A and 610B.

[0085] Figure 6B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure is shown. Figure 6B , a semiconductor structure or device 600B, for example, Fig. 6A600A, includes a non-planar diffusion or active region 604B (e.g., a fin structure) formed by a substrate 602 and located within an isolation region 606. A gate line 608B is disposed over the non-planar diffusion or active region 604B and over a portion of the isolation region 606. As shown, the gate line 608B includes a gate electrode 650 and a gate dielectric layer 652, as well as a dielectric cap layer 654. From this perspective, it can also be seen that the gate contact via 616 is disposed in an interlayer dielectric stack or layer 670 along with the overlying metal interconnect 660. In addition, from Figure 6B As seen from the perspective of FIG. 6A , the gate contact via 616 is disposed above the non-planar diffusion or active region 604B.

[0086] Therefore, refer again Fig. 6A and Figure 6B In an embodiment, the trench contact vias 612A, 612B and the gate contact via 616 are formed in the same layer and are substantially coplanar. Figure 5A and Figure 5B In contrast, the contact to the gate line will additionally include an additional gate contact layer, which may, for example, extend perpendicularly to the corresponding gate line. Fig. 6A and Figure 6B In the described (multiple) structures, the fabrication of structures 600A and 600B respectively enables the contact to be landed directly on the active gate portion from the metal interconnect layer without shorting to the adjacent source drain region. In an embodiment, such an arrangement provides a large area reduction of the circuit layout by eliminating the need to extend the transistor gate on the isolation to form a reliable contact. As used throughout the text, in an embodiment, reference to the active portion of the gate refers to the portion of the gate line or structure disposed above the active or diffusion region of the underlying substrate (from a plan view perspective). In an embodiment, reference to the passive portion of the gate refers to the portion of the gate line or structure disposed above the isolation region of the underlying substrate (from a plan view perspective).

[0087] In an embodiment, the semiconductor structure or device 600 is a non-planar device, such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 608A and 608B surrounds at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is made into a discrete three-dimensional body (e.g., in a full surround gate device). In one such embodiment, the gate electrode stacks of gate lines 608A and 608B each completely surround the channel region.

[0088] Generally, one or more embodiments are directed to methods for landing gate contact vias directly on active transistor gates and structures formed thereby. Such methods can eliminate the need to extend gate lines on isolation for contact purposes. Such methods can also eliminate the need for a separate gate contact (GCN) layer for conducting signals from gate lines or structures. In an embodiment, the elimination of the above features is achieved by recessing the contact metal in the trench contact (TCN) and introducing additional dielectric material (e.g., trench insulation layer (TILA)) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer having etching characteristics different from the gate dielectric material cap layer used for trench contact alignment in a gate aligned contact process (GAP) processing scheme (e.g., using a gate insulation layer (GILA)).

[0089] As an exemplary fabrication scheme, the starting structure includes one or more gate stack structures disposed on a substrate. The gate stack structure may include a gate dielectric layer and a gate electrode. A trench contact, such as a contact to a diffusion region of the substrate or to an epitaxial region formed in the substrate, is spaced apart from the gate stack structure by a dielectric spacer. An insulating cap layer may be disposed on the gate stack structure (e.g., GILA). In one embodiment, a contact blocking region or "contact plug" that may be made of an interlayer dielectric material is included in the region where the blocking contact formation is to be blocked.

[0090] In an embodiment, the contact pattern is substantially perfectly aligned with the existing gate pattern while eliminating the use of lithography operations with extremely tight registration budgets. In one such embodiment, the method enables the use of essentially highly selective wet etching (or anisotropic dry etching processes, some of which are non-plasma, gas phase isotropic etching (e.g., relative to classical dry or plasma etching)) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, as used in other methods, the method enables the elimination of the need for other critical lithography operations for generating contact patterns. This method also allows perfect or near-perfect self-alignment with a large margin for edge placement errors. In an embodiment, the trench contact grid is not patterned separately, but is formed between polycrystalline (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0091] In addition, the gate stack structure can be made by replacing the gate process. In such a scheme, the dummy gate material (e.g., polysilicon or silicon nitride column material) can be removed and replaced by a permanent gate electrode material. In one such embodiment, in contrast to the earlier processing, a permanent gate dielectric layer is also formed in the process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including aqueous phosphoric acid.

[0092] In an embodiment, one or more methods described herein substantially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in a particular such embodiment, an anneal of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius, such as after forming the gate dielectric layer. The annealing is performed before forming the permanent contact.

[0093] Next, the trench contact may be recessed to provide a recessed trench contact having a height lower than the top surface of the adjacent spacer. An insulating capping layer is then formed on the recessed trench contact (e.g., TILA). According to an embodiment of the present disclosure, the insulating capping layer on the recessed trench contact is composed of a material having different etching characteristics than the insulating capping layer on the gate stack structure.

[0094] The trench contact can be recessed by a process that is selective to the materials of the spacer and the gate insulating cap layer. For example, in one embodiment, the trench contact is recessed by an etching process (e.g., a wet etching process or a dry etching process). The trench contact insulating cap layer can be formed by a process suitable for providing a conformal and sealed layer above the exposed portion of the trench contact. For example, in one embodiment, the trench contact insulating cap layer is formed as a conformal layer located above the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized by chemical mechanical polishing (CMP) to provide a trench contact insulating cap layer only above the recessed trench contact.

[0095] Regarding material combinations suitable for the gate or trench contact insulating capping layer, in one embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon oxide, and the other material is composed of silicon nitride. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon oxide, and the other material is composed of carbon-doped silicon nitride. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon oxide, and the other material is composed of silicon carbide. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon nitride, and the other material is composed of carbon-doped silicon nitride. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon nitride, and the other material is composed of silicon carbide. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon nitride, and the other material is composed of silicon carbide. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of carbon-doped silicon nitride, and the other material is composed of silicon carbide.

[0096] In another aspect, a nanowire or nanoribbon structure is described. A nanowire or nanoribbon release process can be performed by replacing the gate trench. An example of such a release process is described below. In addition, in yet another aspect, back-end (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein may be implemented to achieve front-side and back-side interconnect integration for nanowire transistors. The embodiments described herein may provide methods for achieving relatively wider interconnect spacing. The result may be improved product performance and lower patterning costs. Embodiments may be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0097] In another aspect, it should be understood that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials including but not limited to Si and SiGe. For example, III-V materials may be used.

[0098] It should be understood that in certain embodiments, the nanowires or nanobelts or sacrificial intervening layers may be composed of silicon. As used throughout the text, a silicon layer may be used to describe a silicon material composed of a very large amount (if not all) of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form, and therefore, a very small percentage of carbon, germanium or tin may be included. Such impurities may be included as unavoidable impurities or components during the deposition of Si, or may "contaminate" Si when diffused during post-deposition processing. In this way, the embodiments described herein for the silicon layer may include a silicon layer containing a relatively small amount (e.g., "impurity" level) of non-Si atoms or substances (e.g., Ge, C or Sn). It should be understood that the silicon layer as described herein may be undoped or may be doped with dopant atoms (e.g., boron, phosphorus or arsenic).

[0099] It should be understood that in certain embodiments, the nanowires or nanoribbons or sacrificial intervening layers may be composed of silicon germanium. As used throughout, a silicon germanium layer may be used to describe a silicon germanium material composed of a majority of both silicon and germanium (e.g., at least 5% of both). In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, the silicon germanium layer includes approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer includes about 30% germanium and about 70% silicon (Si 70 Ge 30 ). It should be understood that, in practice, 100% pure silicon germanium (generally referred to as SiGe) may be difficult to form, and therefore, may include very small percentages of carbon or tin. Such impurities may be included as unavoidable impurities or components during deposition of SiGe, or may "contaminate" SiGe when diffused during post-deposition processing. Thus, embodiments described herein for silicon germanium layers may include silicon germanium layers that include relatively small amounts (e.g., "impurity" levels) of non-Ge and non-Si atoms or substances (e.g., carbon or tin). It should be understood that silicon germanium layers as described herein may be undoped or may be doped with dopant atoms (e.g., boron, phosphorus, or arsenic).

[0100] Described below are various devices and processing schemes that can be used to make devices that can be integrated with structures having a through-stack heat sink for double-sided devices. It should be understood that exemplary embodiments do not necessarily require all of the features described, or may include more features than described. For example, nanowire release processing can be performed by replacing gate trenches. An example of such a release process is described below. In addition, in yet another aspect, back-end (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein can be implemented to achieve front-side and back-side interconnect integration for nanowire transistors. The embodiments described herein can provide methods for achieving relatively wide interconnect spacing. The result can be improved product performance and lower patterning costs. The embodiments can be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0101] One or more embodiments described herein are directed to dual epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depths. In an embodiment, an integrated circuit structure is fabricated by forming a source-drain opening of a nanowire / nanoribbon transistor partially filled with SD epitaxy. The remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain sides enables direct contact to a backside interconnect level.

[0102] As an exemplary process flow for making a gate-all-around device for a gate-all-around integrated circuit structure, Figure 7A-7J Cross-sectional views are illustrated of various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0103] refer to Fig. 7A , a method of making an integrated circuit structure includes: forming a starting stack including alternating sacrificial layers 704 and nanowires 706 located above a fin 702 (e.g., a silicon fin). The nanowires 706 may be referred to as a vertical arrangement of nanowires. As depicted, a protective cap 708 may be formed over the alternating sacrificial layers 704 and nanowires 706. Also as depicted, a relaxed buffer layer 752 and a defect modification layer 750 may be formed under the alternating sacrificial layers 704 and nanowires 706.

[0104] refer to Figure 7B , a gate stack 710 is formed on the vertical arrangement structure of the horizontal nanowires 706. Figure 7C As depicted in , portions of the vertically arranged structure of horizontal nanowires 706 are then released by removing portions of the sacrificial layer 704 to provide a recessed sacrificial layer 704 ′ and a cavity 712 .

[0105] It should be understood that the contact processing described below can be completed without first performing the deep etching and asymmetric contact processing described below. Figure 7C In either case (eg, with or without asymmetric contact processing), in an embodiment, the fabrication process involves using a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial bump, which may be a vertically discrete source or drain structure.

[0106] refer to Fig.7D , an upper gate spacer 714 is formed at the sidewalls of the gate structure 710. A cavity spacer 716 is formed in the cavity 712 beneath the upper gate spacer 714. A deep trench contact etch is then optionally performed to form a trench 718 and form a recessed nanowire 706'. As depicted, there may also be a patterned relaxed buffer layer 752' and a patterned defect modification layer 750'.

[0107] like Fig. 7E As depicted in , sacrificial material 720 is then formed in trench 718. In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0108] refer to Figure 7F , a first epitaxial source or drain structure (e.g., left-hand feature 722) is formed at a first end of the vertical arrangement of horizontal nanowires 706'. A second epitaxial source or drain structure (e.g., right-hand feature 722) is formed at a second end of the vertical arrangement of horizontal nanowires 706'. In an embodiment, as depicted, the epitaxial source or drain structure 722 is a vertically discrete source or drain structure and may be referred to as an epitaxial bump.

[0109] like Figure 7G As depicted in , an interlayer dielectric (ILD) material 724 is then formed at the sides of the gate electrode 710 and adjacent to the source or drain structure 722. Figure 7H , a replacement gate process is used to form a permanent gate dielectric 728 and a permanent gate electrode 726. Fig.7I , the ILD material 724 is then removed. The sacrificial material 720 is then removed from one of the source drain locations (eg, the right hand side) to form the trench 732, but the sacrificial material 720 is not removed from the other of the source drain locations to form the trench 730.

[0110] refer to Figure 7J, forming a first conductive contact structure 734 coupled to the first epitaxial source or drain structure (e.g., left-hand feature 722). Forming a second conductive contact structure 736 coupled to the second epitaxial source or drain structure (e.g., right-hand feature 722). The second conductive contact structure 736 is formed deeper along the fin 702 than the first conductive contact structure 734. In an embodiment, although Figure 7J Not depicted, but the method also includes: forming an exposed surface of a second conductive contact structure 736 at the bottom of the fin 702. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, where examples may include Ti, Ni, Co (for the former, and W, Ru, Co for the latter).

[0111] In an embodiment, as depicted, the second conductive contact structure 736 is deeper along the fin 702 than the first conductive contact structure 734. In one such embodiment, as depicted, the first conductive contact structure 734 is not along the fin 702. In another such embodiment, not depicted, the first conductive contact structure 734 is partially along the fin 702.

[0112] In an embodiment, the second conductive contact structure 736 is along the entire fin 702. In an embodiment, although not depicted, the second conductive contact structure 736 has an exposed surface at the bottom of the fin 702 if the bottom of the fin 702 is exposed by a backside substrate removal process.

[0113] In an embodiment, for example as described above, Figure 7J The structure or Figure 7A-7J The related structure in may be included in a structure including a through-stack heat sink for a double-sided device.

[0114] In another aspect, in order to be able to access two conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be made using a backside exposure method of a frontside structure. In some exemplary embodiments, the exposure of the backside of a transistor or other device structure requires wafer-level backside processing. In contrast to conventional TSV type technology, the exposure of the backside of a transistor as described herein can be performed at the density of a device unit and even in a sub-region of the device. In addition, such exposure of the backside of a transistor can be performed to substantially remove all donor substrates on which a device layer is disposed during front-side device processing. In this way, micron-deep TSVs become unnecessary when the thickness of the semiconductor in the device unit may be only tens or hundreds of nanometers after the exposure of the backside of the transistor.

[0115] The exposure techniques described herein can enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer that is employed in front-side fabrication, exposed from the backside, and employed again in back-side fabrication. Processing both the front side and the exposed back side of a device structure can address many of the challenges associated with fabricating 3D ICs when relying primarily on front-side processing.

[0116] Methods of revealing the back side of the transistor can be used, for example, to remove at least a portion of the carrier layer and the intervening layers of the donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be used.

[0117] In some embodiments, prior to the above steps, the carrier layer is cleaved along a fracture plane substantially parallel to the intermediate layer. A cleavage or fracture process can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cleaved away by practicing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted into the carrier layer to a uniform target depth where a fracture plane is desired. After such a cleavage process, the remaining thickness of the carrier layer in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove a greater thickness of the carrier layer.

[0118] Next, the exposure of the intervening layer is detected. Detection is used to identify the point when the backside surface of the donor substrate has advanced to the point close to the device layer. Any endpoint detection technology known to be suitable for detecting the transition between the materials used in the carrier layer and the intervening layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting the change in light absorption or emission of the backside surface of the donor substrate during the execution of polishing and / or etching. In some other embodiments, the endpoint criteria are associated with the change in light absorption or emission of the byproducts during the polishing or etching of the backside surface of the donor substrate. For example, the absorption or emission wavelength associated with the carrier layer etching byproduct can be changed as a function of the different components of the carrier layer and the intervening layer. In other embodiments, the endpoint criteria are associated with the change in the mass of the substance in the byproduct of polishing or etching the backside surface of the donor substrate. For example, the byproducts of the processing can be sampled by a quadrupole mass analyzer, and the change in the mass of the substance can be related to the different components of the carrier layer and the intervening layer. In another exemplary embodiment, the endpoint criteria are associated with the change in friction between the backside surface of the donor substrate and the polishing surface in contact with the backside surface of the donor substrate.

[0119] Since non-uniformities in the carrier removal process can be mitigated by the difference in etch rates between the carrier layer and the intervening layer, detection of the intervening layer can be enhanced in cases where the removal process is selective for the carrier layer relative to the intervening layer. Detection can even be skipped if the grinding, polishing and / or etching operation removes the intervening layer at a rate sufficiently lower than the rate at which the carrier layer is removed. If no endpoint criteria are used, then the grinding, polishing and / or etching operation of a predetermined fixed duration can be stopped on the intervening layer material if the thickness of the intervening layer is sufficient for etching selectivity. In some examples, the carrier etch rate:intervening layer etch rate is 3:1-10:1 or greater.

[0120] After exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more component layers in the intervening layer may be removed. For example, the thickness of the intervening layer may be uniformly removed by polishing. Alternatively, the thickness of the intervening layer may be removed using a mask or blanket etching process. The process may employ the same polishing or etching process as used to thin the carrier, or may be a different process with different process parameters. For example, where the intervening layer provides an etch stop for the carrier removal process, the latter operation may employ a different polishing or etching process that is more conducive to the removal of the intervening layer than the removal of the device layer. In the case where the thickness of the intervening layer is to be removed to be less than a few hundred nanometers, the removal process may be relatively slow, may be optimized for uniformity across the wafer, and may be more precisely controlled than the process employed to remove the carrier layer. The CMP process employed may, for example, employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or greater) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layer and embedded in the intervening layer (e.g., as electrical isolation between adjacent device regions).

[0121] For embodiments in which the device layer is exposed by completely removing the intervening layer, backside processing can begin on the exposed backside of the device layer or a specific device region therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intervening layer and a device region previously fabricated in the device layer (e.g., a source or drain region).

[0122] In some embodiments where wet and / or plasma etching is used to recess the backside of the carrier layer, intervening layer, or device layer, such etching may be a patterned etch or a material selective etch that imparts significant non-planarity or topography to the backside surface of the device layer. As further described below, patterning may be within a device cell (i.e., "intra-cell" patterning) or may be performed across device cells (i.e., "inter-cell" patterning). In some patterned etch embodiments, at least a portion of the thickness of the intervening layer is employed as a hard mask for backside device layer patterning. Thus, the mask etching process may precede the device layer etching of the corresponding mask.

[0123] The processing scheme described above can produce a donor-host substrate assembly that includes an IC device that exposes the back side of an intermediate layer, the back side of a device layer, and / or the back side of one or more semiconductor regions within a device layer, and / or the front side metallization. Additional backside processing can then be performed on any of these exposed regions during downstream processing.

[0124] It should be understood that the structures produced by the exemplary processing schemes described above can be used in the same or similar form for subsequent processing operations to complete device fabrication (e.g., PMOS and / or NMOS device fabrication). As an example of a completed device, Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0125] refer to Figure 8 , the semiconductor structure or device 800 includes a non-planar active region (e.g., a fin structure including an extended fin portion 804 and a sub-fin region 805) located within a trench isolation region 806. In an embodiment, as indicated by the dotted lines, the non-planar active region is separated into nanowires (e.g., nanowires 804A and 804B) above the sub-fin region 805 instead of a solid fin. In either case, for ease of describing the non-planar integrated circuit structure 800, the non-planar active region 804 is referred to below as the extended fin portion. In an embodiment, as depicted, the sub-fin region 805 also includes a relaxed buffer layer 842 and a defect modification layer 840.

[0126] The gate line 808 is disposed over the extended portion 804 of the non-planar active area (including the surrounding nanowires 804A and 804B, if applicable) and over a portion of the trench isolation region 806. As shown, the gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also include a dielectric cap layer 854. Also visible from this view is the gate contact 814 and the overlying gate contact via 816, along with the overlying metal interconnect 860, all of which are disposed in an interlayer dielectric stack or layer 870. From Figure 8 It can also be seen from the perspective of that in one embodiment, the gate contact 814 is disposed above the trench isolation region 806, but not above the non-planar active region. In another embodiment, the gate contact 814 is located above the non-planar active region.

[0127] In an embodiment, the semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 808 surrounds at least a top surface and a pair of sidewalls of the three-dimensional body.

[0128] Also like Figure 8As depicted in , in an embodiment, an interface 880 exists between the extended fin portion 804 and the sub-fin region 805. The interface 880 can be a transition region between the doped sub-fin region 805 and the lightly doped or undoped upper fin portion 804. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is optionally supplied from an adjacent solid-state doping layer located at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0129] although Figure 8 808, i.e., inside or outside the page. In one embodiment, the material in the source or drain position of the extended fin portion 804 is removed and replaced by another semiconductor material (e.g., by epitaxial deposition) to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 806, i.e., into the sub-fin region 805. According to an embodiment of the present disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin located below the interface 880) suppresses source-to-drain leakage through this portion of the bulk semiconductor fin. In an embodiment, as described above in conjunction with Figure 7J As described, the source and drain regions have associated asymmetric source and drain contact structures.

[0130] Reference again Figure 8 In an embodiment, fins 804 / 805 (and possibly nanowires 804A and 804B) are comprised of a crystalline silicon germanium layer that may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0131] In an embodiment, the trench isolation region 806 and the trench isolation regions (trench isolation structures or trench isolation layers) described throughout the text can be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of a portion of the permanent gate structure from the underlying bulk substrate, or suitable for isolating an active region formed in the underlying bulk substrate (e.g., isolating the fin active region). For example, in one embodiment, the trench isolation region 806 is composed of a dielectric material, such as, but not limited to: silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0132] The gate line 808 may be composed of a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer 852 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer 852 may include a layer of native oxide formed by the top layers of the substrate fin 804. In an embodiment, the gate dielectric layer 852 is composed of a high-k portion at the top and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 852 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, a portion of the gate dielectric is a “U” shaped structure including a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0133] In one embodiment, the gate electrode layer 850 is composed of a metal layer, such as, but not limited to: metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxide. In a specific embodiment, the gate electrode layer 850 is composed of a non-work function setting filling material formed above the metal work function setting layer. Depending on whether the transistor is a PMOS transistor or an NMOS transistor, the gate electrode layer 850 may be composed of a P-type work function metal or an N-type work function metal. In some embodiments, the gate electrode layer 850 may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to: ruthenium, palladium, platinum, cobalt, nickel, tungsten and conductive metal oxides (e.g., ruthenium oxide). The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to: hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). The N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may be composed of a "U"-shaped structure, the U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate, and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In other embodiments of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0134] The spacer associated with the gate electrode stack can be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of the permanent gate structure from an adjacent conductive contact (e.g., a self-aligned contact). For example, in one embodiment, the spacer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0135] The gate contact 814 and the overlying gate contact via 816 may be made of a conductive material. In an embodiment, one or more of the contacts or vias are made of a metallic substance. The metallic substance may be a pure metal (e.g., tungsten, nickel, or cobalt), or may be an alloy (e.g., a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material)).

[0136] In an embodiment (although not shown), a contact pattern is formed that is substantially perfectly aligned to the existing gate pattern 808, while eliminating the use of a photolithography step with an extremely tight registration budget. Figure 7J As described, the contact pattern is a vertically symmetrical contact pattern or an asymmetric contact pattern. In other embodiments, all contacts are front-side connected and are not asymmetric. In one such embodiment, the self-alignment method enables the use of inherently highly selective wet etching (e.g., compared to conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for other critical lithography operations for generating contact patterns as used in conventional methods. In an embodiment, the trench contact grid is not patterned separately, but is formed between polycrystalline (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0137] In an embodiment, providing structure 800 involves making a gate stack structure 808 by a replacement gate process. In such a scheme, the dummy gate material (e.g., polysilicon or silicon nitride pillar material) can be removed and replaced by a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, as opposed to what is done in an earlier process. In an embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etch process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etch process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etch including aqueous phosphoric acid.

[0138] Reference again Figure 8, the arrangement of semiconductor structure or device 800 places the gate contact above the isolation region. Such an arrangement may be viewed as an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region (e.g., above fin 805) and located in the same layer as the trench contact via.

[0139] In an embodiment, for example as described above, Figure 8 The structure in may be included in a structure with a through-stack heat sink for a double-sided device.

[0140] It should be understood that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. In addition, the processes described herein can be used to make one or more semiconductor devices. The semiconductor device can be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for a logic unit or a memory, or a bipolar transistor. In addition, in an embodiment, the semiconductor device has a three-dimensional architecture, for example, a nanowire device, a nanobelt device, a tri-gate device, an independently accessed dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for making semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0141] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or a layer of an insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0142] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. Common examples are lines and structures using copper, which may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term "metal" includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and the like. Therefore, the interconnect may be a single material layer, or may be formed by several layers (including a conductive liner and a filling layer). Any suitable deposition process (e.g., electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In an embodiment, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or an alloy thereof. Interconnects are also sometimes referred to in the art as traces, conductors, wires, metal, or simply interconnects.

[0143] In an embodiment, as also used throughout this specification, the hard mask material, capping layer or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, capping or plug materials can be used in different regions to provide different growth or etching selectivities relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, capping or plug layer includes a layer of silicon nitride (e.g., silicon nitride), or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, capping or plug layers known in the art may be used. The hard mask, capping or plug layer can be formed by CVD, PVD or other deposition methods.

[0144] In an embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), EUV and / or EBDW lithography, etc. Positive or negative photoresists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0145] In another aspect, one or more embodiments are directed to adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may be directed to the integration of multi-width (multiple Wsi) nanowires and nanoribbons in a SAGE architecture and separated by SAGE walls. In an embodiment, the nanowire / nanoribbon is integrated with multiple Wsi in the SAGE architecture portion of the front-end process flow. Such a process flow may involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next-generation transistors with low power and high performance. The associated epitaxial source or drain region may be embedded (e.g., removing portions of the nanowires and then performing source or drain (S / D) growth).

[0146] To provide further context, advantages of the self-aligned gate end cap (SAGE) architecture can include enabling higher layout density and, in particular, scaling diffusion to diffusion pitch. To provide an illustrative comparison, Fig. 9 A cross-sectional view taken through a nanowire and fin is shown for a non-endcap architecture (left hand side (a)) versus a self-aligned gate endcap (SAGE) architecture (right hand side (b)) according to an embodiment of the present disclosure.

[0147] refer to Fig. 9 904, an integrated circuit structure 900 includes a substrate 902 having a fin 904 that extends an amount 906 above an isolation structure 908 that laterally surrounds a lower portion of the fin 904. As depicted, an upper portion of the fin may include a relaxed buffer layer 922 and a defect modification layer 920. A corresponding nanowire 905 is located above the fin 904. A gate structure may be formed above the integrated circuit structure 900 to fabricate a device. However, a break in such a gate structure may be accommodated by increasing the spacing between the fin 904 / nanowire 905 pairs.

[0148] In contrast, reference Fig. 9On the right-hand side (b), the integrated circuit structure 950 includes a substrate 952 having a fin 954, which extends an amount 956 above an isolation structure 958 that laterally surrounds a lower portion of the fin 954. As depicted, the upper portion of the fin may include a relaxed buffer layer 972 and a defect modification layer 970. The corresponding nanowire 955 is located above the fin 954. An isolation SAGE wall 960 (which, as depicted, may include a hard mask thereon) is included within the isolation structure 952 and between adjacent fin 954 / nanowire 955 pairs. The distance between the isolation SAGE wall 960 and the nearest fin 954 / nanowire 955 pair defines a gate end cap spacing 962. A gate structure may be formed above the integrated circuit structure 900 between the isolation SAGE walls to make a device. Breakpoints in such a gate structure are caused by the isolation SAGE walls. Since the isolation SAGE walls 960 are self-aligned, limitations from conventional methods can be minimized to achieve more aggressive diffusion-to-diffusion spacing. In addition, since the gate structure includes breaks at all locations, individual gate structure portions can be layered through local interconnects formed above the isolation SAGE walls 960. In an embodiment, as depicted, the SAGE walls 960 each include a lower dielectric portion and a dielectric cap located on the lower dielectric portion. According to an embodiment of the present disclosure, a dielectric cap for use with Fig. 9 The fabrication process of the associated structures involves using a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0149] In an embodiment, for example as described above, Fig. 9 The structure of part (a) in the embodiment may be included in a structure including a through-stack heat sink for a double-sided device. In an embodiment, for example as described above, Fig. 9 The structure of portion (b) in may be included in a structure having a through-stack heat sink for a double-sided device.

[0150] A self-aligned gate end cap (SAGE) processing scheme involves forming a gate / trench contact end cap that is self-aligned to the fin without requiring additional length to account for mask mismatch. Thus, embodiments may be implemented to achieve a reduction in transistor layout area. Embodiments described herein may involve the fabrication of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolation gate wall, or a self-aligned gate end cap (SAGE) wall.

[0151] In an exemplary processing scheme for a structure having SAGE walls separating adjacent devices, Fig.10 Cross-sectional diagrams representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure having a gate-all-around device are illustrated in accordance with an embodiment of the present disclosure.

[0152] refer to Fig.10 , a starting structure includes a nanowire patterned stack 1004 located above a substrate 1002. A lithographic patterned stack 1006 is formed above the nanowire patterned stack 1004. As depicted, the nanowire patterned stack 1004 includes alternating sacrificial layers 1010 and nanowire layers 1012, which may be located above a relaxed buffer layer 1082 and a defect modification layer 1080. A protective mask 1014 is located between the nanowire patterned stack 1004 and the lithographic patterned stack 1006. In one embodiment, the lithographic patterned stack 1006 is a three-layer mask consisting of a topography mask portion 1020, an anti-reflective coating (ARC) 1022, and a photoresist layer 1024. In a particular such embodiment, the topography mask portion 1020 is a carbon hard mask (CHM) layer, and the anti-reflective coating 1022 is a silicon ARC layer.

[0153] refer to Fig.10 In part (b), the stack of part (a) is photolithographically patterned and then etched to provide an etched structure including a patterned substrate 1002 and trenches 1030.

[0154] refer to Fig.10 1. In part (c), the structure of part (b) has an isolation layer 1040 and a SAGE material 1042 formed in the trench 1030. The structure is then planarized to leave the patterned topographic mask layer 1020' as an exposed upper layer.

[0155] refer to Fig.10 In portion (d), the isolation layer 1040 is recessed below the upper surface of the patterned substrate 1002 , for example, to define an extended fin portion and provide a trench isolation structure 1041 underneath the SAGE wall 1042 .

[0156] refer to Fig.10 In the portion (e), the sacrificial layer 1010 is removed at least in the channel region to release the nanowires 1012A and 1012B. Fig.10 After forming the structure of portion (e) in FIG. 1 , a gate stack can be formed around nanowire 1012B or 1012A, over the extended fins of substrate 1002, and between SAGE walls 1042. In one embodiment, the remaining portion of protective mask 1014 is removed before forming the gate stack. In another embodiment, the remaining portion of protective mask 1014 is retained as an insulating fin cap as an artifact of the processing scheme.

[0157] Reference again Fig.10In portion (e), it should be understood that a channel view is depicted in which the source or drain region is located inside or outside the page. In an embodiment, the channel region including nanowire 1012B has a width that is less than the channel region including nanowire 1012A. Therefore, in an embodiment, the integrated circuit structure includes nanowires of multiple widths (multiple Wsi). Although the structures of 1012B and 1012A can be distinguished as nanowires and nanoribbons, respectively, both such structures are generally referred to as nanowires in this document. It should also be understood that references or depictions of fin / nanowire pairs throughout the text may refer to a fin and one or more overlying nanowires (e.g., Fig.10 According to an embodiment of the present disclosure, the structure of the nanowires is shown in FIG. Fig.10 The fabrication process of the associated structures involves using a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0158] In an embodiment, for example as described above, Fig.10 The structure of portion (e) in may be included in a structure having a through-stack heat sink for a double-sided device.

[0159] In an embodiment, as described throughout, a self-aligned gate end cap (SAGE) isolation structure may be composed of one or more materials suitable for ultimately electrically isolating or contributing to isolating portions of a permanent gate structure from one another. Exemplary materials or material combinations include single material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include a multilayer stack having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride, and an upper portion of a higher dielectric constant material (e.g., hafnium oxide).

[0160] To highlight an exemplary integrated circuit structure having three vertically arranged nanowires, Fig.11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Fig. 11B Shows Fig.11A A cross-sectional source or drain view of a nanowire-based integrated circuit structure taken along the aa' axis. Fig. 11C Shows Fig.11A A cross-sectional source or drain view of a nanowire-based integrated circuit structure taken along the bb' axis.

[0161] refer to Fig.11A, the integrated circuit structure 1100 includes one or more vertically stacked nanowires (1104 groups) located above a substrate 1102. In the depicted embodiment, as depicted, a relaxation buffer layer 1102C, a defect modification layer 1102B, and a lower substrate portion 1102A are included in the substrate 1102. For illustrative purposes, in order to emphasize the nanowire portion, the optional fins located below the bottommost nanowire and formed by the substrate 1102 are not depicted. The embodiments herein are directed to both single-wire devices and multi-wire devices. As an example, for illustrative purposes, three nanowire-based devices with nanowires 1104A, 1104B, and 1104C are shown. For ease of description, nanowire 1104A is used as an example, wherein the description focuses on one nanowire in the nanowire. It should be understood that in the case of describing the properties of one nanowire, the embodiments based on multiple nanowires may have the same or substantially the same properties for each nanowire in the nanowire.

[0162] Each of the nanowires 1104 includes a channel region 1106 in the nanowire. The channel region 1106 has a length (L). Fig. 11C , the channel region also has a perimeter (Pc) orthogonal to the length (L). Fig.11A and Fig. 11C In both cases, the gate electrode stack 1108 surrounds the entire perimeter (Pc) of each of the channel regions 1106. The gate electrode stack 1108 includes a gate electrode and a gate dielectric layer located between the channel region 1106 and the gate electrode (not shown). In an embodiment, the channel region is discrete because it is completely surrounded by the gate electrode stack 1108 without any intervening material (e.g., underlying substrate material or overlying channel fabrication material). Therefore, in an embodiment with multiple nanowires 1104, the channel regions 1106 of the nanowires are also discrete relative to each other.

[0163] refer to Fig.11A and Fig. 11BIn both, the integrated circuit structure 1100 includes a pair of non-discrete source or drain regions 1110 / 1112. The pair of non-discrete source or drain regions 1110 / 1112 are located on either side of a channel region 1106 of a plurality of vertically stacked nanowires 1104. In addition, the pair of non-discrete source or drain regions 1110 / 1112 are adjacent to the channel region 1106 of the plurality of vertically stacked nanowires 1104. In one such embodiment not depicted, due to epitaxial growth on and between nanowire portions extending beyond the channel region 1106, a pair of non-discrete source or drain regions 1110 / 1112 are directly adjacent to the channel region 1106 vertically, wherein the nanowire ends are shown as being within the source or drain structure. In another embodiment, as shown in FIG. Fig.11A As depicted in , a pair of non-discrete source or drain regions 1110 / 1112 indirectly vertically abut the channel region 1106 because they are formed at the ends of the nanowires rather than between the nanowires.

[0164] In an embodiment, as depicted, the source or drain regions 1110 / 1112 are non-discrete because there is not a single and discrete source or drain region for each channel region 1106 of the nanowire 1104. Therefore, in an embodiment having multiple nanowires 1104, the source or drain region 1110 / 1112 of the nanowire is a global or unified source or drain region, as opposed to being discrete for each nanowire. That is, the non-discrete source or drain regions 1110 / 1112 are global in the sense that a single unified feature is used as the source or drain region for multiple (in this case, 3) nanowires 1104, and more specifically, for more than one discrete channel region 1106. In one embodiment, from a cross-sectional perspective orthogonal to the length of the discrete channel region 1106, as shown in FIG. Fig. 11B As depicted in FIG. 1 , each of a pair of non-discrete source or drain regions 1110 / 1112 is generally rectangular in shape having a bottom tapered portion and a top vertex portion. However, in other embodiments, the source or drain regions 1110 / 1112 of the nanowire are relatively larger and discrete non-vertically merged epitaxial structures, such as a combination of Figure 7A-7J The protrusion described.

[0165] According to the embodiments of the present disclosure, and as Fig.11A and Fig. 11BAs depicted in , the integrated circuit structure 1100 also includes a pair of contacts 1114, each contact 1114 being located on one of the pair of non-discrete source or drain regions 1110 / 1112. In one such embodiment, each contact 1114 completely surrounds the corresponding non-discrete source or drain region 1110 / 1112 in a vertical sense. In another aspect, as Fig. 11B As depicted in FIG, the entire perimeter of the non-discrete source or drain region 1110 / 1112 may not be in contact with the contact 1114, and the contact 1114 therefore only partially surrounds the non-discrete source or drain region 1110 / 1112. In a non-depicted comparative embodiment, the entire perimeter of the non-discrete source or drain region 1110 / 1112 is surrounded by the contact 1114, as taken along the a-a' axis.

[0166] Reference again Fig.11A In an embodiment, the integrated circuit structure 1100 further includes a pair of spacers 1116. As depicted, outer portions of the pair of spacers 1116 may overlap portions of the non-discrete source or drain regions 1110 / 1112, thereby providing "embedded" portions of the non-discrete source or drain regions 1110 / 1112 under the pair of spacers 1116. Also as depicted, the embedded portions of the non-discrete source or drain regions 1110 / 1112 may not extend under the entirety of the pair of spacers 1116.

[0167] Substrate 1102 may be made of a material suitable for integrated circuit structure fabrication. In one embodiment, substrate 1102 includes a lower bulk substrate made of a single crystal material, which may include, but is not limited to: silicon, germanium, silicon-germanium, germanium-tin, silicon-germanium-tin, or a III-V compound semiconductor material. An upper insulator layer is located on the lower bulk substrate, and the upper insulator layer is made of a material that may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. Therefore, structure 1100 can be made from a starting insulator-on-semiconductor substrate. Alternatively, structure 1100 is formed directly from a bulk substrate, and local oxidation is used to form an electrically insulating portion to replace the above-mentioned upper insulator layer. In another alternative embodiment, structure 1100 is formed directly from a bulk substrate, and doping is used to form an electrically isolated active region (e.g., a nanowire) thereon. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an Ω-FET type structure.

[0168] In an embodiment, the nanowires 1104 may be sized as wires or ribbons (as described below) and may have square or rounded corners. In an embodiment, the nanowires 1104 are made of materials such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single crystalline. For example, for silicon nanowires 1104, the single crystalline nanowires may be based on a (100) global orientation, for example, having a 100 μm diameter in the z direction. <100> Plane. Other orientations are also contemplated as described below. In an embodiment, the dimensions of nanowire 1104 are nanometer-scale from a cross-sectional perspective. For example, in a particular embodiment, the smallest dimension of nanowire 1104 is less than about 20 nanometers. In an embodiment, nanowire 1104 is composed of strained material, particularly in channel region 1106.

[0169] refer to Fig. 11C In an embodiment, each of the channel regions 1106 has a width (Wc) and a height (Hc), and the width (Wc) is substantially the same as the height (Hc). That is, in both cases, the cross-sectional profile of the channel regions 1106 is square, or if rounded, the cross-sectional profile of the channel regions 1106 is circular. In another aspect, for example, as described throughout for nanoribbons, the width and height of the channel regions need not be the same.

[0170] In an embodiment, as described throughout, an integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or tri-gate device having a corresponding one or more overlying nanowire structures. In such an embodiment, the corresponding semiconductor channel region is comprised of or formed in a three-dimensional body, wherein one or more discrete nanowire channel portions overly the three-dimensional body. In one such embodiment, the gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, and also surrounds each of the one or more discrete nanowire channel portions.

[0171] In an embodiment, for example as described above, Figure 11A-11C The structure in may be included in a structure with a through-stack heat sink for a double-sided device.

[0172] In an embodiment, as described throughout, the underlying substrate may be composed of a semiconductor material that can withstand the manufacturing process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate, which is composed of a crystalline silicon, silicon / germanium or germanium layer doped with charge carriers to form an active region, the charge carriers being, for example, but not limited to: phosphorus, arsenic, boron, gallium or a combination thereof. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a different crystalline substrate, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate may alternatively be composed of a III-V group material. In an embodiment, the bulk substrate is composed of a III-V group material, the III-V group material being, for example, but not limited to: gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide or a combination thereof. In one embodiment, the bulk substrate is composed of a Group III-V material and the charge carrier dopant impurity atoms are, for example, but not limited to, impurity atoms of carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0173] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to: processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, etc. The integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0174] Fig.12 A computing device 1200 is shown in accordance with one implementation of an embodiment of the present disclosure. The computing device 1200 houses a board 1202. The board 1202 may include a plurality of components, including, but not limited to, a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the board 1202. In some implementations, the at least one communication chip 1206 is also physically and electrically coupled to the board 1202. In further implementations, the communication chip 1206 is part of the processor 1204.

[0175] Depending on the application of the computing device 1200, the computing device 1200 may include other components that may or may not be physically and electrically coupled to the board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (e.g., hard disk drive, compact disc (CD), digital versatile disc (DVD), etc.).

[0176] The communication chip 1206 can implement wireless communications for transmitting data to and from the computing device 1200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments, they may not contain wires. The communication chip 1206 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. The computing device 1200 may include multiple communication chips 1206. For example, the first communication chip 1206 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, while the second communication chip 1206 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0177] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. The integrated circuit die of the processor 1204 may include one or more structures constructed according to implementations of embodiments of the present disclosure, for example, a full-surround gate integrated circuit structure with a through-stack heat sink for a double-sided device. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0178] The communication chip 1206 also includes an integrated circuit die packaged within the communication chip 1206. The integrated circuit die of the communication chip 1206 may include one or more structures constructed according to implementations of embodiments of the present disclosure, such as a gate-all-around integrated circuit structure with a through-stack heat spreader for double-sided devices.

[0179] In further embodiments, another component housed within computing device 1200 may contain an integrated circuit die including one or more structures constructed in accordance with embodiments of the present disclosure, such as a fully-around-gate integrated circuit structure with a through-stack heat sink for a double-sided device.

[0180] In various embodiments, computing device 1200 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, computing device 1200 may be any other electronic device that processes data.

[0181] Fig.13 An interposer 1300 including one or more embodiments of the present disclosure is shown. Interposer 1300 is an intermediate substrate for bridging a first substrate 1302 to a second substrate 1304. For example, first substrate 1302 may be an integrated circuit die. Second substrate 1304 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 1300 is to extend connections to a wider spacing or to rewire connections to different connections. For example, interposer 1300 may couple an integrated circuit die to a ball grid array (BGA) 1306, which may then be coupled to second substrate 1304. In some embodiments, first substrate 1302 and second substrate 1304 are attached to opposite sides of interposer 1300. In other embodiments, first substrate 1302 and second substrate 1304 are attached to the same side of interposer 1300. And in further embodiments, three or more substrates are interconnected through interposer 1300.

[0182] The interposer 1300 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In other embodiments, the interposer 1300 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0183] The interposer 1300 may include metal interconnects 1308 and vias 1310, including but not limited to through silicon vias (TSVs) 1312. The interposer 1300 may also include embedded devices 1314, including both passive devices and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1300. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used for the fabrication of the interposer 1300 or for fabricating components included in the interposer 1300.

[0184] In another aspect, in an embodiment, the structures described herein are suitable for use as high bandwidth (HBW) devices that can operate at low temperatures (e.g., in the range of -77 degrees Celsius to 0 degrees Celsius). In one embodiment, a thermal regulator / refrigeration device is coupled to a common board having a device with structures (e.g., those described herein coupled thereto). In one embodiment, the thermal regulator device and / or the refrigeration device are included on a processing device having structures (e.g., those described herein). In an embodiment, the structures described herein implement a zetta-unit of compute (Zuoc), for example, to enable operation at low temperatures, etc.

[0185] It should be understood that the structures described herein can operate at low temperatures (e.g., in the range of -77 degrees Celsius to 0 degrees Celsius). In one embodiment, the thermal regulator / refrigeration device is coupled to a common board having a device with structures (such as those described herein coupled thereto), such as described below in conjunction with Fig.14A In one embodiment, a heat regulator device and / or a refrigeration device is included on a processing device having a structure (such as those described herein), such as the following in conjunction with Fig. 14B As described.

[0186] Fig.14A A computing device 1400 is shown in accordance with one implementation of an embodiment of the present disclosure. The computing device 1400 houses a board. The board may include a plurality of components, including, but not limited to, a processing device 1402. The computing device 1400 may also include a communication chip 1412. In one embodiment, the processing device 1402 is physically and electrically coupled to the board. In some implementations, the communication chip 1412 is also physically and electrically coupled to the board. In further implementations, the communication chip 1412 is part of the processing device 1402.

[0187] Depending on the application of computing device 1400, computing device 1400 may include other components that may or may not be physically and electrically coupled to the board. These other components may include, but are not limited to: memory 1404 (e.g., volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), or flash memory), antenna 1422, display device 1406, battery / power supply 1414, audio output device 1408, audio input device 1418, global positioning system (GPS) device 1416, other output devices 1410 (e.g., video output), other input devices 1420 (e.g., video input), security interface device 1421, and / or testing devices. In one embodiment, thermal regulation / cooling device 1411 is included and coupled to the board, for example, a device including actively cooled copper channels.

[0188] The communication chip 1412 is capable of wireless communication for transmitting data to and from the computing device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments, they may not contain wires. The communication chip 1412 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. The computing device 1400 may include multiple communication chips 1412. For example, the first communication chip 1412 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, while the second communication chip 1412 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0189] The processing device 1402 of the computing device 1400 may include an integrated circuit die in a package. The processing device 1402 may include one or more structures constructed according to implementations of embodiments of the present disclosure, for example, a full-surround gate integrated circuit structure with a through-stack heat sink for a double-sided device. The term "processing device" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0190] Fig. 14B A processing device according to one implementation of an embodiment of the present disclosure is shown. Fig. 14B , the exemplary processing device 1402 includes a memory region, a logic region, a communication device region, an interconnect and redistribution layer (RDL) and metal-insulator-metal (MIM) region, a cooling device region, a thermal regulator region, a battery / power regulator region, and a hardware security device region. In one embodiment, the cooling device region and / or the thermal regulator region is a region including an actively cooled copper channel.

[0191] Thus, embodiments of the present disclosure include integrated circuit structures having through-stack heat sinks for double-sided devices, and methods of making integrated circuit structures having through-stack heat sinks for double-sided devices.

[0192] The above description of the illustrated implementations of the embodiments of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art.

[0193] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the appended claims should not be interpreted as limiting the present disclosure to the specific embodiments disclosed in the specification and claims. On the contrary, the scope of the present disclosure is determined entirely by the appended claims, which will be interpreted according to the established principles of claim interpretation.

[0194] Example embodiment 1: An integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based transistors and a plurality of metallization layers located above the plurality of fin-based transistors. A back side structure is located below the plurality of fin-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermally conductive via extends from a location located at or below a bottom of the plurality of fin-based transistors to a location located on or into the carrier wafer or substrate.

[0195] Example Embodiment 2: The integrated circuit structure according to Example Embodiment 1, wherein the thermally conductive via comprises a dielectric liner and a conductive filler.

[0196] Example Embodiment 3: The integrated circuit structure according to Example Embodiment 2, wherein the conductive filler is selected from the group consisting of a copper filler, a tungsten filler, or a polysilicon filler.

[0197] Example Embodiment 4: The integrated circuit structure of Example Embodiment 1, 2, or 3, wherein the thermally conductive via does not electrically couple the electrical features.

[0198] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3 or 4, wherein the thermally conductive via is electrically floating.

[0199] Example embodiment 6: An integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of nanowire-based transistors and a plurality of metallization layers located above the plurality of nanowire-based transistors. A back side structure is located below the plurality of nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermally conductive via extends from a location located at or below the bottom of the plurality of nanowire-based transistors to a location located on or into the carrier wafer or substrate.

[0200] Example Embodiment 7: The integrated circuit structure according to Example Embodiment 6, wherein the thermally conductive via comprises a dielectric liner and a conductive filler.

[0201] Example Embodiment 8: The integrated circuit structure according to Example Embodiment 6 or 7, wherein the conductive filler is selected from the group consisting of a copper filler, a tungsten filler, or a polysilicon filler.

[0202] Example Embodiment 9: The integrated circuit structure of Example Embodiment 6, 7, or 8, wherein the thermally conductive via does not electrically couple the electrical features.

[0203] Example Embodiment 10: The integrated circuit structure of Example Embodiment 6, 7, 8 or 9, wherein the thermally conductive via is electrically floating.

[0204] Example embodiment 11: A computing device, comprising: a board and a component coupled to the board. The component comprises an integrated circuit structure, the integrated circuit structure comprising a front side structure. The front side structure comprises a device layer having a plurality of fin-based or nanowire-based transistors and a plurality of metallization layers located above the plurality of fin-based or nanowire-based transistors. A back side structure is located below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermally conductive via extends from a location located at or below a bottom of the plurality of fin-based or nanowire-based transistors to a location located on or into the carrier wafer or substrate.

[0205] Example 12: The computing device according to Example 11 includes a plurality of fin-based transistors.

[0206] Example Embodiment 13: A computing device according to Example Embodiment 11, comprising a plurality of nanowire-based transistors.

[0207] Exemplary Embodiment 14: The computing device of Exemplary Embodiment 11, 12 or 13, further comprising a memory coupled to the board.

[0208] Exemplary Embodiment 15: The computing device of Exemplary Embodiment 11, 12, 13 or 14, further comprising a communication chip coupled to the board.

[0209] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14 or 15, wherein the component is a packaged integrated circuit die.

[0210] Exemplary Embodiment 17: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15 or 16, further comprising a battery coupled to the board.

[0211] Exemplary Embodiment 18: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a display coupled to the board.

[0212] Exemplary Embodiment 19: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, further comprising a camera coupled to the board.

[0213] Exemplary Embodiment 20: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: A front side structure, the front side structure comprising: a device layer comprising a plurality of fin-based transistors; and a plurality of metallization layers overlying the plurality of fin-based transistors; a backside structure underlying the plurality of fin-based transistors; a carrier wafer or substrate bonded to the front side structure; and A thermally conductive via extends from a location at or below a bottom of the plurality of fin-based transistors to a location on or into the carrier wafer or substrate.

2. The integrated circuit structure according to claim 1, wherein: The thermally conductive via includes a dielectric liner and a conductive filler.

3. The integrated circuit structure according to claim 2, wherein: The conductive filler is selected from the group consisting of a copper filler, a tungsten filler, or a polysilicon filler.

4. The integrated circuit structure according to claim 1, 2 or 3, wherein: The thermally conductive via does not electrically couple electrical features.

5. The integrated circuit structure according to claim 1, 2 or 3, wherein: The thermally conductive via is electrically floating.

6. An integrated circuit structure comprising: A front side structure, the front side structure comprising: a device layer comprising a plurality of nanowire-based transistors; and a plurality of metallization layers overlying the plurality of nanowire-based transistors; a backside structure underlying the plurality of nanowire-based transistors; a carrier wafer or substrate bonded to the front side structure; and A thermally conductive via extends from a location at or below a bottom of the plurality of nanowire-based transistors to a location on or into the carrier wafer or substrate.

7. The integrated circuit structure according to claim 6, wherein: The thermally conductive via includes a dielectric liner and a conductive filler.

8. The integrated circuit structure according to claim 6 or 7, wherein: The conductive filler is selected from the group consisting of a copper filler, a tungsten filler, or a polysilicon filler.

9. The integrated circuit structure according to claim 6 or 7, wherein: The thermally conductive via does not electrically couple electrical features.

10. The integrated circuit structure according to claim 6 or 7, wherein: The thermally conductive via is electrically floating.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: A front side structure, the front side structure comprising: a device layer comprising a plurality of fin-based or nanowire-based transistors; and a plurality of metallization layers over the plurality of fin-based or nanowire-based transistors; a backside structure underlying the plurality of fin-based or nanowire-based transistors; a carrier wafer or substrate bonded to the front side structure; and A thermally conductive via extends from a location at or below a bottom of the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.

12. The computing device of claim 11, comprising the plurality of fin-based transistors.

13. The computing device of claim 11, comprising the plurality of nanowire-based transistors.

14. The computing device of claim 11, 12 or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12 or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12 or 13, wherein: The component is a packaged integrated circuit die.

17. The computing device of claim 11, 12 or 13, further comprising: A battery coupled to the board.

18. The computing device of claim 11, 12 or 13, further comprising: A display is coupled to the panel.

19. The computing device of claim 11, 12 or 13, further comprising: A camera is coupled to the board.

20. The computing device of claim 11, 12 or 13, wherein: The component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

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