Chip packaging structure and method integrating CIS-TSV technology and FOPLP technology

Abstract

The invention relates to a structure and a method for preparing a wafer-level system packaging chip by utilizing Hybrid Bonding and FOWLP technologies. According to the packaging structure and method, the integration of the CIS chip and other types of chips can be realized, the packaging process is completed through the FOWLP technology, the integration of different types of chips is realized, the packaging efficiency can be greatly improved, and the processing cost is remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a chip packaging structure and method integrating CIS-TSV technology and FOPLP technology. Background Art

[0002] Image sensor chip (CMOS Inage Sensor, CIS) is an image sensor based on semiconductor CMOS technology, which began to be widely used in the late 1990s. At present, CIS chips have been widely used in many fields such as mobile phones, cameras, automotive electronics, and security. As mobile consumer electronic products such as mobile phones, computers, and digital cameras have higher and higher requirements for the packaging of high-performance, low-power, miniaturized, heterogeneous process integration, and low-cost system integrated electronic products, high-density, multi-type chip system-level packaging products have gradually become mainstream in the new generation of electronic products. At present, CIS chips are mainly prepared by wafer-level packaging CIS-TSV technology.

[0003] The difference between the process flow of Fan Out Panel Level Package (FOPLP) and FOWLP is that it uses a larger panel instead of a wafer, and there are differences in the materials, equipment, and line width and line spacing of the products used. The emergence of FOPLP technology can effectively achieve a larger overall packaging area, further increase packaging efficiency, reduce packaging costs, and have broader development prospects. At present, the size of FOPLP samples has gradually developed from the initial 300*300mm to 500*500mm, 600*600mm, and even larger package sizes. Compared with FOWLP technology, FOPLP technology has the advantages of lower cost, flexible design, good electrothermal performance, diverse business models and a wide range of application fields.

[0004] Based on the respective advantages of CIS-TSV technology and FOPLP technology, how to integrate CIS-TSV technology with FOPLP technology and prepare high-density, multi-type chip system packaging electronic products with high performance, low power consumption, miniaturization, heterogeneous process integration and low cost is gradually becoming a hot technology in the field of chip packaging research. Summary of the invention

[0005] In order to solve the above technical problems, the purpose of the present invention is to provide a chip packaging structure and method integrating CIS-TSV technology and FOPLP technology. The packaging structure and method can realize the integration of CIS-TSV technology and FOPLP technology, and can greatly improve the packaging efficiency and significantly reduce the processing cost while realizing the integration of different types of chips.

[0006] In order to achieve the above technical objectives and the above technical effects, the present invention is implemented by the following technical scheme, which mainly includes the following steps:

[0007] S1, forming a cofferdam structure on a wafer-level glass carrier plate;

[0008] S2, bonding the wafer-level CIS chip to the wafer-level glass carrier plate;

[0009] S3, forming a conductive through-hole structure on the back side of the wafer-level CIS chip;

[0010] S4, forming a first metal redistribution layer on the back side of the wafer-level CIS chip;

[0011] S5, pasting multiple wafer-level CIS chips on a board-level carrier to form a board-level composite;

[0012] S6, forming a first plastic sealing layer on the board-level composite;

[0013] S7, pasting a second chip on the board-level complex;

[0014] S8, forming a second plastic sealing layer on the board-level composite;

[0015] S9, forming a conductive through-hole structure on the second plastic packaging layer on the board-level composite;

[0016] S10, forming a second metal filling wiring layer on the board-level composite;

[0017] S11, forming an insulating layer and a conductive structure through hole on the board-level composite;

[0018] S12, forming a third metal redistribution layer (i.e., a pad) on the board-level composite;

[0019] S13, planting balls on the third metal redistribution layer of the board-level complex;

[0020] S14, removing the board-level carrier plate and the adhesive film from the board-level composite;

[0021] S15, cutting to obtain a single Die.

[0022] The material of the metal redistribution layer in steps S4, S10 and S13 is one or a combination of two or more of aluminum, copper, gold, platinum, nickel and tin. In the present embodiment, the material of the metal redistribution layer of the insulating layer is copper. The material of the insulating layer in step S11 is epoxy resin, silicon oxide insulating material or other insulating materials. In the present embodiment, the insulating layer material is photosensitive epoxy resin.

[0023] The present invention provides a chip packaging structure and method integrating CIS-TSV technology and FOPLP technology. It integrates CIS-TSV technology and FOPLP technology to prepare high-density, multi-type chip system packaging electronic products with high performance, low power consumption, miniaturization, heterogeneous process integration, and low cost.

[0024] According to another aspect of the present invention, a chip packaging structure integrating CIS-TSV technology and FOPLP technology prepared according to the above method comprises a wafer-level glass carrier plate (10) and a wafer-level CIS chip (12); a cofferdam structure (11) is provided on the wafer-level glass carrier plate (10);

[0025] Bonding the wafer-level CIS chip (12) to a wafer-level glass carrier plate (10);

[0026] A conductive through-hole structure (204) is provided on the back side of the bonded wafer-level CIS chip;

[0027] A first metal redistribution layer (15) is provided at the conductive through-hole structure (204), and a plurality of wafer-level CIS chips provided with the first metal redistribution layer (15) are adhered to a board-level carrier board (301) to form a board-level composite body; and a first plastic sealing layer (16) is provided on the board-level composite body;

[0028] Pasting a second chip (19) on the first plastic sealing layer (16) of the board-level composite body; forming a second plastic sealing layer (207) on the second chip (19) of the board-level composite body;

[0029] Providing a conductive through-hole structure (208, 209) on the second plastic packaging layer (207) on the board-level composite;

[0030] Forming a second metal-filled wiring layer (21) on the conductive through-hole structure (208, 209) of the board-level composite;

[0031] An insulating layer (22) and a conductive structure through hole (211) are provided on the second metal-filled wiring layer (21) of the board-level composite body;

[0032] A third metal redistribution layer (23) is arranged on the insulating layer (22) and the conductive structure through hole (211) of the board-level complex; a ball is implanted on the third metal redistribution layer (23) of the board-level complex, and the board-level carrier plate and the adhesive film are removed from the board-level complex; and a single chip is obtained by cutting.

[0033] The beneficial effects of the present invention are mainly the following three points: (1) Integrate wafer-level packaging technology with board-level packaging technology to fully utilize wafer-level packaging equipment and technology and board-level packaging equipment and technology. (2) Integrate CIS chips with other types of chips (second chips) to achieve high-performance, low-power, miniaturized, heterogeneous process integration, and low-cost system integrated electronic products. (3) Most of the process flows in the entire packaging process are board-level packaging, which has high packaging efficiency, low cost, and large production capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A cofferdam structure is formed on a wafer-level high-transmittance glass carrier plate.

[0035] Figure 2 For the general Figure 1 Schematic diagram of the structure shown being bonded to a wafer-level CIS chip through a pressing process.

[0036] Figure 3 For the general Figure 2 In the structure shown, the back side of the wafer-level CIS chip is thinned and a conductive through-hole structure is formed at a position corresponding to the Al Pad structure.

[0037] Figure 4 For Figure 3 A first metal redistribution layer is formed at the conductive via structure in the wafer-level structure.

[0038] Figure 5 For the general Figure 3 Schematic diagram of the wafer-level structure being pasted on a carrier plate.

[0039] Figure 6 For Figure 5 The board-level composite is bonded onto the wafer to form a first plastic packaging layer.

[0040] Figure 7 It is a schematic diagram of the Die structure of the upper part of the board-level complex.

[0041] Figure 8 For Figure 7 The schematic diagram of the structure of the second chip pasted on the first plastic packaging layer of the board-level complex is shown.

[0042] Fig. 9 For Figure 8 A second plastic packaging layer is formed on the board-level composite.

[0043] Fig.10 For Fig. 9 A related conductive through-hole structure is formed on the second plastic packaging layer of the board-level composite.

[0044] Fig.11 For Fig.10 A second metal redistribution layer is formed on the board-level composite.

[0045] Fig.12 For Fig.11 An insulating layer and a conductive via structure are formed on the board-level composite.

[0046] Fig.13 For Fig.12 A third metal redistribution layer is formed on the board-level composite structure.

[0047] Fig.14 For Fig.13 The ball planting process is formed on the board-level complex shown.

[0048] Fig.15 To dismantle Fig.14 Schematic diagram of the board-level composite carrier board and adhesive film shown.

[0049] Fig.16 To obtain Fig.16 Schematic diagram of a single chip with the structure shown. DETAILED DESCRIPTION

[0050] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0051] (1) Figure 1 The cofferdam structure is formed on the wafer-level high-transmittance glass carrier plate as shown in FIG. Figure 1 a. 10 is a wafer-level high-transmittance glass carrier plate, 11 is a cofferdam structure. 201 is the lower surface of the wafer-level high-transmittance glass carrier plate, and 202 is the upper surface of the wafer-level high-transmittance glass carrier plate. Figure 1 The cofferdam structure shown in the figure is formed with a glue layer by a glue rolling or glue printing process to obtain the following Figure 1 b. Wherein 11b is the adhesive layer. (The adhesive layer 11 is relatively thin and will not be specifically shown in the subsequent steps)

[0052] (2) Figure 1 The structure shown is bonded with a wafer-level CIS chip (8-inch or 12-inch) through a press bonding process to obtain the following Figure 2 The structure shown in the figure is described by taking the partial Die structure in the wafer-level sample as an example. 12 is the wafer-level CIS chip, 13 is the conductive structure of the wafer-level CIS chip (i.e., Al Pad), 14 is the photosensitive area of ​​the wafer-level CIS chip, and 203 is the lower surface of the wafer-level CIS chip.

[0053] (3) Figure 2 In the structure shown, the back side of the wafer-level CIS chip is thinned, and a conductive through-hole structure is formed at a position corresponding to the Al Pad structure, so as to obtain Figure 3 The structure shown in FIG. 204 is a conductive through-hole structure.

[0054] (4) Figure 3 A first metal redistribution layer is formed at the conductive via structure in the wafer-level structure shown in FIG. Figure 4 The structure shown in FIG. 15 is the first metal redistribution layer.

[0055] (5) Figure 3 The wafer-level structure shown is pasted on a carrier plate (glass carrier plate facing downward), and the Figure 5 The structure shown in FIG. 301 is a carrier plate, 302 is an adhesive film, and 303 is a wafer-level structure. In this step, the size of the carrier plate is usually 2, 4 or more times the size of the wafer-level structure. In this embodiment, the size of the carrier plate is 4 times that of the wafer-level structure, that is, 4 wafer-level structures can be attached to the carrier plate at the same time, thereby obtaining a board-level composite structure. The top view of the board-level composite structure is shown in FIG. Figure 5 As shown in a, the side view of the plate-level complex is shown in Figure 5 b. Wherein 205 is the lower surface of the bearing plate.

[0056] (6) In Figure 5 The board-level composite body shown in the figure is pasted on the wafer to form a first plastic sealing layer, and the Figure 6 The structure shown in FIG. 16 is a first plastic sealing layer, and 206 is an upper surface of the plastic sealing layer.

[0057] (7) Figure 7 The figure shows a schematic diagram of the upper Die structure of the board-level complex, and the subsequent steps are described based on this structure. 10 is a glass carrier board, 11 is a cofferdam structure, 12 is a CIS chip, 13 is a CIS chip conductive structure (i.e., Al Pad), 14 is a CIS chip photosensitive area, 15 is a first metal redistribution layer, 16 is a first plastic layer, 205 is the lower surface of the carrier board, and 206 is the upper surface of the first plastic layer.

[0058] (8) Figure 7 The second chip (the second chip is usually a non-CIS chip) is attached to the first plastic packaging layer of the board-level composite body as shown in FIG. Figure 8 The structure shown in FIG. 17 is an adhesive film layer, 18 is a second chip, and 19 is a conductive structure of the second chip (ie, Al Pad).

[0059] (9) Figure 8 A second plastic encapsulation layer is formed on the board-level composite body to obtain Fig. 9 The structure shown in FIG. 20 is the second plastic sealing layer, and 207 is the upper surface of the second plastic sealing layer.

[0060] (10) Fig. 9 A related conductive through-hole structure is formed on the second plastic packaging layer of the board-level composite body as shown in FIG. Fig.10The structure shown. 208 and 209 are related conductive via structures. It is worth noting that the conductive via structure 209 must correspond to the second chip conductive structure 19, and the location of the conductive via structure 208 must be staggered with the location of the second chip conductive structure 19.

[0061] (11) Fig.10 A second metal redistribution layer is formed on the board-level composite body as shown, and a Fig.11 The structure shown in FIG. 21 is a second metal redistribution layer.

[0062] (12) Fig.11 An insulating layer and a conductive through-hole structure are formed on the board-level composite body as shown in FIG. Fig.12 The structure shown in FIG. 22 is an insulating layer, 210 is an upper surface of the insulating layer, and 211 is a conductive through-hole structure formed on the insulating layer.

[0063] (13) Fig.12 A third metal redistribution layer is formed on the board-level composite structure as shown, and a Fig.13 The structure shown in FIG. 23 is the third metal redistribution layer.

[0064] (14) Fig.13 The ball implantation process is formed on the board-level complex as shown, and the Fig.14 The structure shown in FIG. 24 is a conductive structure (i.e., solder ball).

[0065] (15) Demolition Fig.14 The board-level composite carrier board and adhesive film shown in the figure are obtained as Fig.15 The structure shown.

[0066] (16) is cut to obtain Fig.16 A single chip with the structure shown.

[0067] like Fig.16 As shown in the structure, the present embodiment prepares a system integrated electronic product with high performance, low power consumption, miniaturization, heterogeneous process integration and low cost by integrating CIS-TSV technology and FOPLP technology. The specific layers in the structure are as follows: 10-glass carrier plate, 11-cofferdam structure, 12-CIS chip, 13-CIS chip conductive structure (Al Pad), 14-CIS chip photosensitive area, 15-first metal redistribution layer, 16-first plastic sealing layer, 17-adhesive film, 18-second chip, 19-second chip conductive structure (Al Pad), 20-second plastic sealing layer, 21-second metal redistribution layer, 22-insulating layer, 23-third metal redistribution layer, 24-conductive structure (tin ball).

[0068] It is worth noting that: in the description of the present invention, the meaning of "multiple" is two or more than two, unless otherwise clearly and specifically defined. In the present invention, unless otherwise clearly stipulated and defined, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; the circuits described in the present invention are all commonly used circuits in the art, and other related components are all existing commonly used components. For ordinary technicians in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0069] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes that fall within the meaning and scope of the elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

Claims

1. A chip packaging method integrating CIS-TSV technology and FOPLP technology, characterized in that: The steps include: S1, forming a cofferdam structure on a wafer-level glass carrier plate; S2, bonding the wafer-level CIS chip to the wafer-level glass carrier plate; S3, forming a conductive through-hole structure on the back side of the wafer-level CIS chip; S4, forming a first metal redistribution layer on the back side of the wafer-level CIS chip; S5, pasting multiple wafer-level CIS chips on a board-level carrier to form a board-level composite; S6, forming a first plastic sealing layer on the board-level composite; S7, pasting a second chip on the board-level complex; S8, forming a second plastic sealing layer on the board-level composite; S9, forming a conductive through-hole structure on the second plastic packaging layer on the board-level composite; S10, forming a second metal filling wiring layer on the board-level composite; S11, forming an insulating layer and a conductive structure through hole on the board-level composite; S12, forming a third metal redistribution layer on the board-level composite; S13, planting balls on the third metal redistribution layer of the board-level complex; S14, removing the board-level carrier plate and the adhesive film from the board-level composite; S15, cutting to obtain a single Die.

2. The method according to claim 1, characterized in that: The material of the metal redistribution layer in steps S4, S10 and S13 is one or a combination of two or more of aluminum, copper, gold, platinum, nickel and tin.

3. The method according to claim 1, characterized in that: The material of the insulating layer in step S11 is epoxy resin or silicon oxide insulating material.

4. The method according to claim 1, characterized in that: The method integrates CIS-TSV technology and FOPLP technology to prepare high-density, multi-type chip system packaging electronic products with the characteristics of high performance, low power consumption, miniaturization, heterogeneous process integration and low cost.

5. The chip packaging structure integrating CIS-TSV technology and FOPLP technology prepared by the method according to claim 1, characterized in that: It comprises a wafer-level glass carrier plate (10) and a wafer-level CIS chip (12); a cofferdam structure (11) is provided on the wafer-level glass carrier plate (10); Bonding the wafer-level CIS chip (12) to a wafer-level glass carrier plate (10); A conductive through-hole structure (204) is provided on the back side of the bonded wafer-level CIS chip; A first metal redistribution layer (15) is provided at the conductive through-hole structure (204), and a plurality of wafer-level CIS chips provided with the first metal redistribution layer (15) are adhered to a board-level carrier board (301) to form a board-level composite body; and a first plastic sealing layer (16) is provided on the board-level composite body; Pasting a second chip (19) on the first plastic sealing layer (16) of the board-level composite body; forming a second plastic sealing layer (207) on the second chip (19) of the board-level composite body; Providing a conductive through-hole structure (208, 209) on the second plastic packaging layer (207) on the board-level composite; Forming a second metal-filled wiring layer (21) on the conductive through-hole structure (208, 209) of the board-level composite; An insulating layer (22) and a conductive structure through hole (211) are provided on the second metal-filled wiring layer (21) of the board-level composite body; A third metal redistribution layer (23) is arranged on the insulating layer (22) and the conductive structure through hole (211) of the board-level complex; a ball is implanted on the third metal redistribution layer (23) of the board-level complex, and the board-level carrier plate and the adhesive film are removed from the board-level complex; and a single chip is obtained by cutting.

6. The chip packaging structure integrating CIS-TSV technology and FOPLP technology according to claim 5, characterized in that: An adhesive layer (11) is formed on the cofferdam structure by means of a glue rolling or glue printing process.

7. The chip packaging structure integrating CIS-TSV technology and FOPLP technology according to claim 5, characterized in that: The wafer-level glass carrier plate (10) and the wafer-level CIS chip (12) are bonded by a pressing process; the back side of the bonded wafer-level CIS chip is thinned, and a conductive through-hole structure is formed at a position corresponding to the conductive structure (13) of the wafer-level CIS chip.

8. The chip packaging structure integrating CIS-TSV technology and FOPLP technology according to claim 5, characterized in that: The conductive through hole structure (209) must correspond to the second chip conductive structure (19), and the location of the conductive through hole structure (208) must be staggered with the location of the second chip conductive structure (19).

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