TBC battery and preparation method thereof

Abstract

The invention relates to a TBC battery and a preparation method thereof. The preparation method comprises the following steps: S1, forming a dielectric region and a polycrystalline silicon layer; s2, forming a dopant source layer and a mask layer of the first conductive type impurities; s3, opening the film and cleaning; and S4, one-step co-doping of impurities of different conductive types. According to the invention, the dopant source layer and the mask layer of the first conductive type impurities are deposited in sequence, so that the PN region film opening is enlarged, and the window is cleaned; the dopant source layer of the first conductive type impurity can be made into an extremely thin high-concentration layer, so that the oxygen content of the silicon substrate is reduced, the recombination is reduced, the recombination of carriers in the solar cell is reduced, the photoelectric conversion efficiency is improved, the light-induced degradation phenomenon can be reduced, and meanwhile, boron doping at a relatively low temperature can be matched.

Description

Technical Field

[0001] The present invention relates to the field of TBC batteries, and in particular to a TBC battery and a preparation method thereof. Background Art

[0002] The IBC (Interdigitated Back Contact) cell and the TOPcon (Tunnel Oxide Passivated Contact) cell can be stacked to form a TBC (Tunnel Back Contact) cell. TBC cells are the highest level of crystalline silicon research and development and manufacturing, and are currently becoming a hot spot for the development of a new generation of solar cell technology. The back surface is fully covered with doped polysilicon / silicon oxide film for passivation, which is a one-dimensional passivation contact, which effectively reduces the back surface recombination, improves the open circuit voltage and fill factor, and at the same time, because there is no shielding on the front, the short circuit current is increased, thereby obtaining a higher cell efficiency.

[0003] In order to prepare the N+ region, the local P+ region and the isolation region therebetween (the structure combining these three is usually called a PIN structure), the existing process route requires two high-temperature doping processes, two amorphous silicon deposition processes, two laser processes and multiple mask processes. The process is cumbersome and the process time is long, which seriously affects the production capacity and causes additional manufacturing costs. In addition, the existing process route has too many high-temperature processes, and two high-temperature dopings (phosphorus doping temperature 800-1000°C, boron doping temperature 900-1200°C) greatly affect the minority carrier lifetime of the substrate silicon wafer and thus have an adverse effect on the battery efficiency. In addition, the existing TBC preparation process route is complex and the process window is small. Since the BSG thickness is relatively thick to bear the role of blocking and doping, high-energy laser film opening is required for film opening, but high-energy laser film opening will cause recombination, and low-energy laser film opening cannot completely remove the BSG layer. In the limited pickling time, it cannot be pickled clean, which will also cause recombination, thereby affecting the conversion efficiency of the battery. Summary of the invention

[0004] The present invention is aimed at the above problems, makes up for the deficiencies of the prior art, and provides a TBC battery and a preparation method thereof to solve the problems arising from the above background technology.

[0005] A first aspect of the present invention provides a method for preparing a TBC battery, comprising the following steps: S1 forms a dielectric region and a polysilicon layer; S2 forming a dopant source layer of first conductivity type impurities and a mask layer; S3 film opening and cleaning; S4 different conductivity type impurities are co-doped in one step.

[0006] Preferably, the thickness of the dopant source layer of the first conductive type impurities is 5nm-60nm, for example: 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, etc. More preferably, the thickness of the dopant source layer of the first conductive type impurities is 20nm-40nm.

[0007] In the present invention, the thickness of the dopant source layer of the first conductive type impurity is 5nm-60nm. When the thickness is less than 5nm, the doping concentration is too low, resulting in a decrease in the photoelectric conversion efficiency; when the thickness is greater than 60nm, the oxygen content of the silicon wafer will be high, resulting in serious recombination, resulting in a decrease in the photoelectric conversion efficiency and photoinduced degradation.

[0008] Preferably, in the preparation method, before forming the dielectric region in S1, the method further includes the steps of cleaning and polishing the substrate silicon wafer, and the substrate silicon wafer is of N-type or P-type.

[0009] Preferably, in the preparation method, after the S4 conductive dopant is co-doped in one step, it also sequentially includes laser selective doping, preparation of the Gap area, a texturing step, removal of the dopant source layer of the first conductive type impurities, a mask layer and an RCA cleaning step, a dielectric layer formation step, and a metallization step.

[0010] Preferably, the TBC cell includes a substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, a dielectric region and a polysilicon layer being sequentially arranged on the back side of the substrate silicon wafer in a direction away from the substrate silicon wafer, and an impurity source layer of the first conductive type impurities being formed outside the polysilicon layer.

[0011] Preferably, the S2 is formed in the doping source layer of the first conductive type impurities by CVD method, with a formation temperature of 300°C-800°C and a time of 1min-90min. The forming raw materials include boron source gas or phosphorus source gas, and the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0012] Preferably, the forming raw material also includes other gases, and the other gases are one or more gases of SiH4, N2O, NH3, Ar.

[0013] Preferably, the S2 dopant source layer of the first conductivity type impurities is a silicon-containing compound layer containing first conductivity type impurities, and the first conductivity type impurities are boron, gallium or phosphorus.

[0014] Preferably, the mask layer of the S2 first conductivity type impurities is a composite film composed of one or more of silicon nitride, silicon oxynitride and silicon oxide, and the thickness of the mask layer is 2nm-200nm.

[0015] By adopting the above technical solution, the mask layer is formed outside the first dopant source layer, and in the subsequent mold opening and cleaning process, only the first dopant source layer in the mold opening area and the mask layer outside the first dopant source layer are removed. The effects are as follows: ① A mask layer is formed on the outside of the first dopant source layer, and only a relatively thin first dopant source layer is needed to meet the doping concentration of the first conductive dopant in the poly or c-Si layer. A relatively thin dopant source layer is conducive to forming a uniform film thickness (the reason is that because of the mask layer, the first dopant source layer in the non-film opening area will not be consumed or only a little will be consumed after the film opening and cleaning; secondly, when performing a one-step co-diffusion, the first dopant source layer in the non-film opening area and the mask layer together prevent the second dopant from diffusing to the non-film opening area, so a thicker dopant source layer is not needed); ② The film opening process window is increased to ensure the uniformity within and between wafers after the film opening process: because there is a mask layer on the outside of the first dopant source layer, the film opening depth can be controlled by adjusting the ratio of each gas in the mask layer and the thickness, thereby protecting the polysilicon area or c-Si area in the film opening area from doping with the first dopant and loss after the film opening, thereby ensuring the uniformity within and between wafers after the film opening process. ③ Increase the uniformity of the first dopant source layer in the cleaning window and the non-film-opening area after cleaning: Utilize the difference in cleaning rates between the mask and the first dopant source layer, so that the residual film layer in the film-opening area is cleaned while the mask layer in the non-film-opening area protects the first dopant source layer from being cleaned, ensuring the uniformity of the first dopant source layer in the non-film-opening area; ④ Improve the uniformity of the doping concentration in the first doped area of ​​the polysilicon layer: Because of the mask process, the first dopant source layer is deposited more uniformly, and the first dopant source layer in the non-film-opening area is basically not cleaned during cleaning. During one-step co-diffusion, the mask layer helps to block the second dopant source layer from diffusing like the first doping area. The above advantages comprehensively improve the uniformity of the doping concentration in the first doped area of ​​the polysilicon layer. ⑤ By adjusting the gas during mask formation, the material of the mask can be changed, so that the cleaning rate of the mask is lower than that of the first dopant source layer, further improving the effect of the mask.

[0016] Preferably, the film opening in S3 is performed by at least one of laser, slurry etching and photolithography.

[0017] More preferably, laser film opening is adopted, and the parameters of laser film opening are set as follows: wavelength 200nm-1064nm, power ≥1W, scanning speed 5m / s-50m / s, frequency 200kHz-2000kHz.

[0018] By adopting the above technical solution, the c-Si region or polysilicon layer region where the second conductive type impurity region will be formed in the future is laser-opened. The local dopant source layer of the first conductive type impurity is removed or thinned, and in this process, no doping is caused to the polysilicon region or c-Si region, or only a low concentration doping of one order of magnitude lower than the future doping concentration of this area is caused.

[0019] Preferably, the cleaning method in S3 includes acid washing, alkali washing, or acid washing followed by alkali washing.

[0020] More preferably, the cleaning method is acid cleaning.

[0021] The acid washing is performed using hydrofluoric acid with a concentration of 0.5%-50%. After washing, the first dopant source layer in the non-film-opening area is retained by at least 2nm; and there is no first dopant source layer remaining in the film-opening area, that is, the residual first dopant source concentration after washing is less than 1×10 19 cm -3 .

[0022] By adopting the above technical solution, the film-opening area formed by laser film-opening provides a reserved area for the second conductive type impurity layer to be formed in the future. After cleaning the film-opening area, a polysilicon area or a c-Si area is reserved for forming the second conductive type impurity doping. The main purpose of cleaning here is to remove the doping source layer of the first doped conductive type impurity remaining on the surface of the polysilicon layer in the film-opening area or the doping source layer of the first doped conductive type impurity remaining on the surface of the c-Si, so as to ensure that the non-film-opening area and the film-opening area form a single conductive type impurity doping during one-step co-diffusion; and after cleaning, the doping source layer of the first doped conductive type impurity in the non-laser film-opening area needs to retain a sufficient thickness, in order to ensure that the first doping area has a sufficient doping concentration after one-step co-doping, and as a mask layer to prevent the doping material of the second conductive type impurity from being doped into the first doping area. The complete removal of the doping source layer of the first doped conductive type impurity and the doping source layer of the second doped conductive type impurity in the non-film-opening area will be completely removed in the subsequent RCA cleaning step.

[0023] Preferably, the doping temperature of the S4 different conductivity type impurities co-doped in one step is 600°C-1000°C, more preferably, the doping temperature is 600°C-980°C, and the doping time is 5 min-180 min, and the doping time does not include the time required for heating and cooling.

[0024] Preferably, in the one-step co-doping of different conductive type impurities in S4, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used to simultaneously form a first conductive type impurity region and a second conductive type impurity region, the first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the one-step co-doping of different conductive type impurities is performed at least once.

[0025] Preferably, the doping sources of the second conductive type impurities are boron source gas and phosphorus source gas, the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0026] Preferably, before the S4 co-doping step of different conductive type impurities, it also includes a laser selective doping step, with a scanning speed of 5m / s-50m / s, a frequency of 200kHz-2000kHz, a wavelength of the laser selective doping of 200nm-1064nm, a power ≥1W, a scanning speed of 5m / s-50m / s, and a frequency of 200kHz-2000kHz, and the laser selective doping obtains a local heavily doped region of the conductive type impurity region.

[0027] Preferably, after the S4 one-step co-doping step of impurities of different conductive types, a preparation step of the Gap region is also included, and the preparation of the Gap region is automatically formed when the S4 impurities of different conductive types are co-doped in one step or prepared by laser, and the setting parameters of the laser preparation are: wavelength 200 nm-1064 nm, power ≥1W, scanning speed 5m / s-50m / s, frequency 200kHz-2000kHz.

[0028] Preferably, the preparation step of the Gap area further includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer or a Gap area texturing surface on the back side, and the morphology and size of the front texturing surface and the Gap area texturing surface are the same or different.

[0029] Another aspect of the present invention provides a TBC cell, comprising a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer comprising a front velvet surface and a second dielectric layer; the back side of the substrate silicon wafer comprising a dielectric region, a second conductivity type impurity region, a first conductivity type impurity region, a first dielectric layer, a metal electrode and a Gap region; The dielectric region is a tunnel oxide layer, the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 5nm-60nm; The second conductive type impurity region and the first conductive type impurity region are formed simultaneously in one or more conductive dopant one-step co-doping steps; In the conductive dopant co-doping step, at least once, a doping source having impurities of a second conductivity type opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region on the back side of the substrate silicon wafer is electrically opposite to the second conductive type impurity region on the front side of the substrate silicon wafer, and a local area of ​​the metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

[0030] Preferably, the c-Si region or polysilicon layer of the second conductive type impurity region is formed by film opening and cleaning, the film opening method is at least one of laser, etching slurry, and photolithography, the cleaning method includes at least one of acid washing, alkaline washing, and acid washing followed by alkaline washing, and the one-step co-doping is to achieve the doping of the doping sources of the first conductive type impurities and the second conductive type impurities under the same high temperature conditions.

[0031] Preferably, the film opening method in the S3 film opening and cleaning is laser film opening, and the cleaning method in the S3 film opening and cleaning is acid cleaning.

[0032] Preferably, a Gap area velvet surface is also provided on the back side of the substrate silicon wafer, and the Gap area velvet surface is different in morphology and size from the front velvet surface; the first conductive type impurity region, and / or the second conductive type impurity region is also provided with a heavily doped region.

[0033] Another aspect of the present invention provides a TBC cell, comprising a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer comprising a front velvet surface and a second dielectric layer; the back side of the substrate silicon wafer comprising a dielectric region, a second conductivity type impurity region, a first conductivity type impurity region, a first dielectric layer, a metal electrode and a Gap region; The local region of the electrode penetrates the first dielectric layer to form an ohmic contact with the second conductive type impurity region; the local region of the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity region; The dielectric region is a tunneling oxide layer, the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities.

[0034] Compared with the prior art, the present invention has the following beneficial effects: The present invention deposits a dopant source layer and a mask layer of first conductive type impurities in sequence. The dopant source layer of the first conductive type impurities below can most likely only serve as a dopant source layer and can be made into an extremely thin high-concentration layer. The mask layer serves as a barrier layer, and the mask layer can be made thicker or thinner according to the laser power. The limiting condition of the laser is that the second conductive type impurities cannot cause doping after the film is opened, and the PN region film opening and cleaning window are enlarged. Since the dopant source layer of the first conductive type impurities can be made into an extremely thin high-concentration layer, the oxygen content of the silicon substrate is reduced, the recombination effect inside the battery is reduced, thereby improving the photoelectric conversion efficiency, and reducing the light-induced decay phenomenon. At the same time, it can also match the boron doping at a lower temperature. The present invention First, a dopant source layer of the first conductive type impurity is deposited. When different conductive types of impurities are co-doped in one step, the deposited dopant source layer of the first conductive type impurity can be used as a doping source to achieve high-temperature simultaneous doping in one step to form a first conductive type impurity region and a second conductive type impurity region. There is only one high-temperature doping, and the number of high-temperature doping times is reduced. On the other hand, the present invention only removes the dopant source layer of the first conductive type impurity and performs RCA cleaning once, and the number of cleaning times is reduced, shortening the process and time of the TOPCon battery, and no more thermal processes, heating / cooling processes, and wet processes are required, thereby simplifying the process steps and time of solar cells, and increasing the battery cell yield, thereby saving production costs and facilitating large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the TBC battery structure in Example 1; Figure 2 This is a process flow chart of TBC battery preparation in Example 1; Figure 3 This is a schematic diagram of the TBC battery structure in Example 8; Figure 4 This is a process flow chart of TBC battery preparation in Example 8; Figure 5 This is a schematic diagram of the TBC battery structure in Example 14; Figure 6 This is a process flow chart of TBC battery preparation in Example 14; Figure 7 This is a schematic diagram of the TBC battery structure in Example 20; Figure 8 This is a process flow chart for preparing TBC batteries in Example 20.

[0036] In the figure: 1-second dielectric layer; 2-front velvet surface, 3-N-type silicon wafer; 4-tunneling oxide layer, 5-second conductivity type impurity polysilicon region and heavily doped region, 6-first dielectric layer, 7-electrode, 8-gap region, 9-first conductivity type impurity polysilicon region, 10-second conductivity type impurity c-Si region and heavily doped region. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings in the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0038] A method for preparing a TBC battery comprises the following steps: S1 forms a dielectric region and a polysilicon layer; S2 forming a dopant source layer of first conductivity type impurities and a mask layer; S3 film opening and cleaning; S4 different conductivity type impurities are co-doped in one step.

[0039] The present invention deposits a dopant source layer and a mask layer of first conductive type impurities in sequence. The dopant source layer of the first conductive type impurities below can most likely only serve as a dopant source layer and can be made into an extremely thin high-concentration layer. The mask layer serves as a barrier layer, and the mask layer can be made thicker or thinner according to the laser power. The limiting condition of the laser is that the second conductive type impurities cannot cause doping after the film is opened, and the PN region film opening and cleaning window are enlarged. Since the dopant source layer of the first conductive type impurities can be made into an extremely thin high-concentration layer, the oxygen content of the silicon substrate is reduced, the recombination effect inside the battery is reduced, thereby improving the photoelectric conversion efficiency, and reducing the light-induced decay phenomenon. At the same time, it can also match the boron doping at a lower temperature. The present invention First, a dopant source layer of the first conductive type impurity is deposited. When different conductive types of impurities are co-doped in one step, the deposited dopant source layer of the first conductive type impurity can be used as a doping source to achieve high-temperature simultaneous doping in one step to form a first conductive type impurity region and a second conductive type impurity region. There is only one high-temperature doping, and the number of high-temperature doping times is reduced. On the other hand, the present invention only removes the dopant source layer of the first conductive type impurity and performs RCA cleaning once, and the number of cleaning times is reduced, shortening the process and time of the TOPCon battery, and no more thermal processes, heating / cooling processes, and wet processes are required, thereby simplifying the process steps and time of solar cells, and increasing the battery cell yield, thereby saving production costs and facilitating large-scale production.

[0040] As a preferred embodiment, the thickness of the dopant source layer of the first conductive type impurity is 5nm-60nm. For example: 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, etc. More preferably, the thickness of the dopant source layer of the first conductive type impurity is 20nm-40nm.

[0041] In the present invention, the thickness of the dopant source layer of the first conductive type impurity is 5nm-60nm. When the thickness is less than 5nm, the doping concentration is too low, resulting in a decrease in the photoelectric conversion efficiency; when the thickness is greater than 60nm, the oxygen content of the silicon wafer will be high, resulting in serious recombination, resulting in a decrease in the photoelectric conversion efficiency and photoinduced degradation.

[0042] As a preferred embodiment, the TBC cell includes a substrate silicon wafer, wherein the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, a dielectric region and a polysilicon layer are sequentially arranged on the back side of the substrate silicon wafer in a direction away from the substrate silicon wafer, and an impurity source layer of the first conductive type impurity is formed outside the polysilicon layer.

[0043] As a preferred implementation, the substrate silicon wafer in S1 is N-type or P-type, has a resistivity of 0.1-3.0 Ωcm, and a thickness of 100-200 μm.

[0044] As a preferred implementation, the cleaning and polishing in S1 utilizes acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and performs etching and polishing on the surface of the single crystal silicon wafer.

[0045] As a preferred embodiment, in the preparation method, after S4 co-doping with impurities of different conductive types in one step, it also sequentially includes laser selective doping, preparation of Gap area, texturing step, removal of the dopant source layer of the first conductive type impurities and RCA cleaning step, dielectric layer formation step, and metallization step.

[0046] As a preferred embodiment, the tunneling oxide layer and the polysilicon layer are formed by CVD in S1. In the CVD furnace tube, N2O is used as an oxidant, the oxidation temperature is 300℃-650℃, and the time is 60s-600s to form a tunneling oxide layer with a thickness of 1-3nm; SiH4 is used as a reaction gas and Ar is used as a dilution gas. The formation temperature is 300℃-650℃ and the time is 300s-3600s to form a polysilicon layer on the surface of the tunneling oxide layer with a thickness of 50-400nm. The CVD method is plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

[0047] As a preferred embodiment, the S2 forms the dopant source layer of the first conductive type impurities, and is formed by CVD, with a formation temperature of 300°C-800°C and a time of 1min-90min. The forming raw materials include a boron source gas or a phosphorus source gas, and the boron source gas is at least one of BH3, TMB, BCl3, and BBr3; the phosphorus source gas is at least one of PH3 and POCl3; and the CVD method is PECVD or LPCVD.

[0048] As a preferred embodiment, the forming raw material also includes other gases, and the other gases are one or more gases of SiH4, N2O, NH3, Ar.

[0049] As a preferred implementation, the S2 dopant source layer of the first conductivity type impurities is a silicon-containing compound layer containing first conductivity type impurities, and the first conductivity type impurities are boron, gallium or phosphorus.

[0050] As a preferred embodiment, the mask layer is deposited by CVD in S2, and a mask layer is formed on the dopant source layer through chemical reaction and plasma reaction in the CVD furnace tube; the mask layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and its thickness is 2nm-200nm.

[0051] By adopting the above technical solution, the mask layer is formed outside the first dopant source layer, and in the subsequent mold opening and cleaning process, only the first dopant source layer in the mold opening area and the mask layer outside the first dopant source layer are removed. The effects are as follows: ① A mask layer is formed on the outside of the first dopant source layer, and only a relatively thin first dopant source layer is needed to meet the doping concentration of the first conductive dopant in the poly or c-Si layer. A relatively thin dopant source layer is conducive to forming a uniform film thickness (the reason is that because of the mask layer, the first dopant source layer in the non-film opening area will not be consumed or only a little will be consumed after the film opening and cleaning; secondly, when performing a one-step co-diffusion, the first dopant source layer in the non-film opening area and the mask layer together prevent the second dopant from diffusing to the non-film opening area, so a thicker dopant source layer is not needed); ② The film opening process window is increased to ensure the uniformity within and between wafers after the film opening process: because there is a mask layer on the outside of the first dopant source layer, the film opening depth can be controlled by adjusting the ratio of each gas in the mask layer and the thickness, thereby protecting the polysilicon area or c-Si area in the film opening area from doping with the first dopant and loss after the film opening, thereby ensuring the uniformity within and between wafers after the film opening process. ③ Increase the uniformity of the first dopant source layer in the cleaning window and the non-film-opening area after cleaning: Utilize the difference in cleaning rates between the mask and the first dopant source layer, so that the residual film layer in the film-opening area is cleaned while the mask layer in the non-film-opening area protects the first dopant source layer from being cleaned, ensuring the uniformity of the first dopant source layer in the non-film-opening area; ④ Improve the uniformity of the doping concentration in the first doped area of ​​the polysilicon layer: Because of the mask process, the first dopant source layer is deposited more uniformly, and the first dopant source layer in the non-film-opening area is basically not cleaned during cleaning. During one-step co-diffusion, the mask layer helps to block the second dopant source layer from diffusing like the first doping area. The above advantages comprehensively improve the uniformity of the doping concentration in the first doped area of ​​the polysilicon layer. ⑤ By adjusting the gas during mask formation, the material of the mask can be changed, so that the cleaning rate of the mask is lower than that of the first dopant source layer, further improving the effect of the mask.

[0052] As a preferred embodiment, in the S3 film opening and cleaning step, the film opening method is at least one of laser, etching slurry, and photolithography. More preferably, a laser method is used, and the laser parameters are set to: wavelength 200 nm-1064 nm, power ≥1W, scanning speed 5m / s-50m / s, and frequency 200kHz-2000kHz.

[0053] By adopting the above technical solution, the c-Si region or polysilicon layer region where the second conductive type impurity region will be formed in the future is laser-opened. The local dopant source layer of the first conductive type impurity is removed or thinned, and in this process, no doping is caused to the polysilicon region or c-Si region, or only a low concentration doping of one order of magnitude lower than the future doping concentration of this area is caused.

[0054] As a preferred embodiment, the cleaning method in S3 includes acid washing, alkali washing, or acid washing followed by alkali washing.

[0055] More preferably, the cleaning method is acid cleaning.

[0056] The acid washing is performed using hydrofluoric acid with a concentration of 0.5%-50%. After washing, the first dopant source layer in the non-film-opening area is retained by at least 2nm, that is, the residual first dopant source concentration after washing is less than 1×10 19 cm -3 ; and there is no residue of the first dopant source layer in the film opening area.

[0057] By adopting the above technical solution, the film-opening area formed by laser film-opening provides a reserved area for the second conductive type impurity layer to be formed in the future. After cleaning the film-opening area, a polysilicon area or a c-Si area is reserved for forming the second conductive type impurity doping. The main purpose of cleaning here is to remove the doping source layer of the first doped conductive type impurity remaining on the surface of the polysilicon layer in the film-opening area or the doping source layer of the first doped conductive type impurity remaining on the surface of the c-Si, so as to ensure that the non-film-opening area and the film-opening area form a single conductive type impurity doping during one-step co-diffusion; and after cleaning, the doping source layer of the first doped conductive type impurity in the non-laser film-opening area needs to retain a sufficient thickness, in order to ensure that the first doping area has a sufficient doping concentration after one-step co-doping, and as a mask layer to prevent the doping material of the second conductive type impurity from being doped into the first doping area. The complete removal of the doping source layer of the first doped conductive type impurity and the doping source layer of the second doped conductive type impurity in the non-film-opening area will be completely removed in the subsequent RCA cleaning step.

[0058] As a preferred embodiment, the S4 different conductive type impurities are co-doped in one step, the silicon wafer is placed in a doping tube for doping, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used, and the doping temperature is 600°C-1000°C. As a more preferred embodiment, the doping temperature is 600°C-980°C, and the doping time is 5 min-180 min. The dopant source layer of the first conductive type impurity formed on the back of the silicon wafer can be used as a doping source and as a barrier layer for doping with another element during doping, so that different conductive type impurities are simultaneously doped at a high temperature in one step to form a first conductive type impurity region and a second conductive type impurity region. The first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the number of times the different conductive type impurities are co-doped in one step is at least once.

[0059] As a preferred embodiment, the doping source of the second conductive type impurity is a boron source gas or a phosphorus source gas, the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0060] As a preferred embodiment, after the S4 is co-doped with impurities of different conductive types in one step, it also includes laser selective doping, with a scanning speed of 5m / s-50m / s and a frequency of 200kHz-2000kHz. The wavelength of the laser selective doping is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, and the frequency is 200kHz-2000kHz. The laser selective doping obtains a local heavily doped area of ​​the conductive type impurity area.

[0061] As a preferred embodiment, after the laser selective doping, it also includes the preparation of the Gap area, and the preparation of the Gap area is automatically formed when S4 different conductive type impurities are co-doped in one step or prepared by laser, and the setting parameters of the laser preparation are: wavelength 200 nm-1064 nm, power ≥1W, scanning speed 5m / s-50m / s, frequency 200kHz-2000kHz.

[0062] As a preferred embodiment, the preparation step of the Gap area also includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer or a Gap area texturing surface on the back side, and the morphology and size of the front texturing surface and the Gap area texturing surface are the same or different.

[0063] As a preferred embodiment, the texturing step uses 0.5-2wt% of KOH, NaOH or one or more of them to perform texturing by corrosion, and the corrosion time is 400s-600s.

[0064] As a preferred embodiment, the step of removing the dopant source layer of the first conductive type impurities and the RCA cleaning step is to place the silicon wafer in a hydrofluoric acid concentration of 0.5%-50% for pickling, and the pickling time is 10s-1200s to remove the dopant source layer of the first conductive type impurities of the silicon wafer; and then perform standard RCA cleaning on the silicon wafer to remove surface contaminants.

[0065] As a preferred embodiment, in the step of forming a dielectric layer, the dielectric layer is at least composed of an anti-reflection film, and a 50-120nm anti-reflection film layer is formed by CVD. The reflective film layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0066] As a preferred implementation, the dielectric layer further includes a passivation film layer, the thickness of the passivation film layer is 2-15 nm, and the passivation film layer is aluminum oxide.

[0067] As a preferred embodiment, in the metallization step, a back metal electrode is provided on the silicon wafer, and the metal electrode is preferably a silver electrode, to obtain the TBC battery structure.

[0068] As a preferred implementation, the polysilicon layer is formed in S1, the dopant source layer of the first conductive type impurities is formed in S2, and the doping in S4 is all in dual insertion mode.

[0069] Since many working sections of the present invention are changed from a single-insertion mode to a double-insertion mode, production costs are saved, output is increased, and large-scale production is facilitated.

[0070] This embodiment also provides a TBC cell, comprising a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer comprising a front velvet surface and a second dielectric layer; the back side of the substrate silicon wafer comprising a dielectric region, a second conductive type impurity region, a first conductive type impurity region, a first dielectric layer, a metal electrode and a Gap region; The dielectric region is a tunnel oxide layer, the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 5nm-60nm; The second conductive type impurity region and the first conductive type impurity region are formed simultaneously in one or more conductive dopant one-step co-doping steps; In the conductive dopant co-doping step, at least once, a doping source having impurities of a second conductivity type opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region on the back side of the substrate silicon wafer is electrically opposite to the second conductive type impurity region on the front side of the substrate silicon wafer, and a local area of ​​the metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

[0071] As a preferred embodiment, the c-Si region or polysilicon layer of the second conductive type impurity region is formed by film opening and cleaning, the film opening method is at least one of laser, etching slurry, and photolithography, the cleaning method includes at least one of acid washing, alkaline washing, and acid washing followed by alkaline washing, and the one-step co-doping is to achieve the doping of the doping sources of the first conductive type impurities and the second conductive type impurities under the same high temperature conditions.

[0072] As a preferred embodiment, a Gap area velvet is also provided on the back side of the substrate silicon wafer, and the Gap area velvet has the same or different morphology and size as the front velvet; the first conductive type impurity region, and / or the second conductive type impurity region is also provided with a heavily doped region.

[0073] This embodiment also provides a TBC cell, comprising a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer comprising a front velvet surface and a second dielectric layer; the back side of the substrate silicon wafer comprising a dielectric region, a second conductive type impurity region, a first conductive type impurity region, a first dielectric layer, a metal electrode and a Gap region; The local region of the electrode penetrates the first dielectric layer to form an ohmic contact with the second conductive type impurity region; the local region of the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity region; The dielectric region is a tunneling oxide layer; the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities.

[0074] Since many working sections of the present invention are changed from a single-insertion mode to a double-insertion mode, production costs are saved, output is increased, and large-scale production is facilitated.

[0075] The TBC battery and the preparation method thereof of the present invention are further described below through specific examples and comparative examples.

[0076] Example 1 like Figure 1 As shown, an N-type TBC battery comprises an N-type silicon wafer 3, the N-type silicon wafer 3 is a substrate silicon wafer, a second dielectric layer 1 and a front velvet surface 2 are arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 are arranged on the back side of the N-type silicon wafer 3; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0077] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0078] like Figure 2 As shown, the method for preparing an N-type TBC battery in this embodiment includes the following steps: 1. Select a P-doped N-type silicon wafer with a resistivity of 1.5Ω cm and a thickness of 150μm; use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0079] 2. In a PECVD furnace tube, N2O was used as the oxidant, the oxidation temperature was 600℃, and the time was 3 min. A tunneling oxide layer with a thickness of 3 nm was deposited on the back of the silicon wafer. SiH4 was used as the reaction gas, Ar was used as the dilution gas, the deposition temperature was 600℃, and the time was 90 min. A polysilicon layer with a thickness of 250 nm was deposited on the surface of the tunneling oxide layer.

[0080] 3. In a PECVD furnace tube, PH3, SiH4, N2O, and NH3 are used as deposition raw materials, the deposition temperature is 600°C, and the time is 50 minutes. A 30nm thick phosphorus-containing silicon oxide compound layer is deposited on the polysilicon layer; a 100nm thick silicon oxide mask layer is deposited on the phosphorus-containing silicon oxide compound layer.

[0081] 4. Use laser to open the film of silicon wafer. The laser setting parameters are wavelength 200 nm, power ≥1W, scanning speed 25m / s, frequency 1000kHz, and then clean it in a cleaning machine. The cleaning method is acid pickling and drying after cleaning to expose the polysilicon layer on the back of the silicon wafer.

[0082] 5. Place the silicon wafer in a boron doping tube for one-step co-doping of boron and phosphorus. The doping temperature is 800°C, the doping time is 100 minutes, the boron doping source is BBr3, and a second conductive type impurity polysilicon region is formed on the back of the silicon wafer. At the same time, the phosphorus-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity region to form the first conductive type impurity polysilicon region, and can also be used as a boron doping barrier layer. The number of one-step co-doping of boron and phosphorus is 2 times. When laser selective doping is performed, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz to produce a heavily doped region of the second conductive type impurity polysilicon region.

[0083] 6. Use laser to prepare Gap area on silicon wafer. The laser setting parameters are wavelength 600 nm, power ≥1W, scanning speed 25m / s, frequency 1000kHz, and then pickling, water washing and drying in a cleaning machine.

[0084] 7. Use 1.3% NaOH solution for etching for 500s to prepare a front velvet surface on the front side of the silicon wafer and a Gap area velvet surface on the back side of the Gap area (not shown in the figure), and then use an acid-base solution to polish the pyramid velvet surface in the Gap area to make the pyramid velvet surface in the Gap area smooth and flat.

[0085] 8. Place the silicon wafer in 25% HF for pickling for 600 seconds to remove the phosphorus-containing silicon oxide layer, boron-containing silicon oxide layer and mask layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0086] 9. ALD atomic layer deposition method is used, TMA is used as a precursor, and the reaction temperature is controlled at 300°C to deposit a dense Al2O3 passivation layer with a thickness of 10nm on the front and back of the silicon wafer. PECVD method is used to deposit a 100nm SiO2 anti-reflection layer on the front and back of the silicon wafer. The passivation layer and the anti-reflection layer form a dielectric layer.

[0087] 10. Print Ag paste on the back of the silicon wafer, dry and sinter it to obtain the back metal electrode.

[0088] Example 2 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer and a front velvet surface arranged on the front side of the N-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0089] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 5 nm.

[0090] The method for preparing an N-type TBC battery in this embodiment comprises the following steps: 1. Select a P-doped N-type silicon wafer with a resistivity of 0.1Ω cm and a thickness of 100μm; use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0091] 2. In the LPCVD furnace tube, N2O was used as the oxidant, the oxidation temperature was 550℃, and the time was 2 min. A tunneling oxide layer with a thickness of 2nm was deposited on the back of the silicon wafer. SiH4 was used as the reaction gas, Ar was used as the dilution gas, the deposition temperature was 550℃, and the time was 20 min. A polysilicon layer with a thickness of 50nm was deposited on the surface of the tunneling oxide layer.

[0092] 3. In a PECVD furnace tube, POCl3, SiH4, N2O, and NH3 are used as deposition raw materials, the deposition temperature is 300°C, and the time is 5 minutes. A 5nm thick phosphorus-containing silicon oxide compound layer is deposited on the polysilicon layer; a 200nm thick silicon oxide mask layer is deposited on the phosphorus-containing silicon oxide compound layer.

[0093] 4. Use laser to open the film of silicon wafer. The laser setting parameters are wavelength 200 nm, power ≥1W, scanning speed 5m / s, frequency 2000kHz, and then clean it in a cleaning machine. The cleaning method is acid pickling and drying after cleaning to expose the local polysilicon layer on the back of the silicon wafer.

[0094] 5. Place the silicon wafer in a boron doping tube for one-step co-doping of boron and phosphorus. The doping temperature is 600°C, the doping time is 180 minutes, the boron doping source is BBr3, and a second conductive type impurity polysilicon region is formed on the back of the silicon wafer. The phosphorus-containing silicon oxide layer on the back can be used as a doping source for the first conductive type impurity region to form the first conductive type impurity polysilicon region, and can also be used as a barrier layer for boron doping. The number of one-step co-doping of boron and phosphorus is 4 times. When laser selective doping is performed, the wavelength is set to 1064nm, the scanning speed is 50m / s, and the frequency is 2000kHz to produce a heavily doped region of the second conductive type impurity polysilicon region.

[0095] 6. Use laser to prepare Gap area on silicon wafer with wavelength of 200 nm, power ≥1W, scanning speed of 5m / s and frequency of 2000kHz, then pickle and wash with water and dry in a cleaning machine.

[0096] 7. Use 0.5% NaOH solution for etching for 600s to prepare a front velvet surface on the front side of the silicon wafer and a Gap area velvet surface on the back side of the Gap area (not shown in the figure), and then use an acid-base solution to polish the pyramid velvet surface in the Gap area to make the pyramid velvet surface in the Gap area smooth and flat.

[0097] 8. Place the silicon wafer in 0.5% HF for pickling for 1200 seconds to remove the phosphorus-containing silicon oxide layer, boron-containing silicon oxide layer and mask layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0098] 9. A 70nm SiO2 anti-reflection layer is deposited on the front and back sides of the silicon wafer by PECVD, and the anti-reflection layer forms a dielectric layer.

[0099] 10. Print Ag paste on the back of the silicon wafer, dry and sinter it to obtain the back metal electrode.

[0100] Example 3 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer and a front velvet surface arranged on the front side of the N-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0101] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 60 nm.

[0102] The method for preparing an N-type TBC battery in this embodiment comprises the following steps: 1. Select a P-doped N-type single crystal silicon wafer with a resistivity of 3Ω cm and a thickness of 200μm; use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0103] 2. In the LPCVD furnace tube, N2O was used as the oxidant, the oxidation temperature was 650℃, and the time was 4 min. A tunneling oxide layer with a thickness of 4 nm was deposited on the back of the silicon wafer. SiH4 was used as the reaction gas, Ar was used as the dilution gas, the deposition temperature was 650℃, and the time was 150 min. A polysilicon layer with a thickness of 400 nm was deposited on the surface of the tunneling oxide layer.

[0104] 3. In an LPCVD furnace tube, PH3, SiH4, N2O, and NH3 are used as deposition raw materials, the deposition temperature is 800°C, and the time is 90 minutes. A 60nm thick phosphorus-containing silicon oxide compound layer is deposited on the polysilicon layer; a 2nm thick silicon oxide mask layer is deposited on the phosphorus-containing silicon oxide compound layer.

[0105] 4. Use laser to open the film on the silicon wafer. The laser setting parameters are wavelength 1064 nm, power ≥1W, scanning speed 50m / s, frequency 200kHz, and then pickling, washing and drying in a cleaning machine.

[0106] 5. Place the silicon wafer in a boron doping tube for one-step co-doping of boron and phosphorus. The doping temperature is 1000°C, the doping time is 5 minutes, the boron doping source is BBr3, and a second conductive type impurity polysilicon region is formed on the back of the silicon wafer. The phosphorus-containing silicon oxide layer on the back can be used as a doping source for the first conductive type impurity region to form the first conductive type impurity polysilicon region, and can also be used as a barrier layer for boron doping. The number of one-step co-doping of boron and phosphorus is 1. When laser selective doping is performed, the wavelength is set to 200nm, the scanning speed is 5m / s, and the frequency is 200kHz to produce a heavily doped region of the second conductive type impurity polysilicon region.

[0107] 6. Use laser to prepare Gap area on silicon wafer, with wavelength of 1064 nm, power ≥1W, scanning speed of 50m / s, frequency of 200kHz, and then pickle, wash and dry in a cleaning machine.

[0108] 7. Use 2% NaOH solution for etching for 400s to prepare a front velvet surface on the front side of the silicon wafer and a Gap area velvet surface on the back side (not shown in the figure), and then use an acid-base solution to polish the pyramid velvet surface in the Gap area to make the pyramid velvet surface in the Gap area smooth and flat.

[0109] 8. Place the silicon wafer in 50% HF for pickling for 10 seconds to remove the phosphorus-containing silicon oxide layer, boron-containing silicon oxide layer and mask layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0110] 9. ALD atomic layer deposition method is used, TMA is used as a precursor, and the reaction temperature is controlled at 300°C to deposit a dense Al2O3 passivation layer with a thickness of 15nm on the front and back of the silicon wafer. PECVD method is used to deposit a 120nm SiO2 anti-reflection layer on the front and back of the silicon wafer. The passivation layer and the anti-reflection layer form a dielectric layer.

[0111] 10. Print Ag paste on the back of the silicon wafer, dry and sinter it to obtain the back metal electrode.

[0112] Example 4 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer and a front velvet surface arranged on the front side of the N-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0113] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0114] The preparation method of this embodiment is different from that of embodiment 1 in that: the doping temperature in ⑤ is 950°C.

[0115] Example 5 A P-type TBC battery, comprising a P-type silicon wafer, a second dielectric layer and a front velvet surface arranged on the front side of the P-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the P-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0116] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0117] The preparation method of this embodiment is different from that of embodiment 1 in that: 1. The single crystal silicon wafer is B-doped P-type single crystal silicon wafer; 3. Using BH3, SiH4, N2O, Ar, and NH3 as deposition sources, a boron-containing silicon oxide layer with a thickness of 30 nm is formed; 5. Place the silicon wafer in a phosphorus-doped tube for boron-phosphorus co-doping, with a doping temperature of 800°C and a doping time of 100 min. The phosphorus doping source is POCl3, and a second conductive type impurity polysilicon region is formed on the back of the silicon wafer. The boron-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity region to form the first conductive type impurity polysilicon region, and can also be used as a barrier layer for phosphorus doping. During laser selective doping, a heavily doped region of the second conductive type impurity polysilicon region is produced; The rest are the same.

[0118] Example 6 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer and a front velvet surface arranged on the front side of the N-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0119] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 3 nm. The preparation method of this embodiment is different from that of embodiment 2 in that: 3. A 3nm thick phosphorus-containing silicon oxide layer is deposited in the middle; The rest are the same.

[0120] Example 7 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer and a front velvet surface arranged on the front side of the N-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0121] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 62 nm.

[0122] The preparation method of this embodiment is different from that of embodiment 3 in that: 3. The thickness of the deposited phosphorus-containing silicon oxide layer is 62nm; The rest are the same.

[0123] Example 8 like Figure 3 As shown, an N-type TBC battery comprises an N-type silicon wafer 3, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0124] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0125] The preparation method of this embodiment is as follows Figure 4 shown.

[0126] The preparation method of this embodiment is different from that of embodiment 1 in that: 5. The gap area does not require laser formation: when boron and phosphorus are co-doped in one step, there is a large amount of boron and phosphorus compound in the adjacent parts of the first conductive type impurity region and the second conductive type impurity region, which is basically non-conductive and automatically forms a gap area.

[0127] Step 6 is missing; The rest are the same.

[0128] Example 9 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer and a front velvet surface arranged on the front side of the N-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0129] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 5 nm.

[0130] The preparation method of this embodiment is different from that of embodiment 2 in that: 5. The gap area does not require laser formation: when boron and phosphorus are co-doped in one step, there is a large amount of boron and phosphorus compound in the adjacent parts of the first conductive type impurity region and the second conductive type impurity region, which is basically non-conductive and automatically forms a gap area.

[0131] Step 6 is missing; The rest are the same.

[0132] Example 10 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer and a front velvet surface arranged on the front side of the N-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0133] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 60 nm.

[0134] The preparation method of this embodiment is different from that of embodiment 3 in that: 5. The gap area does not require laser formation: when boron and phosphorus are co-doped in one step, there is a large amount of boron and phosphorus compound in the adjacent parts of the first conductive type impurity region and the second conductive type impurity region, which is basically non-conductive and automatically forms a gap area.

[0135] Step 6 is missing; The rest are the same.

[0136] Embodiment 11 A P-type TBC battery, comprising a P-type silicon wafer, a second material layer and a front velvet surface arranged on the front side of the P-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of an N-type silicon wafer 3, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0137] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0138] The preparation method of this embodiment is different from that of embodiment 8 in that: ① The single crystal silicon wafer is a B-doped P-type single crystal silicon wafer; ③ Using TMB, SiH4, N2O, Ar, and NH3 as formation sources, a boron-containing silicon-oxygen compound layer with a thickness of 30 nm is formed; ⑤ Place the silicon wafer into a phosphorus-doped tube for boron-phosphorus co-doping, the doping temperature is 800°C, the doping time is 100 min, the phosphorus doping source is POCl3, and a second conductive type impurity polysilicon region is formed on the back of the silicon wafer. The boron-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity region to form the first conductive type impurity polysilicon region, and can also be used as a barrier layer for phosphorus doping. During laser selective doping, a heavily doped region of the second conductive type impurity polysilicon region is produced; The rest are the same.

[0139] Example 12 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer and a front velvet surface arranged on the front side of the N-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0140] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 3 nm.

[0141] The preparation method of this embodiment is different from that of embodiment 9 in that: The thickness of the phosphorus-containing silicon oxide compound layer formed in ③ is 3nm; The rest are the same.

[0142] Embodiment 13 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer and a front velvet surface arranged on the front side of the N-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0143] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 62 nm.

[0144] The preparation method of this embodiment is different from that of embodiment 10 in that: The thickness of the phosphorus-containing silicon oxide compound layer formed in ③ is 62nm; The rest are the same.

[0145] Embodiment 14 like Figure 5As shown, an N-type TBC battery comprises an N-type silicon wafer 3, a second dielectric layer 1 arranged on the front side of the N-type silicon wafer 3, a front velvet surface 2, a second conductive type impurity c-Si region and a heavily doped region 10 arranged on the back side of the N-type silicon wafer 3, a first dielectric layer 6, a tunneling oxide layer 4, a first conductive type impurity polysilicon region 9, a gap region 8, and an electrode 7; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0146] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0147] The preparation method of this embodiment is as follows Figure 6 shown.

[0148] The preparation method of this embodiment is different from that of embodiment 1 in that: 4. Perform laser film opening on the back of the silicon wafer to form a c-Si area; 6. The location and depth of the Gap area are different; The rest are the same.

[0149] Embodiment 15 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, a gap region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0150] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 5 nm.

[0151] The preparation method of this embodiment is different from that of embodiment 2 in that: 4. Perform laser film opening on the back of the silicon wafer to form a c-Si area; 6. The location and depth of the Gap area are different; The rest are the same.

[0152] Example 16 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, a gap region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0153] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 60 nm.

[0154] The preparation method of this embodiment is different from that of embodiment 3 in that: ④ Perform laser film opening on the back of the silicon wafer to form a c-Si area; ⑥The location and depth of the Gap area are different; The rest are the same.

[0155] Embodiment 17 A P-type TBC battery, comprising a P-type silicon wafer, a second dielectric layer arranged on the front side of the P-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the P-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, a gap region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0156] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0157] The preparation method of this embodiment is different from that of embodiment 14 in that: ① The single crystal silicon wafer is a B-doped P-type single crystal silicon wafer; ③ Using BH3, SiH4, N2O, Ar, and NH3 as formation sources, a boron-containing silicon oxide layer with a thickness of 30 nm is formed; ⑤ Place the silicon wafer into a phosphorus-doped tube for boron-phosphorus co-doping, the doping temperature is 800°C, the doping time is 100 min, the phosphorus doping source is POCl3, and a second conductive type impurity c-Si region is formed on the back of the silicon wafer. The boron-containing silicon oxide layer on the back can be used as a doping source for the first conductive type impurity region to form a first conductive type impurity polysilicon region, and can also be used as a barrier layer for phosphorus doping. During laser selective doping, a heavily doped region of the second conductive type impurity c-Si region is produced; The rest are the same.

[0158] Embodiment 18 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, a gap region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0159] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 3 nm.

[0160] The preparation method of this embodiment is different from that of embodiment 15 in that: ③ The thickness of the phosphorus-containing silicon oxide compound layer formed is 3nm; The rest are the same.

[0161] Embodiment 19 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, a gap region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0162] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 62 nm.

[0163] The preparation method of this embodiment is different from that of embodiment 16 in that: ③ The thickness of the phosphorus-containing silicon oxide compound layer formed is 62nm; The rest are the same.

[0164] Embodiment 20 like Figure 7 As shown, an N-type TBC battery comprises an N-type silicon wafer 3, a second dielectric layer 1 arranged on the front side of the N-type silicon wafer 3, a front velvet surface 2, a second conductive type impurity c-Si region and a heavily doped region 10 arranged on the back side of the N-type silicon wafer 3, a first dielectric layer 6, a tunneling oxide layer 4, a first conductive type impurity polysilicon region 9, and an electrode 7; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0165] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0166] The preparation method of this embodiment is as follows Figure 8 shown.

[0167] The preparation method of this embodiment is different from that of embodiment 14 in that: Step 6 is missing; The rest are the same.

[0168] Embodiment 21 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0169] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 5 nm.

[0170] The preparation method of this embodiment is different from that of embodiment 15 in that: Step 6 is missing; The rest are the same.

[0171] Embodiment 22 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0172] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 60 nm.

[0173] The preparation method of this embodiment is different from that of embodiment 16 in that: Step 6 is missing; The rest are the same.

[0174] Embodiment 23 An N-type TBC battery, comprising a P-type silicon wafer, a second dielectric layer arranged on the front side of the P-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0175] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0176] The preparation method of this embodiment is different from that of embodiment 20 in that: ① The single crystal silicon wafer is a B-doped P-type single crystal silicon wafer; ③ Using BH3, SiH4, N2O, Ar, and NH3 as formation sources, a boron-containing silicon-oxygen compound layer with a thickness of 30 nm is formed; ⑤ Place the silicon wafer into a phosphorus-doped tube for boron-phosphorus co-doping, the doping temperature is 800°C, the doping time is 100 minutes, the phosphorus doping source is POCl3, and a second conductive type impurity c-Si region is formed on the back of the silicon wafer. The boron-containing silicon oxide layer on the back can be used as a doping source for the first conductive type impurity region to form a first conductive type impurity polysilicon region, and can also be used as a barrier layer for phosphorus doping. During laser selective doping, a heavily doped region of the second conductive type impurity c-Si region is produced; The rest are the same.

[0177] Embodiment 24 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0178] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 3 nm.

[0179] The preparation method of this embodiment is different from that of embodiment 21 in that: ③ The thickness of the phosphorus-containing silicon oxide compound layer formed is 3nm; The rest are the same.

[0180] Embodiment 25 An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0181] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 62 nm.

[0182] The preparation method of this embodiment is different from that of embodiment 22 in that: ③ The thickness of the phosphorus-containing silicon oxide compound layer formed is 62nm; The rest are the same.

[0183] Comparative Example 1 The preparation method of this comparative example is different from that of Example 1 in that no mask layer is deposited in step 2, and the rest are the same.

[0184] Comparative Example 2 This comparative example is a conventional TBC battery preparation method: 1. Select a P-doped N-type silicon wafer with a resistivity of 1.5Ω cm and a thickness of 150μm; use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0185] 2. In the LPCVD furnace tube, N2O was used as the oxidant, the oxidation temperature was 600℃, and the time was 3 min. A tunneling oxide layer with a thickness of 3 nm was deposited on the back of the silicon wafer. SiH4 was used as the reaction gas, Ar was used as the dilution gas, the deposition temperature was 600℃, and the time was 90 min. A polysilicon layer with a thickness of 250 nm was deposited on the surface of the tunneling oxide layer.

[0186] 3. Put the silicon wafer into a boron doping tube for boron doping, using boron trichloride as the boron source, and doping for 180 minutes at 1000°C. The thickness of the formed BSG layer is 150nm. 4. Deposit a 50nm oxide layer as a mask layer by thermal oxidation; 5. Use laser to open the film of silicon wafer. The laser setting parameters are wavelength 200 nm, power ≥1W, scanning speed 5m / s, frequency 1000kHz, and then clean it in a cleaning machine. The cleaning method is acid pickling and drying after cleaning.

[0187] 6. Use LPCVD to deposit a 3nm tunnel oxide layer and a 250nmnm polysilicon layer.

[0188] 7. Place the silicon wafer into a phosphorus-doped tube for phosphorus doping, using phosphorus oxychloride as the phosphorus source, and dope at 800-900°C for 120 minutes. During sintering, set the wavelength to 532nm and the pulse energy to 300μJ to produce P+ and P++ Poly layers in the P zone.

[0189] 8. Use laser to prepare Gap area on silicon wafer with wavelength of 200 nm, power ≥1W, scanning speed of 5m / s and frequency of 2000kHz, then pickle and wash with water and dry in a cleaning machine.

[0190] 9. Use 0.5% NaOH solution for etching for 600 seconds to prepare a velvet surface on the front side of the silicon wafer.

[0191] 10. Place the silicon wafer in 0.5% HF for pickling for 1200 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0192] 11. ALD atomic layer deposition method is adopted, TMA is used as a precursor, and the reaction temperature is controlled at 300°C to deposit a dense Al2O3 passivation layer with a thickness of 6nm on the front and back of the silicon wafer. Then, PECVD method is adopted to deposit a 70nm SiO2 anti-reflection layer on the front and back of the silicon wafer. The passivation layer and the anti-reflection layer form a dielectric layer.

[0193] 12. Print Ag paste on the back of the silicon wafer, dry and sinter it to obtain the back metal electrode.

[0194] The batteries in Examples 1-25 and Comparative Examples 1-2 were tested under the same conditions. The test results are shown in Table 1.

[0195] Table 1 Test results of battery of embodiment and comparative example ;

[0196] As can be seen from Table 1, from the comparison of the test data of Examples 1-25 and Comparative Example 1, it can be seen that when the TBC battery deposits a mask on the dopant source layer of the first conductive type impurity, for the dopant source of the first conductive type impurity with the same thickness, the doping concentration can be relatively high, which will increase the open circuit voltage, short circuit current, and fill factor of the battery, thereby improving the conversion efficiency of the battery. From the comparison of the test data of Examples 1-25 and Comparative Example 2, it can be seen that when the TBC battery deposits the dopant source layer and mask layer of the first conductive type impurity, the open circuit voltage, short circuit current, and fill factor of the battery are all improved, thereby improving the conversion efficiency of the battery; the process time for battery preparation is shortened. It can be seen from the test data of Examples 1-5 and 6-7 that when the thickness of the dopant source layer of the first conductive type impurity is between 5nm and 60nm, the open circuit voltage, short circuit current, fill factor and conversion efficiency of the battery are better; it can be seen from the test data of Examples 8-11 and 12-13 that when the thickness of the dopant source layer of the first conductive type impurity is between 5nm and 60nm, the open circuit voltage, short circuit current, fill factor and conversion efficiency of the battery are better; it can be seen from the test data of Examples 14-17 and 18-19 that when the thickness of the dopant source layer of the first conductive type impurity is between 5nm and 60nm, the open circuit voltage, short circuit current, fill factor and conversion efficiency of the battery are better; it can be seen from the test data of Examples 20-23 and 24-25 that when the thickness of the dopant source layer of the first conductive type impurity is between 5nm and 60nm, the open circuit voltage, short circuit current, fill factor and conversion efficiency of the battery are better.

[0197] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description here should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in the field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a TBC battery, characterized in that: The steps include: S1 forms a dielectric region and a polysilicon layer; S2 forming a dopant source layer of first conductivity type impurities and a mask layer; S3 film opening and cleaning; S4 co-doping of impurities of different conductivity types in one step; The TBC cell includes a substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, a dielectric region and a polysilicon layer being sequentially arranged on the back side of the substrate silicon wafer in a direction away from the substrate silicon wafer, and an impurity source layer of the first conductive type impurities being formed outside the polysilicon layer.

2. The method for preparing a TBC battery according to claim 1, characterized in that: The thickness of the dopant source layer of the first conductive type impurities is 5nm-60nm.

3. The method for preparing a TBC battery according to claim 1, characterized in that: The S2 forms a dopant source layer of first conductivity type impurities, which is formed by CVD at a temperature of 300° C. to 800° C. and the raw materials include boron source gas or phosphorus source gas; The boron source gas is at least one of BH3, TMB, BCl3, and BBr3; The phosphorus source gas is at least one of PH3 and POCl3.

4. The method for preparing a TBC battery according to claim 1, characterized in that: The S2 dopant source layer of the first conductive type impurities is a silicon compound layer containing first conductive type impurities, and the first conductive type impurities are boron, gallium or phosphorus.

5. The method for preparing a TBC battery according to claim 1, characterized in that: The film opening method in the S3 film opening and cleaning is laser film opening, and the parameters of the laser film opening are set as: wavelength 200nm-1064nm, power ≥1W, scanning speed 5m / s-50m / s, frequency 200kHz-2000kHz.

6. The method for preparing a TBC battery according to claim 1, characterized in that: The cleaning method in the S3 film opening and cleaning is pickling, using hydrofluoric acid with a concentration of 0.5%-50% for pickling.

7. The method for preparing a TBC battery according to claim 1, characterized in that: The mask layer of the S2 first conductivity type impurity is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the mask layer is 2nm-200nm.

8. The method for preparing a TBC battery according to claim 1, characterized in that: The doping temperature of the S4 co-doping of different conductive type impurities in one step is 600° C.-1000° C., and the doping time is 5 min-180 min.

9. The method for preparing a TBC battery according to claim 1, characterized in that: In the S4 one-step co-doping of different conductive type impurities, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used to simultaneously form a first conductive type impurity region and a second conductive type impurity region, the first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the number of times the different conductive type impurities are co-doped in one step is at least once.

10. The method for preparing a TBC battery according to claim 1, characterized in that: After the S4 one-step co-doping step of impurities of different conductive types, the method further includes a step of preparing a Gap region. The Gap region is prepared by automatically forming the S4 one-step co-doping step of impurities of different conductive types or by laser preparation. The setting parameters of the laser preparation are: wavelength 200 nm-1064 nm, power ≥1W, scanning speed 5m / s-50m / s, and frequency 200kHz-2000kHz.

11. The method for preparing a TBC battery according to claim 10, characterized in that: The preparation step of the Gap area also includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer or a Gap area texturing surface on the back side, and the morphology and size of the front texturing surface and the Gap area texturing surface are the same or different.

12. The method for preparing a TBC battery according to claim 1, characterized in that: Before the S4 step of co-doping impurities of different conductive types, it also includes a laser selective doping step, with a scanning speed of 5m / s-50m / s, a frequency of 200kHz-2000kHz, a wavelength of the laser selective doping of 200nm-1064nm, a power ≥1W, a scanning speed of 5m / s-50m / s, and a frequency of 200kHz-2000kHz, and the laser selective doping obtains a local heavily doped region of the conductive type impurity region.

13. A TBC battery prepared by the method for preparing a TBC battery according to any one of claims 1 to 12, characterized in that: The invention comprises a substrate silicon wafer, wherein the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, wherein the front side of the substrate silicon wafer comprises a front velvet surface and a second dielectric layer; and the back side of the substrate silicon wafer comprises a dielectric region, a second conductive type impurity region, a first conductive type impurity region, a first dielectric layer, a metal electrode and a Gap region; The dielectric region is a tunnel oxide layer, the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 5nm-60nm; The second conductive type impurity region and the first conductive type impurity region are formed simultaneously in one or more conductive dopant one-step co-doping steps; In the conductive dopant co-doping step, at least once, a doping source having impurities of a second conductivity type opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region on the back side of the substrate silicon wafer is electrically opposite to the second conductive type impurity region on the front side of the substrate silicon wafer, and a local area of ​​the metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

14. A TBC battery according to claim 13, characterized in that: The c-Si region or polysilicon layer of the second conductive type impurity region is formed by film opening and cleaning, the film opening method is at least one of laser, etching slurry, and photolithography, the cleaning method includes at least one of acid washing, alkaline washing, and acid washing followed by alkaline washing, and the one-step co-doping is to achieve the doping of the doping sources of the first conductive type impurities and the second conductive type impurities under the same high temperature conditions.

15. A TBC battery according to claim 13, characterized in that: A Gap region velvet surface is also provided on the back side of the substrate silicon wafer, and the Gap region velvet surface is different in shape and size from the front velvet surface; the first conductive type impurity region and / or the second conductive type impurity region are also provided with a heavily doped region.

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