Wafer test track generation method and system, electronic equipment and storage medium

Abstract

The invention relates to the technical field of integrated circuits, and particularly discloses a wafer test track generation method and system, electronic equipment and a storage medium, and the method comprises the steps: obtaining the size information of a to-be-tested wafer and a test rectangular region of a probe card used for testing the to-be-tested wafer, and determining any point on the circumference of the to-be-tested wafer as a target point; determining the extension direction of a tangent line where the target point is located as the horizontal direction, determining the vertical line direction of the tangent line as the vertical direction, and dividing the wafer to be tested into a plurality of levels along the vertical direction according to any side length corresponding to the test rectangular area and the size information, determining the minimum TD number required by testing of each level along the horizontal direction; and determining a test track of the wafer to be tested according to the minimum TD number corresponding to each level and the travel path direction of the probe card. According to the invention, the wafer testing speed can be improved, the wafer testing time is shortened, and the production efficiency is improved.

Description

Background Art

[0002] After entering the product information on the probe station, the probe station will automatically generate a test track. The final test will be carried out according to the track. The number of TD (Touch down) is fixed, but the automatically generated track may be unreasonable. Figure 2 As shown, when the existing method is used to automatically generate the track, the TD at the edge of the wafer pierces fewer wafers, which greatly wastes the resources of the test area. The existing method for generating wafer test tracks results in a large number of TDs, a long test time, and low production efficiency.

[0003] Therefore, it is urgent to provide a technical solution to solve the above problems. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a wafer test track generation method, system, electronic device and storage medium.

[0005] In a first aspect, the present invention provides a method for generating a wafer test trajectory, and the technical solution of the method is as follows:

[0006] Acquire the size information of the wafer to be tested and the test rectangular area of ​​the probe card used to test the wafer to be tested, and determine any point on the circumference of the wafer to be tested as the target point; wherein the test rectangular area corresponds to a TD of the probe card;

[0007] Determine the extension direction of the tangent where the target point is located as the horizontal direction, and determine the perpendicular direction of the tangent as the vertical direction, divide the wafer to be tested into multiple levels along the vertical direction according to the length of any side corresponding to the test rectangular area and the size information, and determine the minimum number of TDs required for testing each level along the horizontal direction; wherein the upper edge of the test rectangular area of ​​the first level is aligned with the tangent;

[0008] The test track of the wafer to be tested is determined according to the minimum number of TDs corresponding to each level and the travel direction of the probe card.

[0009] The beneficial effects of a wafer test track generation method of the present invention are as follows:

[0010] The method of the present invention can increase wafer testing speed, reduce wafer testing time, and improve production efficiency.

[0011] Based on the above solution, a wafer test track generation method of the present invention can also be improved as follows.

[0012] In an optional manner, the method further includes:

[0013] The test rectangular area of ​​the probe card is determined according to the number of probes and the layout of the probes of the probe card.

[0014] In an optional manner, the method further includes:

[0015] Performing multiple fine-tuning on the upper edge of the test rectangular area of ​​the first level to obtain a test track corresponding to each fine-tuning;

[0016] Among all the test tracks, the test track with the smallest total TD number is determined as the target test track of the wafer to be tested.

[0017] In an optional manner, the range of multiple fine-tuning is: adjusting the distance corresponding to the length of any side along the vertical direction.

[0018] In the above optional manner, the optimal wafer test trajectory is further screened, thereby increasing the wafer test speed, reducing the wafer test time and improving production efficiency.

[0019] In a second aspect, the present invention provides a wafer test trajectory generation system, the technical solution of the system is as follows:

[0020] It includes: processing module, division module and generation module;

[0021] The processing module is used to: obtain the size information of the wafer to be tested and the test rectangular area of ​​the probe card used to test the wafer to be tested, and determine any point on the circumference of the wafer to be tested as the target point; wherein the test rectangular area corresponds to a TD of the probe card;

[0022] The division module is used to: determine the extension direction of the tangent where the target point is located as the horizontal direction, and determine the perpendicular direction of the tangent as the vertical direction, divide the wafer to be tested into multiple levels along the vertical direction according to the length of any side corresponding to the test rectangular area and the size information, and determine the minimum number of TDs required for each level to be tested along the horizontal direction; wherein the upper edge of the test rectangular area of ​​the first level is aligned with the tangent;

[0023] The generating module is used to determine the test track of the wafer to be tested according to the minimum number of TDs corresponding to each level and the path direction of the probe card.

[0024] The beneficial effects of a wafer test trajectory generation system of the present invention are as follows:

[0025] The system of the present invention can increase wafer testing speed, reduce wafer testing time, and improve production efficiency.

[0026] Based on the above solution, a wafer test trajectory generation system of the present invention can also be improved as follows.

[0027] In an optional manner, the method further includes: a preprocessing module; the preprocessing module is used to:

[0028] The test rectangular area of ​​the probe card is determined according to the number of probes and the layout of the probes of the probe card.

[0029] In an optional manner, the method further includes: an optimization module; the optimization module is used to:

[0030] Performing multiple fine-tuning on the upper edge of the test rectangular area of ​​the first level to obtain a test track corresponding to each fine-tuning;

[0031] Among all the test tracks, the test track with the smallest total TD number is determined as the target test track of the wafer to be tested.

[0032] In an optional manner, the range of multiple fine-tuning is: adjusting the distance corresponding to the length of any side along the vertical direction.

[0033] In the above optional manner, the optimal wafer test trajectory is further screened, thereby increasing the wafer test speed, reducing the wafer test time and improving production efficiency.

[0034] In a third aspect, a technical solution of an electronic device of the present invention is as follows:

[0035] The invention comprises a memory, a processor and a program stored in the memory and running on the processor. When the processor executes the program, the steps of the wafer test track generation method of the present invention are realized.

[0036] In a fourth aspect, the present invention provides a computer-readable storage medium having the following technical solution:

[0037] Instructions are stored in the computer-readable storage medium. When the computer-readable storage medium reads the instructions, the computer-readable storage medium executes the steps of the wafer test track generation method of the present invention.

[0038] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are only used to illustrate the embodiments and are not to be considered as limiting the present invention. In addition, the same reference symbols are used to represent the same components throughout the accompanying drawings. In the accompanying drawings:

[0040] Figure 1A schematic diagram of a process flow of an embodiment of a method for generating a wafer test track according to the present invention;

[0041] Figure 2 It is a schematic diagram of the existing wafer test track;

[0042] Figure 3 This is a schematic diagram of the target test trajectory;

[0043] Figure 4 A schematic structural diagram of an embodiment of a wafer test trajectory generation system of the present invention;

[0044] Figure 5 The figure is a schematic structural diagram of an embodiment of an electronic device of the present invention. DETAILED DESCRIPTION

[0045] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0046] Figure 1 A flow chart of an embodiment of a wafer test trajectory generation method provided by the present invention is shown, and the wafer test trajectory generation method can be executed by an electronic device such as a terminal device or a server. Among them, the terminal device can be any fixed or mobile terminal such as a user equipment (User Equipment, UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The server can be a single server or a server cluster composed of multiple servers. Any electronic device can implement the wafer test trajectory generation method by calling the computer-readable instructions stored in the memory through the processor. As Figure 1 As shown, the following steps are included:

[0047] S1. Acquire size information of a wafer to be tested and a test rectangular area of ​​a probe card used to test the wafer to be tested, and determine any point on the circumference of the wafer to be tested as a target point.

[0048] Among them, the wafer to be tested is the wafer that needs to generate the test track in this embodiment. The size information includes: the size, area and other parameters of the wafer to be tested. The test rectangular area corresponds to a TD of the probe card. According to the number of probes and the probe layout of the probe card, the test rectangular area of ​​the probe card is determined. The target point is any point selected on the circumference of the wafer to be tested.

[0049] S2. Determine the extension direction of the tangent where the target point is located as the horizontal direction, and determine the perpendicular direction of the tangent as the vertical direction. According to the length of any side corresponding to the test rectangular area and the size information, divide the wafer to be tested into multiple levels along the vertical direction, and determine the minimum number of TDs required for testing each level along the horizontal direction.

[0050] The tangent line at the target point is: the tangent line of the wafer to be tested made through the target point. The length of any side corresponding to the test rectangular area defaults to the length of the short side of the test matrix area. The upper edge of the test rectangular area of ​​the first level is aligned with the tangent line.

[0051] S3. Determine the test track of the wafer to be tested according to the minimum number of TDs corresponding to each level and the travel direction of the probe card.

[0052] The travel direction of the probe card is set to a Z-shaped travel direction by default, that is, for any level, the test is first performed from left to right along the horizontal direction; for each level, the test is performed from top to bottom along the vertical direction.

[0053] In an optional manner, the method further includes:

[0054] The upper edge of the test rectangular area of ​​the first level is fine-tuned multiple times to obtain a test track corresponding to each fine-tuning.

[0055] Among them, the range of multiple fine-tuning is: adjusting the distance corresponding to any side length in the vertical direction, that is, the total range of multiple fine-tuning cannot exceed the range of the target distance value of the upward translation relative to the wafer to be tested from the starting position (the position where the upper edge of the test rectangular area of ​​the first level is aligned with the tangent), and the target distance value is the distance of any side length corresponding to the test rectangular area.

[0056] Among all the test tracks, the test track with the smallest total TD number is determined as the target test track of the wafer to be tested.

[0057] Among them, the target test track is the test track with the smallest total TD number, that is, the test track after the wafer to be tested is optimized. Figure 3 As shown in the figure, the number of TDs of the target test track is 29, while the number of TDs of the existing wafer test track is 34. The number of TDs is reduced from 34TD to 29TD, which is a reduction of 5TD, or 14.7%. Since the test time of each TD is the same, the test time of the wafer to be tested is reduced by 14.7%.

[0058] The technical solution of this embodiment can increase the wafer testing speed, reduce the wafer testing time, and improve production efficiency.

[0059] Figure 4FIG. 2 is a schematic diagram showing a structure of an embodiment of a wafer test trajectory generation system 200 provided by the present invention. Figure 4 As shown, the system 200 includes: a processing module 210, a dividing module 220 and a generating module 230;

[0060] The processing module 210 is used to: obtain the size information of the wafer to be tested and the test rectangular area of ​​the probe card used to test the wafer to be tested, and determine any point on the circumference of the wafer to be tested as a target point; wherein the test rectangular area corresponds to a TD of the probe card;

[0061] The division module 220 is used to: determine the extension direction of the tangent where the target point is located as the horizontal direction, and determine the perpendicular direction of the tangent as the vertical direction, divide the wafer to be tested into multiple levels along the vertical direction according to the length of any side corresponding to the test rectangular area and the size information, and determine the minimum number of TDs required for each level to be tested along the horizontal direction; wherein the upper edge of the test rectangular area of ​​the first level is aligned with the tangent;

[0062] The generating module 230 is used to determine the test track of the wafer to be tested according to the minimum number of TDs corresponding to each level and the travel direction of the probe card.

[0063] In an optional manner, the method further includes: a preprocessing module; the preprocessing module is used to:

[0064] The test rectangular area of ​​the probe card is determined according to the number of probes and the layout of the probes of the probe card.

[0065] In an optional manner, the method further includes: an optimization module; the optimization module is used to:

[0066] Performing multiple fine-tuning on the upper edge of the test rectangular area of ​​the first level to obtain a test track corresponding to each fine-tuning;

[0067] Among all the test tracks, the test track with the smallest total TD number is determined as the target test track of the wafer to be tested.

[0068] In an optional manner, the range of multiple fine-tuning is: adjusting the distance corresponding to the length of any side along the vertical direction.

[0069] The technical solution of this embodiment can increase the wafer testing speed, reduce the wafer testing time, and improve production efficiency.

[0070] The above-mentioned parameters and steps for each module to implement corresponding functions in the wafer test trajectory generation system 200 of this embodiment can refer to the parameters and steps in the embodiment of the wafer test trajectory generation method above, and will not be repeated here.

[0071] like Figure 5 As shown, an electronic device 300 according to an embodiment of the present invention includes a processor 320, the processor 320 is coupled to a memory 310, and the memory 310 stores at least one computer program 330, and the at least one computer program 330 is loaded and executed by the processor 320, so that the electronic device 300 implements any of the above-mentioned wafer test track generation methods, specifically:

[0072] The electronic device 300 may have relatively large differences due to different configurations or performances, and may include one or more processors 320 (Central Processing Units, CPU) and one or more memories 310, wherein the one or more memories 310 store at least one computer program 330, and the at least one computer program 330 is loaded and executed by the one or more processors 320, so that the electronic device 300 implements any of the wafer test track generation methods provided in the above embodiments. Of course, the electronic device 300 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output, and the electronic device 300 may also include other components for implementing device functions, which will not be repeated here.

[0073] A computer-readable storage medium according to an embodiment of the present invention stores at least one computer program, and the at least one computer program is loaded and executed by a processor so that a computer implements any of the above-mentioned wafer test trajectory generation methods.

[0074] Optionally, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0075] In an exemplary embodiment, a computer program product or a computer program is also provided, the computer program product or the computer program comprising computer instructions, the computer instructions being stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the electronic device performs any of the above-mentioned wafer test trace generation methods.

[0076] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects and represent the definition of a specific order or sequence. The order of use of similar objects can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than the order shown or described.

[0077] Those skilled in the art know that the present invention can be implemented as a system, method or computer program product. Therefore, the present disclosure can be specifically implemented in the following forms, namely: it can be complete hardware, it can be complete software (including firmware, resident software, microcode, etc.), or it can be a combination of hardware and software, which is generally referred to as "circuit", "module" or "system" herein. In addition, in some embodiments, the present invention can also be implemented in the form of a computer program product in one or more computer-readable media, and the computer-readable medium contains computer-readable program code.

[0078] Any combination of one or more computer-readable media can be used. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0079] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A wafer test track generation method, characterized in that: include: Acquire the size information of the wafer to be tested and the test rectangular area of ​​the probe card used to test the wafer to be tested, and determine any point on the circumference of the wafer to be tested as the target point; wherein the test rectangular area corresponds to a TD of the probe card; Determine the extension direction of the tangent where the target point is located as the horizontal direction, and determine the perpendicular direction of the tangent as the vertical direction, divide the wafer to be tested into multiple levels along the vertical direction according to the length of any side corresponding to the test rectangular area and the size information, and determine the minimum number of TDs required for testing each level along the horizontal direction; wherein the upper edge of the test rectangular area of ​​the first level is aligned with the tangent; The test track of the wafer to be tested is determined according to the minimum number of TDs corresponding to each level and the travel direction of the probe card.

2. The wafer test track generation method according to claim 1, characterized in that: Also includes: The test rectangular area of ​​the probe card is determined according to the number of probes and the layout of the probes of the probe card.

3. The wafer test track generation method according to claim 1, characterized in that: Also includes: Performing multiple fine-tuning on the upper edge of the test rectangular area of ​​the first level to obtain a test track corresponding to each fine-tuning; Among all the test tracks, the test track with the smallest total TD number is determined as the target test track of the wafer to be tested.

4. The wafer test track generation method according to claim 3, characterized in that: The range of multiple fine-tuning is: adjusting the distance corresponding to the length of any side along the vertical direction.

5. A wafer test trajectory generation system, characterized in that: include: Processing module, partitioning module and generation module; The processing module is used to: obtain the size information of the wafer to be tested and the test rectangular area of ​​the probe card used to test the wafer to be tested, and determine any point on the circumference of the wafer to be tested as the target point; wherein the test rectangular area corresponds to a TD of the probe card; The division module is used to: determine the extension direction of the tangent where the target point is located as the horizontal direction, and determine the perpendicular direction of the tangent as the vertical direction, divide the wafer to be tested into multiple levels along the vertical direction according to the length of any side corresponding to the test rectangular area and the size information, and determine the minimum number of TDs required for each level to be tested along the horizontal direction; wherein the upper edge of the test rectangular area of ​​the first level is aligned with the tangent; The generating module is used to determine the test track of the wafer to be tested according to the minimum number of TDs corresponding to each level and the path direction of the probe card.

6. The wafer test trajectory generation system according to claim 5, characterized in that: Also includes: Preprocessing module; The pre-processing module is used for: The test rectangular area of ​​the probe card is determined according to the number of probes and the layout of the probes of the probe card.

7. The wafer test trajectory generation system according to claim 6, characterized in that: Also includes: Optimization module; The optimization module is used to: Performing multiple fine-tuning on the upper edge of the test rectangular area of ​​the first level to obtain a test track corresponding to each fine-tuning; Among all the test tracks, the test track with the smallest total TD number is determined as the target test track of the wafer to be tested.

8. The wafer test trajectory generation system according to claim 7, characterized in that: The range of multiple fine-tuning is: adjusting the distance corresponding to the length of any side along the vertical direction.

9. An electronic device, characterized in that: The electronic device includes a processor, the processor is coupled to a memory, at least one computer program is stored in the memory, and the at least one computer program is loaded and executed by the processor so that the electronic device implements the wafer test trajectory generation method as described in any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one computer program, and the at least one computer program is loaded and executed by a processor so that the computer-readable storage medium implements the wafer test trajectory generation method according to any one of claims 1 to 4.

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