Test circuit and working method thereof

Abstract

The invention discloses a test circuit and a working method of the test circuit, the test circuit is used for measuring a nominal value of a to-be-tested element, the test circuit comprises a first transmission gate, the first transmission gate comprises a first input end, a first output end, a first control end and a second control end, and the first input end is coupled with a power supply voltage end; the second transmission gate comprises a second input end, a second output end, a third control end and a fourth control end, the second output end is connected with the first output end, and the second input end is grounded; the input end of the first phase inverter is connected with the first control end, and the output end of the first phase inverter is connected with the second control end; the input end of the second phase inverter is connected with the fourth control end, and the output end of the second phase inverter is connected with the third control end; and a to-be-tested element, wherein the first end of the to-be-tested element is connected with the first output end. The test circuit can accurately measure the nominal value of the element to be tested.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a testing circuit and a working method of the testing circuit. Background Art

[0002] In the test of integrated circuits, capacitance is one of the most basic test items. For MOS tubes, accurate measurement of capacitance value is the basis for accurate model establishment. However, as the size of MOS tubes shrinks, on the one hand, the order of magnitude of the capacitance values ​​of its various parts continues to shrink. On the other hand, due to the increasingly complex generation of parasitic capacitance, the relative error of capacitance measurement value is getting larger and larger, which will lead to a large number of errors in the process of establishing MOS tube models, making the model inaccurate and ultimately affecting the performance and reliability of circuit design.

[0003] In the prior art, a test structure based on the charge injection effect is adopted. The relationship between the amount of charge required for charging the capacitor to be measured and the value of the capacitor to be measured is utilized, and the value of the capacitor to be measured is calculated by measuring the amount of charge required for charging the capacitor. However, due to the influence of the charge injection effect and the mismatch between the reference end and the measuring end devices, the test structure based on the charge injection effect still has great limitations in measurement accuracy.

[0004] In the test structure without charge injection effect, there is no need to consider the charge injection effect, and there is only one measurement branch. Compared with the test structure based on the charge injection effect, this structure does not need to consider the influence of the mismatch between the reference end and the measurement end device. However, due to the limited voltage transmission capability of the MOS tube and the fact that the on-state voltage of the MOS tube is affected by the drain voltage, it is difficult to accurately control the voltage across the device under test during the actual measurement process. This will cause a certain voltage difference to exist across the device under test during the parasitic capacitance measurement process, making its measurement value inaccurate, and ultimately resulting in a large error in the calculated capacitance value under test. Summary of the invention

[0005] The technical problem solved by the present invention is that there is an error in the measurement value of the component to be measured.

[0006] To solve the above technical problems, an embodiment of the present invention provides a test circuit for measuring the nominal value of a component under test, comprising: a first transmission gate, comprising a first input terminal, a first output terminal, a first control terminal and a second control terminal, the first input terminal being coupled to a power supply voltage terminal; a second transmission gate, comprising a second input terminal, a second output terminal, a third control terminal and a fourth control terminal, the second output terminal being connected to the first output terminal, and the second input terminal being grounded; a first inverter, the input terminal of the first inverter being connected to the first control terminal, and the output terminal of the first inverter being connected to the second control terminal; a second inverter, the input terminal of the second inverter being connected to the fourth control terminal, and the output terminal of the second inverter being connected to the third control terminal; and a component under test, the first terminal of the component under test being connected to the first output terminal.

[0007] Optionally, the test circuit further includes: an ammeter, a first end of the ammeter is connected to the power supply voltage end, and a second end of the ammeter is connected to the first input end.

[0008] Optionally, the first transmission gate includes: a first PMOS tube and a first NMOS tube, the gate of the first PMOS tube is the first control terminal, the gate of the first NMOS tube is the second control terminal, the source of the first PMOS tube is coupled to the drain of the first NMOS tube and serves as the first input terminal, and the drain of the first PMOS tube is coupled to the source of the first NMOS tube and serves as the first output terminal.

[0009] Optionally, the second transmission gate includes: a second PMOS tube and a second NMOS tube, the gate of the second PMOS tube is the third control terminal, the gate of the second NMOS tube is the fourth control terminal, the source of the second PMOS tube is coupled to the drain of the second NMOS tube and serves as the second output terminal, and the drain of the second PMOS tube is coupled to the source of the second NMOS tube and serves as the second input terminal.

[0010] Optionally, the component to be tested includes a capacitor to be tested.

[0011] Optionally, the test circuit also includes: a test module coupled to the first control terminal, the third control terminal, the first input terminal and the second terminal of the component to be tested, the test module being used to apply a clock signal to the first control terminal and the third control terminal, apply a control signal to the second terminal of the component to be tested, and obtain a current result of the first input terminal, and obtain a nominal value of the component to be tested based on the current result.

[0012] Optionally, the clock signal includes a first clock signal and a second clock signal, the control signal includes a first control signal and a second control signal, and the current result includes a first current result and a second current result; the test module is used to apply the first clock signal to the first control terminal, and apply the second clock signal to the third control terminal; apply the first control signal or the second control signal to the second terminal of the element to be tested, and after applying the first clock signal, the second clock signal and the first control signal, obtain the first current result of the first input terminal, after applying the second control signal, obtain the second current result of the first input terminal, and obtain the nominal value of the element to be tested based on the first current result and the second current result.

[0013] Optionally, the frequencies of the first clock signal, the second clock signal, the first control signal, and the second control signal are the same, and a measurement cycle includes a first time node, a second time node, a third time node, a fourth time node, and a fifth time node in sequence; within a measurement cycle, after the first clock signal is converted from the first level to the second level at the first time node, it maintains the second level to the fourth time node, and after the first time node is converted from the second level to the first level, it maintains the first level to the fifth time node; within a measurement cycle, after the second clock signal is converted from the first level to the second level at the second time node, it maintains the second level to the third time node, and after the third time node is converted from the second level to the first level, it maintains the first level to the fifth time node.

[0014] Optionally, the first control signal maintains the second level from the first time node to the fifth time node.

[0015] Optionally, the measurement module obtains a first current result of the first input terminal between the second time node and the third time node.

[0016] Optionally, the second control signal is converted from the second level to the first level between the first time node and the second time node, and maintains the first level to the third time node, and is converted from the first level to the second level between the third time node and the fourth time node, and maintains the second level to the fifth time node.

[0017] Optionally, the measurement module obtains the second current result of the first input terminal between the second time node and the third time node or between the fourth time node and the fifth time node.

[0018] The technical solution of the present invention also provides a working method of the test circuit, comprising: applying a clock signal to a first control terminal and a third control terminal, applying a control signal to a second terminal of the component to be tested, and obtaining a current result of the first input terminal, and obtaining a nominal value of the component to be tested based on the current result.

[0019] Optionally, the clock signal includes a first clock signal and a second clock signal, the control signal includes a first control signal and a second control signal, and the current result includes a first current result and a second current result; applying the clock signal to the first control terminal and the third control terminal, applying the control signal to the second terminal of the element to be measured, and obtaining the current result of the first input terminal, and obtaining the nominal value of the element to be measured based on the current result, including: applying the first clock signal to the first control terminal, applying the second clock signal to the third control terminal, and applying the first control signal to the second terminal of the element to be measured, to obtain the first current result of the first input terminal; applying the first clock signal to the first control terminal, applying the second clock signal to the third control terminal, and applying the second control signal to the second terminal of the element to be measured, to obtain the second current result of the first input terminal; obtaining the nominal value of the element to be measured based on the first current result and the second current result.

[0020] Optionally, the frequencies of the first clock signal, the second clock signal, the first control signal, and the second control signal are the same, and a measurement cycle includes a first time node, a second time node, a third time node, a fourth time node, and a fifth time node in sequence; within a measurement cycle, after the first clock signal is converted from the first level to the second level at the first time node, it maintains the second level to the fourth time node, and after it is converted from the second level to the first level at the fourth time node, it maintains the first level to the fifth time node; within a measurement cycle, after the second clock signal is converted from the first level to the second level at the second time node, it maintains the second level to the third time node, and after it is converted from the second level to the first level at the third time node, it maintains the first level to the fifth time node.

[0021] Optionally, the first control signal maintains the second level from the first time node to the fifth time node.

[0022] Optionally, obtaining the first current result of the first input terminal includes: obtaining the first current result of the first input terminal between the second time node and the third time node.

[0023] Optionally, the second control signal is converted from the second level to the first level between the first time node and the second time node, and maintains the first level to the third time node, and is converted from the first level to the second level between the third time node and the fourth time node, and maintains the second level to the fifth time node.

[0024] Optionally, obtaining the second current result of the first input terminal includes: obtaining the second current result of the first input terminal between the second time node and the third time node or between the fourth time node and the fifth time node.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] The test circuit provided in the technical solution of the present invention comprises a first transmission gate and a second transmission gate. When measuring the nominal value of the component to be measured, the component to be measured is charged and discharged through the first transmission gate and the second transmission gate to achieve complete voltage transfer, thereby being able to accurately control the voltage across the component to be measured. In addition, the technical solution of the present invention has only one measurement branch, which avoids the influence of the measurement accuracy caused by the mismatch of the components to be measured in the two measurement branches.

[0027] Furthermore, the test circuit provided in the technical solution of the present invention has an ammeter, through which the charging current under different states is obtained, and finally a high-precision test of the nominal value of the component to be tested is achieved.

[0028] Furthermore, the first transmission gate and the second transmission gate in the technical solution of the present invention are both composed of a PMOS tube and an NMOS tube. When the on-resistance in the NMOS tube increases, the on-resistance in the PMOS tube decreases, so that the on-resistance value in the transmission gate remains balanced, and the on-resistance value is not affected by the source voltage or the drain voltage.

[0029] The working method of the test circuit provided in the technical solution of the present invention makes the voltages at both ends of the component to be tested the same or opposite by applying different electrical levels to the first transmission gate, the second transmission gate and the second end of the component to be tested during the measurement period, thereby obtaining the first current result and the second current result, and obtaining the nominal value of the component to be tested based on the first current result and the second current result; since the conduction and shutdown of the transmission gate are only related to the applied clock signal and control signal, and have nothing to do with the source-drain voltage, the voltage range of the nominal value of the component to be tested that can be measured using the transmission gate is wider, further realizing the accurate measurement of the nominal value of the component to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of a test structure based on charge injection effect;

[0031] Figure 2 It is a schematic diagram of a test structure without charge injection effect;

[0032] Figure 3 A schematic diagram of a test circuit provided by an embodiment of the present invention is shown in FIG. Figure 1 ;

[0033] Figure 4 A schematic diagram of a test circuit provided by an embodiment of the present invention is shown in FIG. Figure 2 ;

[0034] Figure 5 The timing of a signal in a test circuit provided by an embodiment of the present invention is Figure 1 ;

[0035] Figure 6 The timing of a signal in a test circuit provided by an embodiment of the present invention is Figure 2 . DETAILED DESCRIPTION

[0036] From the background technology, we can understand that the existing test structure has the problem of not being able to take into account both the accuracy of measurement and the single measurement object. Now we analyze the reasons in combination with the existing test structure:

[0037] Figure 1 It is a structural schematic diagram of a test structure based on charge injection effect.

[0038] Please refer to Figure 1 The test structure includes: a first PMOS tube PM1, a second PMOS tube PM2, a first NMOS tube NM1, a second NMOS tube NM2, a first ammeter I', a second ammeter I, a first metal interconnection line Metal1 and a second metal interconnection line Metal2, wherein the first PMOS tube PM1 and the first NMOS tube NM1 form a first inverter, and the second PMOS tube PM2 and the second NMOS tube NM2 form a second inverter.

[0039] Below Figure 1 The working principle of the capacitance test structure based on the charge injection effect is explained.

[0040] Figure 1 The first inverter side is connected to the capacitor calibration structure, and the second inverter side is connected to the grounded capacitor structure to be measured. The first ammeter I' and the second ammeter I respectively measure the current flowing through the first inverter and the second inverter, and the input signals of the first PMOS tube PM1, the second PMOS tube PM2, the first NMOS tube NM1 and the second NMOS tube NM2 are respectively controlled by two non-overlapping clock signals V1 and V2. The frequencies of the clock signals V1 and V2 are the same, but the duty cycles in the signal cycles are different, that is, the low-level duration of V1 completely includes the low-level duration of V2, and the high-level duration of V2 completely includes the high-level duration of V1, ensuring that at any time when the capacitance value is measured, in one inverter, only one device of the NMOS and PMOS tubes can be turned on.

[0041] When the PMOS tube is turned on and the NMOS tube is turned off, the capacitor structure to be tested in the right test structure is charged; when the NMOS tube is turned on and the PMOS tube is turned off, these charges are released to the ground terminal. The PMOS tube and the NMOS tube can respectively realize the charging and discharging of the capacitor structure to be tested, and the current caused by the charge change can be measured by the ammeter, so the capacitor CDUT to be tested can be calculated by the following formula:

[0042] I-I′ = CDUT·Vdd·f, where f is the signal frequency of clock signals V1 and V2, and Vdd is the power supply voltage.

[0043] In the above solution, by adding capacitors on both the left and right sides, the capacitance value of the capacitor under test is then measured. However, the addition of the two metal interconnects Metal1 and Metal2 will bring the influence of parasitic capacitance to the measurement structure. Also, due to the charge injection effect and the influence brought by the mismatch between the reference terminal and the measurement terminal devices, the test structure based on the charge injection effect still has relatively large limitations in measurement accuracy, thus affecting the measurement accuracy of the capacitance value of the capacitor under test.

[0044] Figure 2 It is a schematic structural diagram of a test structure without charge injection effect.

[0045] Please refer to Figure 2 , the charge injection induced error-free structure includes: PMOS transistor V p , NMOS transistor V N , ammeter A, capacitor under test C, and PAD control circuit. Among them, the capacitance test structure without charge injection effect also includes parasitic capacitance C P .

[0046] In the above solution, compared with the test structure based on the charge injection effect, this structure does not need to consider the influence brought by the mismatch between the reference terminal and the measurement terminal devices. However, since the MOS transistor is completely turned off when Vgs < Vth, the voltage transfer ability of the MOS transistor is limited, and the turn-on voltage of the MOS transistor is affected by the drain voltage. Therefore, during the actual measurement process, it is difficult to accurately control the voltage across the device under test, which will cause a certain voltage difference across the device under test during the measurement of the parasitic capacitance, making its measurement value inaccurate, and ultimately resulting in a large error in the calculated capacitance value of the capacitor under test.

[0047] To solve the problem that the measured value of the component under test in the above test circuit has an error, the technical solution of the present invention provides a test circuit and a working method of the test circuit. The test structure charges and discharges the component under test through the first transmission gate and the second transmission gate to achieve complete voltage transfer, and thus can accurately control the voltage across the component under test.

[0048] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following combines the attached Figures 3 to 6 to make a detailed description of the specific embodiments of the present invention.

[0049] Figure 3 It is a schematic structure of a test circuit provided by an embodiment of the present invention Figure 1 .

[0050] Please refer to Figure 3The technical solution of the present invention provides a test circuit for measuring the nominal value of a component under test 5, comprising: a first transmission gate 1, comprising a first input terminal, a first output terminal, a first control terminal and a second control terminal, the first input terminal being coupled to a power supply voltage terminal VDD; a second transmission gate 2, comprising a second input terminal, a second output terminal, a third control terminal and a fourth control terminal, the second output terminal being connected to the first output terminal, and the second input terminal being grounded; a first inverter 3, the input terminal of the first inverter 3 being connected to the first control terminal, and the output terminal of the first inverter 3 being connected to the second control terminal; a second inverter 4, the input terminal of the second inverter 4 being connected to the fourth control terminal, and the output terminal of the second inverter 4 being connected to the third control terminal; and a component under test 5, the first terminal of the component under test 5 being connected to the first output terminal.

[0051] In this embodiment, the test circuit further includes: an ammeter 7, a first end of the ammeter 7 is connected to the power supply voltage terminal VDD, and a second end of the ammeter 7 is connected to the first input terminal.

[0052] In this embodiment, the first transmission gate 1 includes: a first PMOS tube MP1 and a first NMOS tube MN1, the gate of the first PMOS tube MP1 is the first control terminal, the gate of the first NMOS tube MN1 is the second control terminal, the source of the first PMOS tube MP1 is coupled to the drain of the first NMOS tube MN1 and serves as the first input terminal, and the drain of the first PMOS tube MP1 is coupled to the source of the first NMOS tube MN1 and serves as the first output terminal.

[0053] In a specific embodiment, the input voltage of the first input terminal includes a voltage value that is less than any voltage value within the second level range.

[0054] In this embodiment, the second transmission gate 2 includes: a second PMOS tube MP2 and a second NMOS tube MN2, the gate of the second PMOS tube MP2 is the third control terminal, the gate of the second NMOS tube MN2 is the fourth control terminal, the source of the second PMOS tube MP2 is coupled to the drain of the second NMOS tube MN2 and serves as the second output terminal, and the drain of the second PMOS tube MP2 is coupled to the source of the second NMOS tube MN2 and serves as the second input terminal.

[0055] Figure 4 A schematic diagram of a test circuit provided by an embodiment of the present invention is shown in FIG. Figure 2 .

[0056] Please refer to Figure 4 , the component under test 5 includes a capacitor C under test DUT .

[0057] In other embodiments, the DUT 5 also includes a resistor and an inductor, and the technical solution of the present invention is not limited thereto. Other types of DUT 5 are within the protection scope of the present invention.

[0058] Please continue to refer to Figure 3 The test circuit also includes: a test module coupled to the first control terminal, the third control terminal, the first input terminal and the second terminal of the element to be tested, the test module is used to apply a clock signal to the first control terminal and the third control terminal, apply a control signal to the second terminal of the element to be tested, and obtain a current result of the first input terminal, and obtain a nominal value of the element to be tested 5 based on the current result.

[0059] In this embodiment, the clock signal includes a first clock signal Vp and a second clock signal Vn, the control signal includes a first control signal Vapp1 and a second control signal Vapp2, and the current result includes a first current result I1 and a second current result I2; the test module is used to apply the first clock signal Vp to the first control end, and apply the second clock signal Vn to the third control end; apply the first control signal Vapp1 or the second control signal Vapp2 to the second end of the element under test 5, and after applying the first clock signal Vp, the second clock signal Vn and the first control signal Vapp1, obtain the first current result I1 of the first input end, after applying the second control signal Vapp2, obtain the second current result I2 of the first input end, and obtain the nominal value of the element under test 5 according to the first current result I1 and the second current result I2.

[0060] In this embodiment, there is also a parasitic element 6 in the test circuit. The first end of the parasitic element 6 is connected to the first output end and the second output end, and the second end of the parasitic element 6 is connected to the second input end. The type of the parasitic element 6 is consistent with the type of the component to be tested 5. For example, the component to be tested 5 is a capacitor C to be tested. DUT When the first parasitic element 6 is a parasitic capacitor C PAR .

[0061] Figure 5 The timing of a signal in a test circuit provided by an embodiment of the present invention is Figure 1 .

[0062] Figure 6 The timing of a signal in a test circuit provided by an embodiment of the present invention is Figure 2 .

[0063] Please refer to Figure 5 or Figure 6 In one cycle, the frequencies of the first clock signal Vp, the second clock signal Vn, the first control signal Vapp1 and the second control signal Vapp2 are the same, and one measurement cycle includes the first time node Q1, the second time node Q2, the third time node Q3, the fourth time node Q4 and the fifth time node Q5 in sequence.

[0064] In a specific embodiment, the first clock signal Vp and the second clock signal Vn are non-overlapping clock signals.

[0065] In this embodiment, the timing change process of the first clock signal Vp and the second clock signal Vn is specifically as follows: within a measurement cycle, after the first clock signal Vp is converted from the first level to the second level at the first time node Q1, it maintains the second level to the fourth time node Q4, and after the fourth time node Q4 is converted from the second level to the first level, it maintains the first level to the fifth time node Q5; within a measurement cycle, after the second clock signal Vn is converted from the first level to the second level at the second time node Q2, it maintains the second level to the third time node Q3, and after the third time node Q3 is converted from the second level to the first level, it maintains the first level to the fifth time node Q5.

[0066] In this embodiment, please continue to refer to Figure 5 The timing process of the control signal specifically includes: the first control signal Vapp1 maintains the second level from the first time node Q1 to the fifth time node Q5. In this embodiment, between the second time node Q2 and the third time node Q3, the first current result I1 of the first input terminal is obtained.

[0067] In this embodiment, please continue to refer to Figure 6 , the timing process of the control signal specifically also includes: the second control signal Vapp2 is converted from the second level to the first level between the first time node Q1 and the second time node Q2, and maintains the first level to the third time node Q3, and is converted from the first level to the second level between the third time node Q3 and the fourth time node Q4, and maintains the second level to the fifth time node Q5.

[0068] In this embodiment, the second current result I2 of the first input terminal is obtained between the second time node Q2 and the third time node Q3 or between the fourth time node Q4 and the fifth time node Q5.

[0069] The following example takes the voltage value of the first level as 0V and the voltage value of the second level as 1.05V as an example, and combines Figure 4 , Figure 5 and Figure 6 , the working process of the test circuit of this embodiment is specifically described.

[0070] Please refer to Figure 5 , between the second time node Q2 and the third time node Q3, a second level (i.e., 1.05V) is applied to the first control terminal and the input terminal of the first inverter 3, so that the first PMOS transistor MP1 and the first NMOS transistor MN1 are both in the cut-off state, a second level (i.e., 1.05V) is applied to the third control terminal and the input terminal of the second inverter 4, so that the second PMOS transistor MP2 and the second NMOS transistor MN2 are both in the on state, and a second level (i.e., 1.05V) is applied to the capacitor C to be tested.DUT At this time, the second output terminal will be parasitic capacitance C PAR The first end of the input is pulled down to the first level (ie 0V), and the second input end is the parasitic capacitor C PAR The second end of is pulled up to the second level (i.e. 1.05V), so that the parasitic capacitor C PAR The voltages at both ends are opposite and in a charging state; the second output end connects the capacitor C to be tested. DUT The first end of the capacitor C is pulled down to the first level (ie, 0V), so that the capacitor C DUT The voltages at both ends are opposite and in a charging state; therefore, at this time, the first current result I1 of the first input terminal measured by the ammeter 7 is the capacitance C to be measured. DUT The charging current and parasitic capacitance C PAR The sum of the charging currents.

[0071] Please refer to Figure 6 , between the second time node Q2 and the third time node Q3, the second level (i.e., 1.05V) is applied to the first control terminal and the input terminal of the first inverter 3, so that the first PMOS transistor MP1 and the first NMOS transistor MN1 are both in the cut-off state, the second level (i.e., 1.05V) is applied to the third control terminal and the input terminal of the second inverter 4, so that the second PMOS transistor MP2 and the second NMOS transistor MN2 are both in the on state, and the first level (i.e., 0V) is applied to the capacitor C to be measured. DUT At this time, the second output terminal will be parasitic capacitance C PAR The first end of the input is pulled down to the first level (ie 0V), and the second input end is the parasitic capacitor C PAR The second end of is pulled up to the second level (i.e. 1.05V), so that the parasitic capacitor C PAR The voltages at both ends are opposite and in a charging state; the second output end connects the capacitor C to be tested. DUT The first end of the capacitor C is pulled down to the first level (ie, 0V), so that the capacitor C DUT The voltage at both ends is the same, and the capacitor C to be measured DUT Therefore, at this time, the second current result I2 of the first input terminal measured by the ammeter 7 is the parasitic capacitance C PAR of charging current.

[0072] Please continue to refer to Figure 6 , between the fourth time node Q4 and the fifth time node Q5, a first level (i.e., 0V) is applied to the first control terminal and the input terminal of the first inverter 3, so that the first PMOS transistor MP1 and the first NMOS transistor MN1 are both in the on state, a first level (i.e., 0V) is applied to the third control terminal and the input terminal of the second inverter 4, so that the second PMOS transistor MP2 and the second NMOS transistor MN2 are both in the off state, and a second level (i.e., 1.05V) is applied to the capacitor C to be measured. DUTAt this time, the first output terminal will be parasitic capacitor C PAR The first end of is pulled up to the second level (i.e. 1.05V), and the parasitic capacitor C PAR The second end of is grounded, that is, at the first level (ie, 0V), so that the parasitic capacitance C PAR The voltages at both ends are opposite and in a charging state; the first output end connects the capacitor C to be tested. DUT The first end of the capacitor C is pulled up to the second level (i.e., 1.05V), so that the capacitor C DUT The voltage at both ends is the same, and the capacitor C to be measured DUT Therefore, at this time, the second current result I2 of the first input terminal measured by the ammeter 7 is the parasitic capacitance C PAR of charging current.

[0073] In this embodiment, the capacitance C to be measured is obtained according to the first current result I1 and the second current result I2. DUT Capacitance value Among them, V DD is the power supply voltage and f is the frequency.

[0074] In this embodiment, between the first time node Q1 and the fourth time node Q4, the second level duration of the first clock signal Vp is greater than the second level duration of the second clock signal Vn, so that when the first transmission gate 1 is completely turned off, the second transmission gate 2 is controlled to be turned on.

[0075] In this embodiment, between the third time node Q3 and the fifth time node Q5, the first level duration of the second clock signal Vn is greater than the first level duration of the first clock signal Vp, so that when the second transmission gate 2 is completely turned off, the first transmission gate 1 is controlled to be turned on.

[0076] Please refer to Figure 3 The technical solution of the present invention also provides a working method of a test circuit, including: applying a clock signal to a first control terminal and a third control terminal, applying a control signal to the second terminal of the component under test 5, and obtaining a current result of the first input terminal, and obtaining a nominal value of the component under test 5 based on the current result.

[0077] Please refer to Figure 5 or Figure 6, the clock signal includes a first clock signal Vp and a second clock signal Vn, the control signal includes a first control signal Vapp1 and a second control signal Vapp2, and the current result includes a first current result I1 and a second current result I2; applying the clock signal to the first control terminal and the third control terminal, applying the control signal to the second terminal of the element under test 5, and obtaining the current result of the first input terminal, and obtaining the nominal value of the element under test 5 based on the current result, including: applying the first clock signal Vp to the first control terminal, applying the second clock signal Vn to the third control terminal, and applying the first control signal Vapp1 to the second terminal of the element under test 5, obtaining the first current result I1 of the first input terminal; applying the first clock signal Vp to the first control terminal, applying the second clock signal Vn to the third control terminal, and applying the second control signal Vapp2 to the second terminal of the element under test 5, obtaining the second current result I2 of the first input terminal; obtaining the nominal value of the element under test 5 according to the first current result I1 and the second current result I2.

[0078] In this embodiment, the frequencies of the first clock signal Vp, the second clock signal Vn, the first control signal Vapp1 and the second control signal Vapp2 are the same, and one measurement cycle includes a first time node Q1, a second time node Q2, a third time node Q3, a fourth time node Q4 and a fifth time node Q5 in sequence; within one measurement cycle, after the first clock signal Vp is converted from the first level to the second level at the first time node Q1, it maintains the second level to the fourth time node Q4, and after the fourth time node Q4 is converted from the second level to the first level, it maintains the first level to the fifth time node Q5; within one measurement cycle, after the second clock signal Vn is converted from the first level to the second level at the second time node Q2, it maintains the second level to the third time node Q3, and after the third time node Q3 is converted from the second level to the first level, it maintains the first level to the fifth time node Q5.

[0079] In this embodiment, the first control signal Vapp1 maintains the second level from the first time node Q1 to the fifth time node Q5.

[0080] In this embodiment, obtaining the first current result I1 of the first input terminal includes: obtaining the first current result I1 of the first input terminal between the second time node Q2 and the third time node Q3.

[0081] In this embodiment, the second control signal Vapp2 is converted from the second level to the first level between the first time node Q1 and the second time node Q2, and maintains the first level to the third time node Q3, and is converted from the first level to the second level between the third time node Q3 and the fourth time node Q4, and maintains the second level to the fifth time node Q5.

[0082] In this embodiment, obtaining the second current result I2 of the first input terminal includes: obtaining the second current result I2 of the first input terminal between the second time node Q2 and the third time node Q3 or between the fourth time node Q4 and the fifth time node Q5.

[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A test circuit for measuring the nominal value of a component under test, characterized in that: include: A first transmission gate, comprising a first input terminal, a first output terminal, a first control terminal and a second control terminal, wherein the first input terminal is coupled to a power supply voltage terminal; A second transmission gate comprises a second input terminal, a second output terminal, a third control terminal and a fourth control terminal, wherein the second output terminal is connected to the first output terminal, and the second input terminal is grounded; A first inverter, wherein an input end of the first inverter is connected to the first control end, and an output end of the first inverter is connected to the second control end; A second inverter, wherein an input terminal of the second inverter is connected to the fourth control terminal, and an output terminal of the second inverter is connected to the third control terminal; A device under test, wherein a first end of the device under test is connected to the first output end.

2. The test circuit according to claim 1, characterized in that: Also includes: An ammeter, a first end of the ammeter is connected to the power supply voltage end, and a second end of the ammeter is connected to the first input end.

3. The test circuit according to claim 1, characterized in that: The first transmission gate includes: a first PMOS tube and a first NMOS tube, the gate of the first PMOS tube is the first control end, the gate of the first NMOS tube is the second control end, the source of the first PMOS tube is coupled to the drain of the first NMOS tube and serves as the first input end, and the drain of the first PMOS tube is coupled to the source of the first NMOS tube and serves as the first output end.

4. The test circuit according to claim 1, characterized in that: The second transmission gate includes: a second PMOS tube and a second NMOS tube, the gate of the second PMOS tube is the third control terminal, the gate of the second NMOS tube is the fourth control terminal, the source of the second PMOS tube is coupled to the drain of the second NMOS tube and serves as the second output terminal, and the drain of the second PMOS tube is coupled to the source of the second NMOS tube and serves as the second input terminal.

5. The test circuit according to claim 1, characterized in that: The component to be tested includes a capacitor to be tested.

6. The test circuit according to claim 1, characterized in that: Also includes: A test module coupled to the first control terminal, the third control terminal, the first input terminal and the second terminal of the component under test, the test module is used to apply a clock signal to the first control terminal and the third control terminal, apply a control signal to the second terminal of the component under test, and obtain a current result of the first input terminal, and obtain a nominal value of the component under test based on the current result.

7. The test circuit according to claim 6, characterized in that: The clock signal includes a first clock signal and a second clock signal, the control signal includes a first control signal and a second control signal, and the current result includes a first current result and a second current result; The test module is used to apply a first clock signal to the first control terminal, and apply a second clock signal to the third control terminal; Apply a first control signal or a second control signal to the second end of the element under test, and obtain a first current result of the first input end after applying a first clock signal, a second clock signal and a first control signal, and obtain a second current result of the first input end after applying a second control signal, and obtain a nominal value of the element under test based on the first current result and the second current result.

8. The test circuit according to claim 7, characterized in that: The first clock signal, the second clock signal, the first control signal, and the second control signal have the same frequency, and a measurement cycle includes a first time node, a second time node, a third time node, a fourth time node, and a fifth time node in sequence; In one measurement cycle, after the first clock signal is converted from the first level to the second level at the first time node, it maintains the second level to a fourth time node, and after the first clock signal is converted from the second level to the first level at the fourth time node, it maintains the first level to a fifth time node; In a measurement cycle, after the second clock signal is converted from the first level to the second level at the second time node, it maintains the second level to a third time node, and after it is converted from the second level to the first level at the third time node, it maintains the first level to a fifth time node.

9. The test circuit according to claim 8, characterized in that: The first control signal maintains a second level from the first time node to the fifth time node.

10. The test circuit according to claim 9, characterized in that: The measurement module obtains a first current result of the first input terminal between the second time node and the third time node.

11. The test circuit according to claim 8, characterized in that: The second control signal is converted from the second level to the first level between the first time node and the second time node, and maintains the first level to the third time node, and is converted from the first level to the second level between the third time node and the fourth time node, and maintains the second level to the fifth time node.

12. The test circuit according to claim 11, characterized in that: The measurement module obtains a second current result of the first input terminal between the second time node and the third time node or between the fourth time node and the fifth time node.

13. A working method of the test circuit according to any one of claims 1 to 5, characterized in that: include: A clock signal is applied to the first control terminal and the third control terminal, a control signal is applied to the second terminal of the DUT, and a current result of the first input terminal is obtained, and a nominal value of the DUT is obtained based on the current result.

14. The working method of the test circuit as claimed in claim 13, characterized in that: The clock signal includes a first clock signal and a second clock signal, the control signal includes a first control signal and a second control signal, and the current result includes a first current result and a second current result; The step of applying a clock signal to the first control terminal and the third control terminal, applying a control signal to the second terminal of the device under test, obtaining a current result of the first input terminal, and obtaining a nominal value of the device under test based on the current result comprises: Applying a first clock signal to the first control terminal, applying a second clock signal to the third control terminal, and applying a first control signal to the second terminal of the device under test to obtain a first current result of the first input terminal; Applying a first clock signal to the first control terminal, applying a second clock signal to the third control terminal, and applying a second control signal to the second terminal of the device under test to obtain a second current result of the first input terminal; The nominal value of the device under test is obtained according to the first current result and the second current result.

15. The working method of the test circuit as claimed in claim 14, characterized in that: The first clock signal, the second clock signal, the first control signal, and the second control signal have the same frequency, and a measurement cycle includes a first time node, a second time node, a third time node, a fourth time node, and a fifth time node in sequence; In one measurement cycle, after the first clock signal is converted from the first level to the second level at the first time node, it maintains the second level to a fourth time node, and after it is converted from the second level to the first level at the fourth time node, it maintains the first level to a fifth time node; In a measurement cycle, after the second clock signal is converted from the first level to the second level at the second time node, it maintains the second level to a third time node, and after it is converted from the second level to the first level at the third time node, it maintains the first level to a fifth time node.

16. The working method of the test circuit as claimed in claim 15, characterized in that: The first control signal maintains a second level from the first time node to the fifth time node.

17. The working method of the test circuit as claimed in claim 16, characterized in that: The obtaining of the first current result of the first input terminal includes: obtaining the first current result of the first input terminal between the second time node and the third time node.

18. The working method of the test circuit as claimed in claim 15, characterized in that: The second control signal is converted from the second level to the first level between the first time node and the second time node, and maintains the first level to the third time node, and is converted from the first level to the second level between the third time node and the fourth time node, and maintains the second level to the fifth time node.

19. The working method of the test circuit as claimed in claim 18, characterized in that: The obtaining of the second current result of the first input terminal includes: obtaining the second current result of the first input terminal between the second time node and the third time node or between the fourth time node and the fifth time node.

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