Semiconductor processing method, electronic equipment and computer readable storage medium

Abstract

The invention belongs to the technical field of semiconductors, and discloses a semiconductor processing method, electronic equipment and a computer readable storage medium, according to the scheme, after photoetching of a front layer of a wafer is completed, warping information of the wafer is obtained, and the position offset of a target overlay alignment mark is calculated based on the warping information of the wafer; the position information of the target overlay alignment mark is accurately positioned. In the subsequent process, the position offset can be utilized, and particularly, the alignment mark position of the current layer of the wafer can be compensated based on the position offset when the current layer of the wafer is subjected to photoetching treatment, so that the alignment error is reduced. In addition, an original photoetching process flow does not need to be changed, and materials are not increased or changed.

Description

[0001] This application is a divisional application of the application number 2023116270419 filed on November 29, 2023, and the invention name is "Method for detecting the position offset of the overlay alignment mark and the semiconductor processing method". Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a method, device, electronic device, storage medium and semiconductor processing method for detecting a position offset of an overlay alignment mark. Background Art

[0003] In semiconductor R&D and mass production, OVL (Overlay) has always been regulated as an important indicator in lithography work.

[0004] OVL refers to the position offset between two adjacent layers of patterns on a wafer. Wafers are manufactured by stacking multiple circuit layers. Overlay alignment marks are set on the layers of the wafer. The photolithography process exposes the wafer by looking for the overlay alignment marks, thereby aligning the two adjacent layers of patterns on the wafer. However, in the entire wafer process, the degree of wafer warping is inconsistent at each stage, which causes the position of the overlay alignment mark on the wafer to change with the warping of the wafer. Since the exposure machine cannot accurately identify the actual overlay alignment mark information of the wafer in real time, the accuracy of exposure is affected, and ultimately the OVL deteriorates. Summary of the invention

[0005] In order to solve the above problems, the present application provides a method, device, electronic device, storage medium and semiconductor processing method for detecting the position offset of an overlay alignment mark.

[0006] According to one aspect of an embodiment of the present application, a method for detecting a position offset of an overlay alignment mark is disclosed. The method for detecting a position offset of an overlay alignment mark comprises:

[0007] After the front layer of the wafer is photolithographically processed, the warpage information of the wafer is obtained;

[0008] Based on the warpage information of the wafer, calculating the position offset of a target overlay alignment mark, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer or an overlay alignment mark expected to be formed on the current layer of the wafer;

[0009] The position offset is output.

[0010] In some embodiments, the calculating the position offset of the target overlay alignment mark based on the warpage information of the wafer includes:

[0011] Obtaining the baseline position of the target overlay alignment mark;

[0012] Based on the warpage information of the wafer and the baseline position of the target overlay alignment mark, a position offset of the target overlay alignment mark is calculated.

[0013] In some embodiments, the warpage information of the wafer includes a critical position between a warpage position and a non-warpage position of the wafer and a plurality of sampling point positions, wherein the plurality of sampling points are distributed along a radial spacing of the wafer and are located between the critical position and an edge position of the wafer;

[0014] The calculating the position offset of the target overlay alignment mark based on the warpage information of the wafer and the baseline position of the target overlay alignment mark comprises:

[0015] Performing curve fitting based on the critical position and the positions of the multiple sampling points to obtain a corresponding curve function;

[0016] Constructing an arc length expression based on the curve function;

[0017] Based on the distance between the critical position and the baseline position of the target overlay alignment mark and the arc length expression, the position offset of the target overlay alignment mark is obtained, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer.

[0018] In some embodiments, constructing an arc length expression based on the curve function includes:

[0019] Taking the distance between the critical position and the center position of the wafer as the lower limit of integration, taking the actual distance between the target overlay alignment mark and the center position of the wafer after warping occurs as the upper limit of integration, constructing an arc length integral formula based on the curve function;

[0020] The step of obtaining the position offset of the target overlay alignment mark based on the distance between the critical position and the baseline position of the target overlay alignment mark and the arc length expression comprises:

[0021] Setting the distance between the critical position and the baseline position of the target overlay alignment mark as an arc length integral value;

[0022] Based on the arc length integral value and the arc length integral formula, a position offset of the target overlay alignment mark is obtained.

[0023] In some embodiments, obtaining the position offset of the target overlay alignment mark based on the arc length integral value and the arc length integral formula includes:

[0024] Based on the arc length integral value and the arc length integral formula, obtaining an actual distance between the target overlay alignment mark and the center position of the wafer under the warpage information;

[0025] Substituting the actual distance into the curve function to obtain the actual position of the target overlay alignment mark under the warping information;

[0026] A displacement vector is obtained based on the actual position and the baseline position as a position offset of the target overlay alignment mark.

[0027] In some embodiments, the number of the plurality of sampling points is at least three, and the distances between adjacent sampling points in the plurality of sampling points are equal.

[0028] In some embodiments, the calculating the position offset of the target overlay alignment mark based on the warpage information of the wafer and the baseline position of the target overlay alignment mark comprises:

[0029] Based on the baseline position and the deformation angle of the wafer, the position offset of the target overlay alignment mark is obtained; wherein the target overlay alignment mark is an overlay alignment mark expected to be formed on the current layer of the wafer.

[0030] In some embodiments, the warpage information of the wafer includes a deformation height of the wafer; and obtaining a position offset of the target overlay alignment mark based on the baseline position and the deformation angle of the wafer includes:

[0031] Acquire a horizontal distance between the baseline position and the center position of the wafer;

[0032] Based on the baseline position, the deformation height and the horizontal distance, a position offset of the target overlay alignment mark is obtained.

[0033] In some embodiments, obtaining the position offset of the target overlay alignment mark based on the baseline position, the deformation height, and the horizontal distance includes:

[0034] Based on relational Obtaining a position offset of the target overlay alignment mark in a first direction in the horizontal direction, wherein X represents the position offset in the first direction, Tx represents the position coordinate in the first direction, h represents the deformation height, and R represents the horizontal distance;

[0035] Based on relational The position offset of the target overlay alignment mark in the second direction in the horizontal direction is obtained, wherein Y represents the position offset in the second direction, Ty represents the position coordinate in the second direction, h represents the deformation height, and R represents the horizontal distance.

[0036] According to one aspect of an embodiment of the present application, a position offset detection device for an overlay alignment mark is disclosed, which includes a warpage acquisition module, an offset calculation module and an offset output module, wherein the warpage acquisition module is used to acquire the warpage information of the wafer after the front layer lithography of the wafer is completed; the offset calculation module is used to calculate the position offset of the target overlay alignment mark based on the warpage information of the wafer, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer or an overlay alignment mark expected to be formed on the current layer of the wafer; and the offset output module is used to output the position offset.

[0037] According to one aspect of an embodiment of the present application, an electronic device is disclosed, which includes one or more processors and a memory, wherein the memory is used to store one or more computer programs, and when the one or more computer programs are executed by the one or more processors, the processor implements the position offset detection method of the overlay alignment mark as described above.

[0038] According to one aspect of an embodiment of the present application, a computer-readable storage medium is disclosed, which stores computer-readable instructions. When the computer-readable instructions are executed by a processor of a computer, the computer executes the position offset detection method of the overlay alignment mark as described above.

[0039] The technical solution provided by the embodiments of the present application includes at least the following beneficial effects:

[0040] The solution disclosed in the present application obtains the warpage information of the wafer after the photolithography of the front layer of the wafer is completed, and calculates the position offset of the target overlay alignment mark based on the warpage information of the wafer, thereby realizing the accurate positioning of the position information of the target overlay alignment mark. The position offset can be used in subsequent processes, specifically, when the photolithography of the wafer layer is performed, the overlay alignment mark position of the wafer layer is compensated based on the position offset, thereby reducing the overlay error. In addition, the present application does not need to change the original photolithography process flow, and there is no increase or change in materials.

[0041] According to one aspect of an embodiment of the present application, a semiconductor processing method is disclosed, and the semiconductor processing method includes:

[0042] Photolithography of the front layer of the wafer;

[0043] Execute the aforementioned method for detecting the position offset of the overlay alignment mark;

[0044] Based on the position offset output by the position offset detection method, photolithography is performed on the current layer of the wafer.

[0045] In some embodiments, when executing the position offset detection method, obtaining the warpage information of the wafer includes:

[0046] Acquire warpage information of a plurality of position points in the wafer, wherein the plurality of position points are distributed at circumferential and / or radial intervals on the wafer, and each of the position points is associated with a target overlay alignment mark;

[0047] When executing the position offset detection method, the baseline position of the target overlay alignment mark associated with the multiple position points is obtained; and based on the warping information of each of the position points and the baseline position of the target overlay alignment mark associated with the position point, the position offset of the target overlay alignment mark associated with the position point is obtained.

[0048] The scheme disclosed in the present application obtains the warpage information of the wafer after the photolithography of the front layer of the wafer is completed and before the photolithography of the current layer of the wafer is performed, and calculates the position offset of the target overlay alignment mark based on the warpage information of the wafer, and then performs photolithography on the current layer of the wafer based on the position offset. Specifically, the position of the overlay alignment mark of the current layer of the wafer can be compensated based on the position offset, which can compensate for the position offset of the overlay alignment mark caused by the warpage of the wafer, so that the overlay alignment mark of the current layer of the wafer is accurately aligned with the overlay alignment mark of the front layer of the wafer, thereby reducing the overlay error.

[0049] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the description, are used to explain the principles of the present application.

[0051] Figure 1 shows the alignment of the overlay alignment marks and the OVL distribution diagram under ideal conditions;

[0052] Figure 2 A schematic diagram showing the warpage of a wafer at different stages of the wafer manufacturing process is shown;

[0053] Figure 3 shows the alignment of the overlay alignment mark and the OVL distribution diagram in the case of warpage;

[0054] Figure 4A flow chart showing a method for detecting a position offset of an overlay alignment mark according to an embodiment of the present application is shown;

[0055] Figure 5 A flow chart showing the steps of calculating the position offset in the first embodiment of the present application is shown;

[0056] Figure 6 A schematic diagram showing the steps of calculating the position offset in the first embodiment of the present application is shown;

[0057] Figure 7 A flow chart showing the steps of calculating the position offset in the second embodiment of the present application is shown;

[0058] Figure 8 The schematic diagram of the position offset calculation step of the second embodiment of the present application is shown;

[0059] Fig. 9 A block diagram showing the composition of a device for detecting the position offset of an overlay alignment mark according to an embodiment of the present application is shown;

[0060] Fig.10 A block diagram showing the composition of an electronic device according to an embodiment of the present application is shown;

[0061] Fig.11 A block diagram of a computer system structure for implementing some embodiments of the present application is shown;

[0062] Fig.12 A flow chart showing a semiconductor processing method according to an embodiment of the present application is shown;

[0063] Fig.13 A process schematic diagram of a semiconductor processing method according to an embodiment of the present application is shown.

[0064] The following are the descriptions of the reference numerals:

[0065] 101. Wafer; 1011. Sector-shaped area; 102. Front layer overlay alignment mark; 103. Current layer overlay alignment mark; 104. Target overlay alignment mark; 900. Overlay alignment mark position offset detection device; 901. Warp acquisition module; 902. Offset calculation module; 903. Offset output module; 1000. Electronic device; 1001. Processor; 1002. Memory; 1100. Computer system; 1101. CPU; 1102. ROM; 1103. RAM; 1104. Bus; 1105. I / O interface; 1106. Input part; 1107. Output part; 1108. Storage part; 1109. Communication part; 1110. Drive; 1111. Removable medium. DETAILED DESCRIPTION

[0066] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of this application will be more comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art.

[0067] In the description of the present application, it should be understood that the terms "center", "front", "rear", "left", "right", "vertical", "horizontal", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0068] In addition, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0069] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0070] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0071] The wafer is manufactured by stacking multiple circuit layers. Overlay alignment marks are set on the layers of the wafer. The photolithography process exposes the wafer by looking for the overlay alignment marks, so that the patterns of two adjacent layers are aligned. Usually, when the wafer 101 has no warpage or very little warpage, when the photolithography equipment performs photolithography on the wafer layer according to the set reference position, each overlay alignment mark 103 of the wafer layer corresponds to each overlay alignment mark 102 of the front layer of the wafer, such as Figure 1In this case, the OVL distribution diagram of each location on the wafer is as follows: Figure 1 As shown in (b), the length of the arrow indicates the size of OVL. Figure 1 As can be seen in (b), the OVL sizes at various locations on the wafer are almost equal, and the OVL is small.

[0072] However, in the actual wafer manufacturing process, the warpage degree of the wafer at each stage is inconsistent due to the influence of the film stack and pattern. Figure 2 As shown, the warpage (Degree) of the wafer changes continuously from FEOL (Front-end-of-line) to MOL (Middle-of-line) and finally to BEOL (Back-end-of-line).

[0073] The position of the front layer overlay alignment mark 102 of the front layer of the wafer changes with the warpage of the wafer 101. If the warpage of the wafer 101 is not considered when the photolithography process is performed on the current layer of the wafer, it may cause the current layer overlay alignment mark 103 of the current layer of the wafer to be misaligned with the front layer overlay alignment mark 102 of the front layer of the wafer. Figure 3 In this case, the OVL distribution diagram of each location on the wafer is as follows: Figure 3 As shown in (b), the length of the arrow indicates the size of OVL. Figure 3 As shown in (b), along the radial direction of the wafer, the OVL of each position on the wafer gradually increases, that is, the OVL gradually deteriorates. This is because the warpage near the edge of the wafer is more serious than the warpage near the center of the wafer. Figure 3 In (b), a more intuitive OVL distribution diagram is shown in Figure 3 As shown in (c).

[0074] When OVL is large, it will affect the lithography process window margin, resulting in WAT (Wafer Acceptance Test) parameter drift, such as resistance drift, voltage, current drift, etc.; when OVL is even larger, the chip made from the wafer may not work properly, resulting in yield loss, and yield loss will lead to increased costs. In addition, with the further improvement of semiconductor product requirements for miniaturization, functional integration, and large-capacity storage space, graphic miniaturization promotes the increase of structural units in the effective area, resulting in a serious reduction in the OVL process window of the key layer. For this reason, it is necessary to control the overlay error to a smaller value.

[0075] However, in the prior art, only the overlay error is generally measured. When the overlay error is too large, the wafer process is terminated or the manufactured wafer is scrapped, and the overlay error cannot be accurately controlled to a smaller value in the wafer process according to the OVL process window. To this end, the present application provides a method for accurately locating the position information of the overlay alignment mark without changing the original lithography process flow and without adding or changing materials, so as to further provide the lithography equipment with accurate position information of the overlay alignment mark, and finally realize a method for detecting the position offset of the overlay alignment mark to reduce the overlay error.

[0076] The method for detecting the position offset of the overlay alignment mark provided in the present application is described in detail below in conjunction with specific implementations.

[0077] Figure 4 A flow chart showing a method for detecting the position offset of an overlay alignment mark according to an embodiment of the present application is shown. Figure 4 As shown, the position offset detection method of the overlay alignment mark at least includes a warpage information acquisition step, a position offset calculation step, and a position offset output step, which correspond to the following steps S110 to S130, respectively, and are described in detail as follows:

[0078] In step S110, after the front layer of the wafer is photolithographically processed, the warpage information of the wafer is obtained.

[0079] The warpage information of the wafer may be data directly representing the warpage of the wafer, such as the deformation angle information of the wafer, the deformation height information of the wafer, etc. The deformation angle refers to the angle between the perpendicular line of the tangent line of the position corresponding to the target overlay alignment mark and the normal line of the wafer flat surface, such as Figure 8 The angle θ shown is, where L1 represents the tangent line at the position corresponding to the target overlay alignment mark, F1 represents the vertical line of the tangent line L1, and F2 represents the normal line of the wafer flat surface; the angle θ is also equal to the angle between the tangent line at the position corresponding to the target overlay alignment mark and the horizontal straight line in the wafer flat surface, and L2 represents the horizontal straight line. The deformation height refers to the warping height of the wafer at the position corresponding to the target overlay alignment mark, such as Figure 8 h shown.

[0080] The warpage information of the wafer may also be data that indirectly characterizes the warpage of the wafer, for example, the critical position between the warpage position and the non-warpage position of the wafer, such as Figure 6 The Q0 point shown in (a) is, for example, a point located between the critical position and the edge position of the wafer. Figure 6 From point Q1 to Q n point.

[0081] In step S120 , based on the warpage information of the wafer, the position offset of the target overlay alignment mark is calculated.

[0082] The target overlay alignment mark may be an overlay alignment mark formed on the front layer of the wafer, or may be an overlay alignment mark expected to be formed on the current layer of the wafer.

[0083] In one embodiment, in step S120, the position offset of the target overlay alignment mark is calculated in combination with the baseline position of the target overlay alignment mark. It can be understood that the baseline position is the position information based on which the lithography equipment performs the lithography process. In the conventional technology, the position offset of the target overlay alignment mark is not considered, and the lithography equipment directly performs the lithography process based on the baseline position when performing the lithography process.

[0084] In detail, step S120 includes: first, obtaining the baseline position of the target overlay alignment mark; and then calculating the position offset of the target overlay alignment mark based on the warpage information of the wafer and the baseline position of the target overlay alignment mark.

[0085] It should be noted that the warpage information of the wafer may be the warpage information corresponding to the position point associated with the target overlay alignment mark, or may include the warpage information corresponding to the position point associated with the target overlay alignment mark and the warpage information corresponding to other position points on the wafer. In step S120, the position offset of the target overlay alignment mark is calculated based on the warpage information corresponding to the position point associated with the target overlay alignment mark and the baseline position of the target overlay alignment mark.

[0086] In one embodiment, the warpage information of the wafer includes a critical position between the warpage position and the non-warpage position of the wafer and a plurality of sampling point positions, wherein the plurality of sampling points are distributed along the radial spacing of the wafer and are located between the critical position and the edge position of the wafer. Figure 5 As shown, in this embodiment, step S120 includes the following steps S210 to S230, which are described in detail as follows:

[0087] In step S210, curve fitting is performed based on the critical position and the positions of multiple sampling points to obtain a corresponding curve function.

[0088] The plurality of sampling points may be at least two sampling points, in which case the curve fitting is performed through the two sampling points and the critical position, a total of three position points. In order to improve the accuracy of the curve fitting result, more sampling points may be selected, such as six sampling points, eight sampling points, ten sampling points or more, while taking into account the amount of data calculation and the efficiency of curve fitting.

[0089] In order to improve the accuracy of the fitting result, the multiple sampling points are evenly distributed along the radial direction of the wafer. In this embodiment, the number of the multiple sampling points is more than three, for example, ten, and the distances between adjacent sampling points in the multiple sampling points are equal.

[0090] In detail, curve fitting is performed based on critical positions and multiple sampling point positions. The least squares method can be used to fit the curve by minimizing the sum of squares of errors from data points to the fitting curve. The spline interpolation method can also be used to fit the curve by establishing a smooth curve between data points. The polynomial regression method can also be used for curve fitting, which will not be described in detail here.

[0091] In one embodiment, if Figure 6 As shown in (a), multiple sampling points are from Q1 to Q n Points, where n is greater than 2, the coordinates corresponding to the critical position Q0 point are (r, a, z), based on the critical position Q0 point, multiple sampling points Q1 point to Q n The curve function obtained by fitting the point position is z(x).

[0092] In step S220, an arc length expression is constructed based on the curve function.

[0093] In one embodiment, step S220 is specifically as follows: taking the distance between the critical position and the center position of the wafer as the lower limit of integration, taking the actual distance between the target overlay alignment mark and the center position of the wafer after warping occurs as the upper limit of integration, and constructing an arc length integral formula based on the curve function. The constructed arc length integral formula is as follows:

[0094]

[0095] Among them, r represents the lower limit of integration, that is, the distance between the critical position and the center position O of the wafer, R′ represents the upper limit of integration, that is, the actual distance between the target overlay alignment mark and the center position O of the wafer after warping occurs, and z′ 2 (r) represents the quadratic derivative of z(r), that is, the curve function z(x) obtained in step S210 is derived and the quadratic power is calculated, which is z′ 2 (r), dr represents the differential of r, As the integrand, s′ represents the integral value of the arc length, that is, the length of the curve from the position Q0 (r, a, z) corresponding to r to the position P′ (R′, a, z′) corresponding to R′.

[0096] In step S230, the position offset of the target overlay alignment mark is obtained based on the distance between the critical position and the baseline position of the target overlay alignment mark and the arc length expression.

[0097] The target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer.

[0098] In one embodiment, step S230 includes: setting the distance between the critical position and the baseline position of the target overlay alignment mark as an arc length integral value; and obtaining the position offset of the target overlay alignment mark based on the arc length integral value and the arc length integral formula.

[0099] As described above, the baseline position of the target overlay alignment mark is the position information based on which the lithography equipment performs lithography processing. In the absence of wafer warpage, the baseline position is the actual position of the target overlay alignment mark. Figure 6 Point P (R, a, z) shown in (a).

[0100] Before and after the wafer warps, the distance from the same position to the critical position is equal, that is, the distance from the critical position Q0 point (r, a, z) to the baseline position P point (R, a, z) is equal to the distance from the critical position Q0 point (r, a, z) to the actual position P' point (R′, a, z′). Therefore, the distance s from the critical position Q0 point (r, a, z) to the baseline position P point (R, a, z) is equal to s′ in the arc length integral formula, that is, the expression s′=s=Rr is satisfied. R′ can be obtained by combining this expression with the arc length integral formula.

[0101] In this embodiment, by constructing an arc length integral formula and based on the fact that the arc length remains unchanged before and after warping, the distance between the actual position of the target overlay alignment mark after warping and the center position of the wafer can be obtained, thereby further obtaining the actual position of the target overlay alignment mark after warping. The data calculation is simple and efficient.

[0102] In one embodiment, based on the arc length integral value and the arc length integral formula, the actual distance between the target overlay alignment mark and the center position O of the wafer under the warpage information is obtained; the actual distance is substituted into the curve function to obtain the actual position P' (R', a, z') of the target overlay alignment mark under the warpage information; the displacement vector is obtained based on the actual position and the baseline position The position offset used as the target overlay alignment mark.

[0103] In this way, the three-dimensional position offset can be obtained, and the position information of the target overlay alignment mark in the three-dimensional space can be accurately located. The data can be processed later to convert the position offset Dimension reduction is performed to decompose it into horizontal and vertical offsets. The horizontal offset is compensated by the photolithography equipment when the wafer layer is photolithographically processed. During exposure, the focusing system of the photolithography equipment should focus on the exposed area on the wafer surface. After obtaining the vertical offset, the focusing position of the light matrix of the photolithography equipment can be adjusted through the lens to solve the defocusing problem caused by deformation in the z direction.

[0104] It should be noted that, in the above embodiment, the coordinates (r, a, z) corresponding to the point Q0, the coordinates (R, a, z) corresponding to the point P, and the coordinates (R′, a, z′) corresponding to the point P′ represent the angle of the sector area corresponding to the arc length S, such as Figure 6 As shown in (b), the wafer 101 has 360 degrees, and a sector area 1011 corresponding to 0° to 5° is intercepted to find the position offset of the target overlay alignment mark 104, and a is 5°. The z represents the coordinate in the vertical direction.

[0105] In one embodiment, the position offset of the target overlay alignment mark is obtained based on the baseline position of the target overlay alignment mark and the deformation angle of the wafer, wherein the target overlay alignment mark is an overlay alignment mark that is expected to be formed on the current layer of the wafer.

[0106] By predicting the baseline position of the overlay alignment mark formed on the current layer of the wafer and combining the deformation angle of the wafer, the position offset of the baseline position of the target overlay alignment mark relative to the correct position under the warping information is obtained. The calculation method of the position offset is simple and easy to implement.

[0107] In one embodiment, the deformation angle is characterized by the deformation height and the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer. It is not necessary to detect the deformation angle, and it is easier to obtain the deformation height and the horizontal distance, which can simplify the calculation process of the position offset. Figure 7 As shown, in this embodiment, step S120 includes the following steps S310 to S320, which are described in detail as follows:

[0108] In step S310, a horizontal distance between a baseline position of a target overlay alignment mark and a center position of a wafer is obtained.

[0109] As shown in FIG8 , the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer, that is, the distance R between the position coordinate Tx of the baseline position of the target overlay alignment mark in the first direction and the position coordinate Tox of the center position O of the wafer in the first direction. The first direction is also the x-axis direction.

[0110] In step S320, the position offset of the target overlay alignment mark is obtained based on the baseline position, deformation height and horizontal distance of the target overlay alignment mark.

[0111] In one embodiment, based on the relation The position offset of the target overlay alignment mark in the first direction in the horizontal direction is obtained. Wherein, X represents the position offset of the target overlay alignment mark in the first direction in the horizontal direction, Tx represents the position coordinate of the baseline position of the target overlay alignment mark in the first direction, h represents the deformation height, and R represents the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer.

[0112] Based on relational Obtain the position offset of the target overlay alignment mark in the second direction in the horizontal direction. Wherein, Y represents the position offset of the target overlay alignment mark in the second direction in the horizontal direction, Ty represents the position coordinate of the baseline position of the target overlay alignment mark in the second direction, h represents the deformation height, and R represents the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer. Wherein, the second direction is also the y-axis direction.

[0113] In this way, the position offsets X and Y of the target overlay alignment mark in the horizontal direction are obtained. The calculation of the position offsets is simple, and the position information of the target overlay alignment mark in the horizontal direction can be accurately located.

[0114] In step S130, the position offset is output.

[0115] That is, the position offset calculated in step S120 is output to the target object, which is, for example, a lithography device, or other devices other than the lithography device.

[0116] In summary, the solution disclosed in the present application obtains the warpage information of the wafer after the front layer of the wafer is lithographically processed, and calculates the position offset of the target overlay alignment mark based on the warpage information of the wafer, thereby realizing the accurate positioning of the position information of the target overlay alignment mark. The position offset can be used in subsequent processes, specifically, when the wafer layer is lithographically processed, the position of the overlay alignment mark of the wafer layer can be compensated based on the position offset, thereby reducing the overlay error. Moreover, the present application does not need to change the original lithography process flow, and there is no increase or change in materials.

[0117] See next Fig. 9 As shown, this embodiment provides a device 900 for detecting the position offset of an overlay alignment mark. The device 900 for detecting the position offset of an overlay alignment mark mainly includes a warpage acquisition module 901 , an offset calculation module 902 and an offset output module 903 .

[0118] The warpage acquisition module 901 is used to acquire the warpage information of the wafer after the front-layer photolithography of the wafer is completed.

[0119] The offset calculation module 902 is used to calculate the position offset of the target overlay alignment mark based on the warpage information of the wafer, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer or an overlay alignment mark expected to be formed on the current layer of the wafer.

[0120] In one embodiment, the offset calculation module 902 is configured to: obtain the baseline position of the target overlay alignment mark; and calculate the position offset of the target overlay alignment mark based on the warpage information of the wafer and the baseline position of the target overlay alignment mark.

[0121] In one embodiment, the warping information of the wafer includes a critical position located between the warping position and the non-warping position of the wafer and a plurality of sampling point positions, wherein the plurality of sampling points are distributed along the radial spacing of the wafer and are located between the critical position and the edge position of the wafer; the offset calculation module 902 is configured to: perform curve fitting based on the critical position and the plurality of sampling point positions to obtain a corresponding curve function; construct an arc length expression based on the curve function; obtain a position offset of the target overlay alignment mark based on the distance between the critical position and the baseline position of the target overlay alignment mark and the arc length expression, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer.

[0122] In one embodiment, the offset calculation module 902 is configured as follows: taking the distance between the critical position and the center position of the wafer as the lower limit of integration, taking the actual distance between the target overlay alignment mark and the center position of the wafer after warping occurs as the upper limit of integration, constructing an arc length integral formula based on a curve function; and setting the distance between the critical position and the baseline position of the target overlay alignment mark as the arc length integral value; and obtaining the position offset of the target overlay alignment mark based on the arc length integral value and the arc length integral formula.

[0123] In one embodiment, the offset calculation module 902 is configured to: obtain the actual distance between the target overlay alignment mark and the center position of the wafer under the warping information based on the arc length integral value and the arc length integral formula; substitute the actual distance into the curve function to obtain the actual position of the target overlay alignment mark under the warping information; obtain the displacement vector based on the actual position and the baseline position as the position offset of the target overlay alignment mark.

[0124] In one embodiment, the number of the plurality of sampling points is at least three, and distances between adjacent sampling points in the plurality of sampling points are equal.

[0125] In one embodiment, the offset calculation module 902 is configured to obtain a position offset of a target overlay alignment mark based on the baseline position and the deformation angle of the wafer; wherein the target overlay alignment mark is an overlay alignment mark expected to be formed on the current layer of the wafer.

[0126] In one embodiment, the warpage information of the wafer includes the deformation height of the wafer; the offset calculation module 902 is configured to: obtain the horizontal distance between the baseline position and the center position of the wafer; based on the baseline position, the deformation height and the horizontal distance, obtain the position offset of the target overlay alignment mark.

[0127] In one embodiment, the offset calculation module 902 is configured to: based on the relationship The position offset of the target overlay alignment mark in the first direction in the horizontal direction is obtained, wherein X represents the position offset of the target overlay alignment mark in the first direction in the horizontal direction, Tx represents the position coordinate of the baseline position of the target overlay alignment mark in the first direction, h represents the deformation height, and R represents the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer.

[0128] Based on relational The position offset of the target overlay alignment mark in the second direction in the horizontal direction is obtained. Wherein, Y represents the position offset of the target overlay alignment mark in the second direction in the horizontal direction, Ty represents the position coordinate of the baseline position of the target overlay alignment mark in the second direction, h represents the deformation height, and R represents the horizontal distance between the baseline position of the target overlay alignment mark and the center position of the wafer.

[0129] The offset output module 903 is used to output the position offset calculated by the offset calculation module 902 .

[0130] The implementation process of the functions and effects of each module in the above-mentioned overlay alignment mark position offset detection device 900 is specifically described in the implementation process of the corresponding steps in the above-mentioned overlay alignment mark position offset detection method, which will not be repeated here.

[0131] See also Fig.10 As shown, this embodiment provides an electronic device 1000, which includes one or more processors 1001 and a memory 1002. The memory 1002 is used to store one or more programs. When the one or more programs are executed by one or more processors 1001, the electronic device 1000 implements the position offset detection method of the overlay alignment mark of the present application.

[0132] It should be noted that the electronic device 1000 may be a photolithography device, or may be other devices other than the photolithography device.

[0133] Fig.11 A block diagram of a computer system structure for implementing some embodiments of the present application is shown. It should be noted that: Fig.11 The computer system shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0134] like Fig.11 As shown, the computer system 1100 includes a CPU (Central Processing Unit) 1101, which can perform various appropriate actions and processes according to the program stored in the ROM (Read-Only Memory) 1102 or the program loaded from the storage part 1108 to the RAM (Random Access Memory) 1103, such as executing the position offset detection method of the overlay alignment mark in the above-mentioned embodiment. Various programs and data required for system operation are also stored in the RAM 1103. The CPU 1101, the ROM 1102 and the RAM 1103 are connected to each other through the bus 1104. The I / O (Input / Output) interface 1105 is also connected to the bus 1104.

[0135] The following components are connected to the I / O interface 1105: an input section 1106 including a keyboard, a mouse, etc.; an output section 1107 including a CRT (Cathode Ray Tube), an LCD (Liquid Crystal Display), etc., and a speaker, etc.; a storage section 1108 including a hard disk, etc.; and a communication section 1109 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1109 performs communication processing via a network such as the Internet. A drive 1110 is also connected to the I / O interface 1105 as needed. A removable medium 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1110 as needed so that a computer program read therefrom is installed into the storage section 1108 as needed.

[0136] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains a computer program for executing all or part of the steps shown in the flowchart in the method for detecting the position offset of the overlay alignment mark. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 1109, and / or installed from the removable medium 1111. When the computer program is executed by the central processing unit (CPU) 1101, various functions defined in the system of the present application are executed.

[0137] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by an instruction execution system, device or device or used in combination with it. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable computer program is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0138] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0139] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0140] As another aspect, the present application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method in the above embodiment.

[0141] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0142] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the implementation methods of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the implementation methods of the present application.

[0143] See next Fig.12 As shown, this embodiment provides a semiconductor processing method, which at least includes a wafer front layer photolithography step, a position offset detection step, and a wafer current layer photolithography step, which respectively correspond to the following steps S410 to S430, and are described in detail as follows:

[0144] In step S410, a photolithography process is performed on the front layer of the wafer.

[0145] Among them, the wafer front layer refers to the layer that completes the photolithography process before the wafer current layer, and the wafer current layer refers to the layer that will be photolithographically processed next.

[0146] In step S420, the aforementioned method for detecting the position offset of the overlay alignment mark is executed to obtain the position offset of the target overlay alignment mark.

[0147] The specific execution process of step S420 can refer to the above description and will not be repeated here.

[0148] Among them, it can be adopted Figure 5 The embodiment shown in the figure calculates the position offset of the target overlay alignment mark, and can also be used Figure 7 The embodiment shown calculates the position offset of the target overlay alignment mark. In detail, when the layer composition of the wafer is relatively simple and the warpage is slight, the method is adopted. Figure 7 The embodiment shown calculates the position offset of the target overlay alignment mark. At this time, only the two-dimensional position offset is obtained, and the calculation process is simpler. In the case where the layer composition of the wafer is relatively complex and the warping is severe, the method is adopted. Figure 5 The illustrated embodiment calculates the position offset of the target overlay alignment mark. In this case, a three-dimensional position offset can be obtained, which helps to control the overlay error to a smaller value.

[0149] In one embodiment, in order to reduce the overlay error as much as possible, when executing the position offset detection method, the position offsets of multiple target overlay alignment marks are detected, and the multiple target overlay alignment marks correspond to different position points of the wafer respectively. In this embodiment, when obtaining the warpage information of the wafer, the warpage information of multiple position points in the wafer is obtained, and each position point is associated with a target overlay alignment mark. The multiple position points can be distributed along the circumferential spacing of the wafer, or along the radial spacing of the wafer, or along the circumferential and radial spacing of the wafer, that is, the multiple position points include multiple position points distributed along the circumferential spacing of the wafer and multiple position points distributed along the radial spacing of the wafer. In this embodiment, the baseline positions of the target overlay alignment marks associated with the multiple position points are obtained; and based on the warpage information of each position point and the baseline position of the target overlay alignment mark associated with the position point, the position offset of the target overlay alignment mark associated with the position point is obtained.

[0150] Among them, when multiple position points are distributed along the circumferential spacing of the wafer, the position offset of the target overlay alignment mark associated with different position points on the circumference of the wafer can be obtained; when multiple position points are distributed along the radial spacing of the wafer, the position offset of the target overlay alignment mark associated with different position points in the radial direction of the wafer can be obtained; when multiple position points are distributed along the circumferential and radial spacing of the wafer, the position offset of the target overlay alignment mark associated with different position points on the circumference of the wafer can be obtained, as well as the position offset of the target overlay alignment mark associated with different position points in the radial direction of the wafer can be obtained.

[0151] It should be noted that the target overlay alignment mark associated with the position point, wherein the association can be that the position point and the target overlay alignment mark are exactly corresponding in position, or that the position point and the target overlay alignment mark are close in position. For example, the associated position point is one or some position points in the wafer part corresponding to the target overlay alignment mark that are close to the position corresponding to the target overlay alignment mark. The warping conditions of different parts of the wafer in the circumferential and radial directions are often different. By obtaining the warping information of multiple position points distributed at circumferential and / or radial intervals on the wafer, and obtaining the position offset of the target overlay alignment mark associated with each position point, the position information of more overlay alignment marks can be accurately located, so as to accurately perform photolithography processing in subsequent processes and reduce overlay errors.

[0152] Of course, in other embodiments, the warping information of only one position point in the wafer may be obtained. In this case, only the position offset of the target overlay alignment mark associated with the one position point will be obtained, and the subsequent lithography processing steps will only compensate for the position of the target overlay alignment mark associated with the one position point.

[0153] In step S430, based on the position offset output in step S420, photolithography is performed on the current layer of the wafer.

[0154] Among them, the position offset output by step S420 can be directly output to the lithography equipment. At this time, the lithography equipment directly performs lithography processing on the target overlay alignment mark corresponding to the wafer layer based on the position offset output by step S420, that is, the baseline position of the target overlay alignment mark corresponding to the wafer layer is compensated based on the position offset. For example, when the position of a target overlay alignment mark is offset to the left by d1 in the first direction, the baseline position of the target overlay alignment mark is adjusted to the right by d1 to obtain the compensated position, and then lithography processing is performed according to the compensated position; for another example, when the position of a target overlay alignment mark is offset forward by d2 in the second direction, the baseline position of the target overlay alignment mark is adjusted backward by d2 to obtain the compensated position, and then lithography processing is performed according to the compensated position.

[0155] The position offset output in step S420 can also be used to compensate the baseline position of the target overlay alignment mark according to the position offset to obtain a compensated position vector map, which is then output to the lithography equipment. The lithography equipment can directly use the position vector map for lithography processing.

[0156] The wafer front layer can be the first layer, the second layer, the third layer, etc. Fig.13 As shown, in one embodiment, after each layer of the wafer is subjected to photolithography processing, the warpage information of the wafer is obtained. When the warpage of the wafer exceeds the requirement, the subsequent processing steps are terminated to avoid meaningless processing steps and improve the utilization rate of the photolithography equipment. Before the photolithography processing is performed, the obtained warpage information of the wafer is used to perform step S420 to obtain the position offset of the target overlay alignment mark, and position compensation is performed during the photolithography processing.

[0157] Here, step S420 may be performed on multiple layers of the wafer and position compensation may be performed during the photolithography process, or step S420 may be performed only on a key layer of the wafer and position compensation may be performed during the photolithography process.

[0158] The scheme disclosed in the present application, after the wafer front layer is photolithographically processed, the wafer warpage information is obtained, and the position offset of the target overlay alignment mark is calculated based on the wafer warpage information, and then the wafer current layer is photolithographically processed based on the position offset. Specifically, the overlay alignment mark position of the wafer current layer can be compensated based on the position offset, and the position offset of the overlay alignment mark caused by the wafer warpage can be compensated, so that the overlay alignment mark of the wafer current layer is accurately aligned with the overlay alignment mark of the wafer front layer, reducing the overlay error. It can be applied to the processing of semiconductors such as Dram (Dynamic Random Access Memory), SRAM (Static Random Access Memory), 3D NAND (flash memory), Logic IC (logic integrated circuit), etc.

[0159] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the appended claims.

Claims

1. A method for processing a semiconductor, characterized in that: include: Photolithography of the front layer of the wafer; After the front layer of the wafer is photolithographically processed, the warpage information of the wafer is obtained, wherein the warpage information of the wafer includes a critical position between a warpage position and a non-warpage position of the wafer and a plurality of sampling point positions, wherein the plurality of sampling points are distributed along the radial spacing of the wafer and are located between the critical position and an edge position of the wafer; Acquiring a baseline position of a target overlay alignment mark, wherein the target overlay alignment mark is an overlay alignment mark formed on the front layer of the wafer; Performing curve fitting based on the critical position and the positions of the multiple sampling points to obtain a corresponding curve function; Taking the distance between the critical position and the center position of the wafer as the lower limit of integration, taking the actual distance between the target overlay alignment mark and the center position of the wafer after warping occurs as the upper limit of integration, constructing an arc length integral formula based on the curve function; Setting the distance between the critical position and the baseline position of the target overlay alignment mark as an arc length integral value; Based on the arc length integral value and the arc length integral formula, obtaining an actual distance between the target overlay alignment mark and the center position of the wafer under the warpage information; Substituting the actual distance into the curve function to obtain the actual position of the target overlay alignment mark under the warping information; Obtaining a displacement vector based on the actual position and the baseline position as a position offset of the target overlay alignment mark; Outputting the position offset; Compensating the baseline position of the target overlay alignment mark corresponding to the current layer of the wafer based on the output position offset to obtain a compensated position; The wafer layer is subjected to photolithography processing based on the compensated position.

2. The semiconductor processing method according to claim 1, characterized in that: The number of the multiple sampling points is at least three, and the distances between adjacent sampling points in the multiple sampling points are equal.

3. A method for processing a semiconductor, characterized in that: include: Photolithography of the front layer of the wafer; After the front layer of the wafer is photolithographically processed, the warpage information of the wafer is obtained, where the warpage information of the wafer includes the deformation height of the wafer; Acquiring a baseline position of a target overlay alignment mark, wherein the target overlay alignment mark is an overlay alignment mark expected to be formed on the current layer of the wafer; Acquire a horizontal distance between the baseline position and the center position of the wafer; Based on relational Obtaining a position offset of the target overlay alignment mark in a first direction in the horizontal direction, wherein X represents the position offset in the first direction, Tx represents the position coordinate in the first direction, h represents the deformation height, and R represents the horizontal distance; Based on relational Obtaining a position offset of the target overlay alignment mark in a second direction in the horizontal direction, wherein Y represents the position offset in the second direction, Ty represents the position coordinate in the second direction, h represents the deformation height, and R represents the horizontal distance; Outputting the position offset; Compensating the baseline position of the target overlay alignment mark corresponding to the current layer of the wafer based on the output position offset to obtain a compensated position; The wafer layer is subjected to photolithography processing based on the compensated position.

4. An electronic device, characterized in that: include: one or more processors; A memory for storing one or more computer programs, which, when executed by the one or more processors, enables the processors to implement the semiconductor processing method according to any one of claims 1 to 3.

5. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-readable instructions, and when the computer-readable instructions are executed by a processor of a computer, the computer is caused to execute the semiconductor processing method according to any one of claims 1 to 3.

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