Voltage regulator with diode holding function and electronic equipment

Abstract

The invention provides a voltage regulator with a diode holding function and electronic equipment. The voltage regulator with the diode holding function comprises an input terminal for receiving power supply voltage, an output terminal for providing stable voltage and a main circuit connected between the input terminal and the output terminal. In a normal mode, the main circuit converts a supply voltage into a first voltage as a stabilized voltage. In the sleep mode, the voltage regulator provides a diode connected between the input terminal and the output terminal of the voltage regulator to generate a second voltage as a stabilized voltage. The second voltage is lower than the first voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 515,350, filed on July 25, 2023. The contents of that application are hereby incorporated by reference. Technical Field

[0003] The invention relates to a voltage regulator, in particular to a reliable and small-volume voltage regulator. Background Art

[0004] A voltage regulator is a circuit that produces a stable voltage regardless of changes in the supply voltage or load conditions. Regulated voltage is often used to power digital devices.

[0005] Therefore, a reliable and compact voltage regulator is needed. Summary of the invention

[0006] The present disclosure provides a voltage regulator with a diode holding function.

[0007] According to an exemplary embodiment of the present disclosure, a voltage regulator with a diode hold function includes an input terminal for receiving a power supply voltage; an output terminal for providing a stable voltage; and a main circuit connected between the input terminal and the output terminal. In normal mode, the main circuit converts the power supply voltage into a first voltage as a stable voltage. In sleep mode, the voltage regulator provides a diode connected between the input terminal and the output terminal of the voltage regulator to generate a second voltage as a stable voltage. The second voltage is lower than the first voltage.

[0008] In an exemplary embodiment, an electronic device using the voltage regulator is shown. The electronic device also includes a digital flip-flop. The digital device is powered by a stable voltage provided by the voltage regulator and has a data retention function in a sleep mode. The data retention in the sleep mode is achieved by a second voltage generated by the voltage regulator in the sleep mode.

[0009] In an exemplary embodiment, the main circuit has a power transistor, which is a metal oxide semiconductor field effect transistor and has a drain connected to the input terminal of the voltage regulator and a source connected to the output terminal of the voltage regulator. In normal mode, the power transistor is biased to provide an active current to a load device connected to the output terminal of the voltage regulator. In sleep mode, the power transistor is biased to turn off the active current, and a diode (as another device different from the power transistor) is connected between the input terminal and the output terminal of the voltage regulator to provide a standby current to the load device. The standby current is lower than the active current. Due to the appropriate value of the standby current, the DFFs in the digital device powered by the voltage regulator still have data retention capability in sleep mode.

[0010] In an exemplary embodiment, the power transistor is a core device that can operate in a limited voltage range narrower than the operating range corresponding to the supply voltage. The voltage regulator does not use any high voltage device between the input terminal of the voltage regulator and the drain of the power transistor. The high voltage device can operate in a high voltage range wider than the limited voltage range. A small-sized voltage regulator is achieved and the reliability of the voltage regulator is guaranteed.

[0011] In an exemplary embodiment, the diode enabled in the sleep mode is provided by the main circuit itself. The main circuit has a power transistor connected between the input terminal and the output terminal of the voltage regulator to generate an active current in the normal mode, wherein the active current supplies the load device connected to the output terminal of the voltage regulator. In the sleep mode, the gate of the power transistor is connected to the drain and operates as a diode to provide a standby current to the load device. It is also appropriately designed that the standby current is lower than the active current. Therefore, in the sleep mode, the DFFs in the digital device powered by the voltage regulator also have data retention capabilities. In this type of exemplary embodiment, the power transistor may be a core device that operates in a limited voltage range narrower than the operating range corresponding to the power supply voltage. The voltage regulator may not use any high-voltage device between the input terminal of the voltage regulator and the drain of the power transistor. The high-voltage device can operate in a high voltage range wider than the limited voltage range. A small-sized voltage regulator is achieved and the reliability of the voltage regulator is guaranteed.

[0012] These and other objects of the present invention will no doubt become apparent to those of ordinary skill in the art from reading the following detailed description of the preferred embodiments and from referring to the various figures and drawings.

[0013] In summary, the present invention provides an efficient and reliable lateral diode suitable for backside power rail applications. By adopting innovative methods in the design, the present invention not only improves the efficiency of power management, but also improves the overall performance and reliability of the integrated circuit. The embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention may be more fully understood by reading the following detailed description and examples with reference to the accompanying drawings, in which:

[0015] Figure 1 According to an exemplary embodiment of the present disclosure, an electronic device 100 is shown;

[0016] Figure 2 According to an exemplary embodiment of the present disclosure, a voltage regulator 200 is shown;

[0017] Figure 3A and Figure 3B According to an exemplary embodiment of the present disclosure, details of the voltage regulator 200 are shown; and

[0018] Figure 4A and Figure 4B According to an exemplary embodiment of the present disclosure, a voltage regulator is shown which uses its power transistor Mpower to provide a diode path in a sleep mode. DETAILED DESCRIPTION

[0019] The following description is intended to illustrate the general principles of the invention and is not to be construed in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0020] Figure 1An electronic device 100 consistent with an exemplary embodiment of the present disclosure is shown, which includes a voltage regulator 102 with a diode hold function, and a digital device 104 including digital flip-flops (DFFs) 106. The voltage regulator 102 with a diode hold function includes a diode 108 enabled in a sleep mode. In a normal mode, the diode 108 is disabled, and the voltage regulator 102 converts a supply voltage Vsupply (received by its input terminal, also denoted as Vsupply hereinafter) into a first voltage Vreg1 as a stable voltage Vreg provided at its output terminal (also denoted as Vreg hereinafter) to power the digital device 104. In the sleep mode, the diode 108 in the voltage regulator 102 is enabled to generate a second voltage Vreg2 as a stable voltage Vreg to power the digital device 104. The second voltage Vreg2 is lower than the first voltage Vreg1 and is designed for data retention of the DFFs 106. In this way, when the electronic device 100 operates in the sleep mode, the data stored in the digital device 104 will not be lost.

[0021] Figure 2 A voltage regulator 200 consistent with an exemplary embodiment of the present disclosure is shown. Figure 1 In addition to the diode path 202 including the diode 108 described in the previous section, the voltage regulator 200 further includes a main circuit 204 that operates a power transistor 206 in a normal mode to generate a first voltage Vreg1 as a regulated voltage Vreg. In the sleep mode, a diode (108 in the diode path 202) connected between the input terminal Vsupply and the output terminal Vreg to generate a second voltage Vreg2 as a regulated voltage Vreg is another device different from the main circuit 204.

[0022] As shown, the diode path 202 can be implemented in a variety of ways.

[0023] The diode path 202 may be implemented as a circuit 208 including a p-channel metal oxide semiconductor field effect transistor (PMOS) Mp having a source connected to the input terminal Vsupply of the voltage regulator, a drain connected to the output terminal Vreg of the voltage regulator, and a gate connected to the drain of the PMOS Mp.

[0024] The diode path 202 may be implemented as a circuit 210. Compared with the circuit 208, the circuit 210 further includes a current-to-voltage component (such as a resistor R, but not limited thereto) connected between the input terminal Vsupply of the voltage regulator and the source of the PMOS Mp.

[0025] The diode path 202 may be implemented as a circuit 212 including an n-channel metal oxide semiconductor field effect transistor (NMOS) Mn having a drain connected to the input terminal Vsupply of the voltage regulator, a source connected to the output terminal Vreg of the voltage regulator, and a gate connected to the drain of the NMOS Mn.

[0026] The diode path 202 may be implemented as a circuit 214. Compared with the circuit 212, the circuit 214 further includes a current-to-voltage component (such as a resistor R, but not limited thereto) connected between the source of the NMOS Mn and the output terminal Vreg of the voltage regulator.

[0027] The diode path 202 may be implemented as a circuit 216 including a two-terminal component Ddiode, with an anode connected to the input terminal Vsupply of the voltage regulator and a cathode connected to the output terminal Vreg of the voltage regulator.

[0028] The diode path 202 can be implemented as a circuit 218, which includes an NMOS Mn and at least one PMOS Mp. The drain of the NMOS Mn is connected to the input terminal Vsupply of the voltage regulator, the source is connected to the output terminal Vreg of the voltage regulator, and the gate is connected to the drain of the NMOS Mn. The source of the PMOS Mp is connected to the input terminal Vsupply of the voltage regulator, the drain is connected to the output terminal Vreg of the voltage regulator, and the gate is connected to the drain of the PMOS Mp. In an exemplary embodiment, the NMOS Mn is a core device, and the PMOS Mp connected in parallel with the NMOS Mn is an input and output (IO) device. The core device Mn operates in a limited voltage range, while the IO device (Mp) operates in a higher voltage range wider than the limited voltage range. The core device Mn and the IO device (Mp) may handle different limit problems.

[0029] Figure 3A and Figure 3B Details of a voltage regulator 200 consistent with an exemplary embodiment of the present disclosure are shown.

[0030] Figure 3A The main circuit 302 of the proposed voltage regulator has a power transistor Mpower connected between the input terminal Vsupply and the output terminal Vref to generate an active current Iactive in the normal mode. The active current Iactive supplies a load device 304 (e.g. Figure 1In the normal mode, the diode path 306 is disconnected from the voltage regulator. The first voltage Vreg1 is generated by the main circuit 302 as a stable voltage Vreg.

[0031] Figure 3B The sleep mode design is shown. In sleep mode, the power transistor Mpower is biased to turn off Figure 3A , and a diode D is provided on a diode path 306. As shown in the figure, the diode D is another device different from the power transistor Mpower, and is a voltage regulator connected between the input terminal Vsupply and the output terminal Vreg in the sleep mode to provide a standby current Istandby to the load device 304. The standby current Istandby is lower than the active current Iactive. Therefore, the second voltage Vreg2 generated in the sleep mode is lower than the first voltage Vreg1, as a stable voltage Vreg. Data retention of the DFFs in the load device 304 is achieved in the sleep mode.

[0032] exist Figure 3A and Figure 3B In the example, the power transistor Mpower is a metal oxide semiconductor field effect transistor (NMOS as shown in the figure), whose drain is connected to the input terminal Vsupply of the voltage regulator, and the source is connected to the output terminal Vref of the voltage regulator. In the example, the main circuit 302 also includes a first resistor R1, three switches SW1 to SW3, and an operational amplifier op. The first resistor R1 and the first switch SW1 are connected in series between the source of the power transistor Mpower and a ground terminal. The second switch SW2 is placed between the gate and the source of the power transistor Mpower. The first input terminal of the operational amplifier op receives a reference voltage Vref, and the second input terminal is connected to the source of the power transistor Mpower. The third switch SW3 is connected between the output terminal of the operational amplifier op and the gate of the power transistor Mpower.

[0033] refer to Figure 3A In the normal mode, the first switch SW1 is closed, the second switch SW2 is open, and the third switch SW3 is closed. The first voltage Vreg1 is generated as a stable voltage Vreg.

[0034] refer to Figure 3B In the sleep mode, the first switch SW1 is open, the second switch SW2 is closed, and the third switch SW3 is open. The second voltage Vreg2 is generated as a stable voltage Vreg.

[0035] In other example embodiments, the main circuit 302 generates the first voltage Vreg1 in the normal mode and may be replaced by other types of voltage regulating circuits. The details of the main circuit 302 are not limited to the components shown.

[0036] In an exemplary embodiment, the power transistor Mpower is a core device operating in a limited voltage range narrower than the operating range corresponding to the supply voltage Vsupply. The proposed voltage regulator, as shown in the figure, does not use any high-voltage device (specifically, a device that can operate in a high voltage range wider than the limited voltage range) between the input terminal Vsupply of the voltage regulator and the drain of the power transistor Mpower. In the case where the supply voltage Vsupply is higher than the maximum tolerable voltage of the power transistor Mpower, the power transistor Mpower is in a sleep mode (reference Figure 3B ) is still well protected because the cross voltage VDS of the power transistor Mpower is (Vsupply-Vreg2), which is within the tolerable range of the power transistor Mpower. No high voltage device is required to protect the power transistor Mpower. The reliability of the power transistor Mpower is guaranteed, and the circuit size of the voltage regulator can be very small.

[0037] However, in some designs, there may be a high voltage device between the input terminal Vsupply of the voltage regulator and the drain of the power transistor Mpower. This depends on the design requirements.

[0038] In some example embodiments, Figure 1 The diode 108 shown in FIG. 1 is provided by changing the bias condition of the power transistor Mpower.

[0039] Figure 4A and Figure 4B A voltage regulator using its power transistor Mpower to provide a diode path in sleep mode is shown, according to an example embodiment of the present disclosure.

[0040] Figure 4A A normal mode design is shown. The power transistor Mpower is connected between the input terminal Vsupply and the output terminal Vref of the voltage regulator, and generates an active current Iactive to supply a load device connected to the output terminal Vreg of the voltage regulator. A first voltage Vreg1 is generated as a stable voltage Vreg.

[0041] Figure 4BThe sleep mode design is shown. The gate of the power transistor Mpower is connected to the drain of the power transistor Mpower through the second resistor R2, forming a diode that provides a standby current Istandby to the load device. The standby current Istandby is lower than the active current Iactive. The generated second voltage Vreg2 is lower than the first voltage Vreg1 and serves as a stable voltage Vreg. Data retention of the load device is achieved.

[0042] As shown in the figure, Figure 4A and 4B The voltage regulator shown in FIG. 1 is provided with a voltage divider 402. The voltage divider 402 is in sleep mode ( Figure 4B ) is enabled to generate a bias voltage Vx by dividing the supply voltage Vsupply, and the bias voltage is connected to the gate of the power transistor Mpower. The voltage divider 402 includes two resistors R2 and R3, and two switches SW4 and SW5. The second resistor R2 and the fourth switch SW4 are connected in series between the input terminal Vsupply of the voltage divider and the gate of the power transistor Mpower. The third resistor R3 and the fifth switch SW5 are connected in series between the gate of the power transistor Mpower and a ground terminal.

[0043] refer to Figure 4A , in the normal mode, the fourth switch SW4 and the fifth switch SW5 are opened, so the voltage divider 402 is disabled.

[0044] refer to Figure 4B In the sleep mode, the fourth switch SW4 and the fifth switch SW5 are closed, so the power transistor Mp is biased to behave as a diode.

[0045] exist Figure 4A and 4B In the example shown in , the voltage regulator has a first resistor R1, switches SW1 and SW3, and an operational amplifier op, such as Figure 3A and 3B described in, but not used Figure 3A and 3B The details of the voltage regulator are not limited to the components shown.

[0046] exist Figure 4A and 4B In the example of FIG. 1 , the power transistor Mpower is a core device that operates within a limited voltage range narrower than the operating range corresponding to the supply voltage Vsupply. Figure 4A and 4BThe proposed voltage regulator shown does not use any high voltage device (specifically, a high voltage device that can operate in a high voltage range wider than the limited voltage range) between the input terminal Vsupply of the voltage regulator and the drain of the power transistor Mpower. With the voltage divider 402, the power transistor Mpower is always well protected. No high voltage device is needed to protect the power transistor Mpower. The reliability of the power transistor Mpower is guaranteed, and the circuit size of the voltage regulator can be very small.

[0047] However, in some Figure 4A and 4B In a design derived from the example of , there may be a high voltage device between the input terminal Vsupply of the voltage regulator and the drain of the power transistor Mpower. This depends on the design requirements.

[0048] The proposed voltage regulator with diode hold function protects the regulated voltage Vreg from reaching zero. Therefore, the digital device powered by the voltage regulator performs well in data retention. The non-zero regulated voltage also ensures the reliability of the power transistor Mpower.

[0049] Although the present invention has been described by way of examples and preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (which are obvious to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

[0050] Although the present invention has been described by way of example and preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover various modifications and similar arrangements (which are obvious to those skilled in the art). Therefore, the scope of the appended claims should be interpreted in the broadest manner so as to cover all such modifications and similar arrangements.

Claims

1. A voltage regulator with a diode holding function, comprising: An input terminal for receiving a supply voltage; Output terminal, providing stable voltage; as well as a main circuit connected between the input terminal and the output terminal, and converting the supply voltage into a first voltage in a normal mode, wherein the first voltage is provided as the stable voltage in the normal mode; In the sleep mode, the voltage regulator provides a diode connected between the input terminal and the output terminal to generate a second voltage as the stable voltage, wherein the second voltage is lower than the first voltage.

2. The voltage regulator with diode holding function as claimed in claim 1, wherein: The main circuit has a power transistor connected to the voltage regulator between the input terminal and the output terminal to generate an active current in the normal mode, wherein the active current supplies a load device of the voltage regulator connected to the output terminal; and In the sleep mode, the power transistor is biased to turn off the active current, and the diode, as another device different from the power transistor, is connected to the voltage regulator between the input terminal and the output terminal to provide a standby current to the load device, wherein the standby current is lower than the active current.

3. The voltage regulator with diode holding function as claimed in claim 1, wherein: The main circuit has a power transistor, wherein the power transistor is a metal oxide semiconductor field effect transistor, a drain of which is connected to the input terminal of the voltage regulator, and a source of which is connected to the output terminal of the voltage regulator; In the normal mode, the power transistor is biased to provide an active current to a load device connected to the output terminal; In the sleep mode, the power transistor is biased to turn off the active current, and the diode, as another device different therefrom, is connected to the voltage regulator between the input terminal and the output terminal to provide a standby current to the load device, wherein the standby current is lower than the active current.

4. The voltage regulator with diode holding function as claimed in claim 3, wherein: The power transistor is a core device that operates in a limited voltage range that is narrower than the operating range corresponding to the supply voltage.

5. The voltage regulator with a diode hold function as claimed in claim 4, excluding any high voltage device, operating in a high voltage range wider than the limited voltage range, between the voltage regulator at the input terminal and the power transistor at the drain.

6. The voltage regulator with diode holding function as claimed in claim 3, wherein: The diode is formed by a p-channel MOSFET having a source connected to the input terminal of the voltage regulator, a drain connected to the output terminal of the voltage regulator, and a gate connected to the drain of the p-channel MOSFET.

7. The voltage regulator with diode holding function as claimed in claim 6, further comprising: A current-to-voltage component is connected between the input terminal of the voltage regulator and the source of the p-channel metal oxide semiconductor field effect transistor.

8. The voltage regulator with diode holding function as claimed in claim 3, wherein: The diode is formed by an n-channel MOSFET having a drain connected to the input terminal of the voltage regulator, a source connected to the output terminal of the voltage regulator, and a gate connected to the drain of the n-channel MOSFET.

9. The voltage regulator with diode holding function as claimed in claim 8, further comprising: A current-to-voltage component is connected between the n-channel MOSFET at the source and the voltage regulator at the output terminal.

10. The voltage regulator with diode holding function as claimed in claim 3, wherein: The diode is formed of a two-terminal component with an anode connected to the input terminal of the voltage regulator and a cathode connected to the output terminal of the voltage regulator.

11. The voltage regulator with diode holding function as claimed in claim 3, wherein: The diode is formed by a core device and input and output devices connected in parallel with the core device; and The core device operates within a limited voltage range, while the input and output devices operate within a higher voltage range that is wider than the limited voltage range.

12. The voltage regulator with diode holding function as claimed in claim 3, wherein: The diode is formed by an n-channel metal oxide semiconductor field effect transistor and a p-channel metal oxide semiconductor field effect transistor; The n-channel MOSFET has a drain connected to the input terminal of the voltage regulator, a source connected to the output terminal of the voltage regulator, and a gate connected to the drain of the n-channel MOSFET; as well as The p-channel MOSFET has a source connected to the input terminal of the voltage regulator, a drain connected to the output terminal of the voltage regulator, and a gate connected to the drain of the p-channel MOSFET.

13. The voltage regulator with diode holding function as claimed in claim 3, wherein the main circuit further comprises: A first resistor and a first switch are connected in series between a source of the power transistor and a ground terminal, wherein the first switch is closed in a normal mode and opened in a sleep mode; a second switch disposed between the gate of the power transistor and the source of the power transistor, wherein the second switch is open in the normal mode and closed in the sleep mode; an operational amplifier having a first input terminal receiving a reference voltage and a second input terminal connected to the source of the power transistor; as well as A third switch is connected between the output terminal of the operational amplifier and the gate of the power transistor, wherein the third switch is closed in the normal mode and opened in the sleep mode.

14. The voltage regulator with diode holding function as claimed in claim 1, wherein: The main circuit has a power transistor connected between an input terminal and an output terminal of a voltage regulator to generate an active current in a normal mode, wherein the active current is supplied to a load device connected to the output terminal of the voltage regulator; and In sleep mode, the gate of the power transistor is connected to the drain of the power transistor to form a diode, providing a standby current to the load device, wherein the standby current is lower than the active current.

15. The voltage regulator with diode holding function as claimed in claim 14, further comprising: A voltage divider, enabled in sleep mode, divides the supply voltage to generate a bias voltage, which is connected to the gate of the power transistor.

16. The voltage regulator with diode hold function as claimed in claim 15, wherein the voltage divider comprises: a second resistor and a fourth switch connected in series between the input terminal of the voltage divider and the gate of the power transistor, wherein the fourth switch is open in the normal mode and closed in the sleep mode; as well as A third resistor and a fifth switch are connected in series between the gate of the power transistor and a ground terminal, wherein the fifth switch is opened in the normal mode and closed in the sleep mode.

17. The voltage regulator with diode holding function as claimed in claim 15, wherein: A power transistor is a core device that operates in a limited voltage range that is narrower than the operating range corresponding to the supply voltage.

18. The voltage regulator with diode hold function as claimed in claim 17, without any high voltage device, operating in a high voltage range wider than the limited voltage range, located between the input terminal of the voltage regulator and the drain of the power transistor.

19. The voltage regulator with diode holding function as claimed in claim 15, wherein the main circuit further comprises: A first resistor and a first switch are connected in series between a source of the power transistor and a ground terminal, wherein the first switch is closed in the normal mode and opened in the sleep mode; an operational amplifier having a first input terminal receiving a reference voltage and a second input terminal connected to the source of the power transistor; as well as A third switch is connected between the output terminal of the operational amplifier and the gate of the power transistor, wherein the third switch is closed in the normal mode and opened in the sleep mode.

20. An electronic device comprising: The voltage regulator with diode holding function as claimed in claim 1 and generating a regulated voltage; as well as A digital device including a digital flip-flop, wherein the digital device is powered by a regulated voltage provided by a voltage regulator and has a data retention function in a sleep mode.

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