A chip power consumption reduction method and system based on dynamic frequency adjustment

Abstract

The present invention discloses a method and system for reducing chip power consumption based on dynamic frequency adjustment. The method includes, during the operation of the integrated chip, for any one of the multiple hosts, calculating in real time the transmission path delay value of the host accessing each slave; comparing the transmission path delay value with the delay theoretical value, and determining the clock frequency adjustment scheme of the host accessing the transmission path where each slave is located according to the comparison result; and determining the clock frequency adjustment scheme of the integrated chip according to the clock frequency adjustment scheme of each host accessing the transmission path where each slave is located. The scheme provided by the present invention can reduce the power consumption of the entire chip and can be applied to various application scenarios of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated chips, and in particular to a method and system for reducing chip power consumption based on dynamic frequency regulation. Background Art

[0002] With the development of semiconductor material technology, IC integration has reached an unprecedented level. The number of transistors integrated on a single chip has exceeded 1 billion, and chip functions have become more and more complex and diversified. The advancement of science and technology has brought about an improvement in living standards, and people's pursuit of quality of life is also gradually improving. In contemporary society, electronic devices have become indispensable and have penetrated into every aspect of our lives, bringing more convenience and enjoyment to life. However, with the popularization of handheld electronic devices, people have put forward higher challenges for smallness, flexibility and durability. While mobile devices bring pleasure, standby time has also become a growing focus. Therefore, the low power consumption solution of chips has attracted much attention and has become an important measurement indicator for a chip. However, there is still a lot of room for improvement in the existing chip design in terms of reducing power consumption. Summary of the invention

[0003] In order to solve the technical problem of high power consumption in existing chip design solutions, an embodiment of the present invention provides a method and system for reducing chip power consumption based on dynamic frequency adjustment.

[0004] The technical solution of the embodiment of the present invention is achieved as follows:

[0005] An embodiment of the present invention provides a chip power consumption reduction method based on dynamic frequency adjustment, which is applied to an integrated chip, wherein the integrated chip includes multiple hosts, multiple slaves and a bus matrix, wherein any one of the multiple hosts is connected to each of the multiple slaves through the bus matrix, and the method includes: during the operation of the integrated chip, for any one of the multiple hosts, calculating in real time a transmission path delay value for the host to access each slave; comparing the transmission path delay value with a theoretical delay value, and determining a clock frequency adjustment scheme for the host to access the transmission path where each slave is located according to the comparison result; determining a clock frequency adjustment scheme for the integrated chip according to the clock frequency adjustment scheme for each host to access the transmission path where each slave is located;

[0006] Among them, the clock frequency adjustment scheme for the host to access the transmission path where each slave is located is determined according to the comparison result, including: if the transmission path delay value is greater than the first value preset by the delay theoretical value, the clock frequency adjustment scheme for the host to access the transmission path where each slave is located is determined to increase the clock frequency of the transmission path where the host is located to access the slave; if the transmission path delay value is less than the second value preset by the delay theoretical value, the clock frequency adjustment scheme for the host to access the transmission path where each slave is located is determined to reduce the clock frequency of the transmission path where the host is located to access the slave.

[0007] In one embodiment, a method for obtaining a theoretical delay value includes: constructing a corresponding simulation scenario according to the integrated architecture of the integrated chip; based on the simulation scenario, extracting an ideal delay value for any one of the multiple hosts in the simulation scenario to access each slave, and using the ideal delay value as the theoretical delay value for the host to access the slave.

[0008] In one embodiment, the transmission path delay value of the host accessing each slave is calculated in real time, including: using the real-time calculation module inside the integrated chip to calculate in real time the actual delay value of each transmission of the host accessing the slave; taking an average value of the actual delay value of each transmission based on the actual delay value of each transmission, and determining the average value as the transmission path delay value of the host accessing the slave.

[0009] In one embodiment, comparing the transmission path delay value with the delay theoretical value includes: comparing the transmission path delay value with the delay theoretical value using the following calculation formula:

[0010] Formula (1)

[0011] Formula (2)

[0012] in, Rmn1 The actual access delay value of the first transmission from the host Master m to the slave Slave n; Rmn2 The actual access delay value of the second transmission from the host Master m to the slave Slave n; Rmnk is the actual access delay value of the kth transmission from the host Master m to the slave Slave n, k is the number of transmissions from the master m to the slave n, is the theoretical value deviation, Lm It is the theoretical value of the delay from the master m to the slave n.

[0013] In one embodiment, the preset first value is the same as the preset second value.

[0014] In one embodiment, increasing or decreasing the clock frequency of the transmission path where the host accesses the slave includes: determining a clock node of the transmission path where the host accesses the slave, the clock node including a host, a slave and / or a bus matrix; and adjusting the working clock of the clock node using a polling scheduling method to increase or decrease the clock frequency of the transmission path where the host accesses the slave.

[0015] In one embodiment, a polling scheduling method is adopted to adjust the working clock of the clock node, including: when the polling scheduling method is adopted to adjust the working clock of the clock node, the upward adjustment frequency of each clock node cannot exceed the approval frequency of the clock node, and the downward adjustment frequency of each clock node cannot be lower than the lowest frequency of the clock node.

[0016] An embodiment of the present invention also provides a chip power consumption reduction system based on dynamic frequency adjustment, comprising: a processor and a memory for storing a computer program that can be run on the processor; wherein, when the processor is used to run the computer program, it executes the steps of any of the above methods.

[0017] An embodiment of the present invention further provides a storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0018] The chip power consumption reduction method and system based on dynamic frequency adjustment provided by the embodiment of the present invention, during the operation of the integrated chip, for any one of the multiple hosts, the transmission path delay value of the host accessing each slave is calculated in real time; the transmission path delay value is compared with the delay theoretical value, and the clock frequency adjustment scheme of the host accessing the transmission path where each slave is located is determined according to the comparison result; according to the clock frequency adjustment scheme of each host accessing the transmission path where each slave is located, the clock frequency adjustment scheme of the integrated chip is determined. The scheme provided by the present invention can reduce the power consumption of the entire chip and can be applied to various application scenarios of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a flow chart of a method for reducing chip power consumption based on dynamic frequency adjustment according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the integrated chip architecture according to an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of access delay in a simulation scenario according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of a clock node according to an embodiment of the present invention;

[0023] Figure 5 1 is a diagram showing the internal structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0025] An embodiment of the present invention provides a chip power consumption reduction method based on dynamic frequency adjustment, which is applied to an integrated chip, wherein the integrated chip includes a plurality of hosts, a plurality of slaves, and a bus matrix, wherein any one of the plurality of hosts is connected to each of the plurality of slaves through the bus matrix, such as Figure 1 As shown, the method includes:

[0026] Step 101: During the operation of the integrated chip, for any one of the plurality of hosts, a transmission path delay value of the host accessing each slave is calculated in real time;

[0027] Step 102: Compare the transmission path delay value with the delay theoretical value, and determine a clock frequency adjustment scheme for the host to access the transmission path where each slave is located according to the comparison result;

[0028] Step 103: Determine the clock frequency adjustment scheme of the integrated chip according to the clock frequency adjustment scheme of the transmission path where each host accesses each slave.

[0029] When the integrated chip is working, due to different application scenarios, the working states of various modules inside the integrated chip will be different. In order to achieve the purpose of saving power consumption of the entire chip, according to different working states, this embodiment adjusts the clock frequency of different functional blocks to achieve the effect of reducing the power consumption of the entire integrated chip. That is, this embodiment dynamically adjusts the clock frequency according to the operation of the entire chip, thereby achieving the effect of reducing the power consumption of the entire chip.

[0030] The power consumption of a chip generally consists of static power consumption and dynamic power consumption. Static power consumption is also called leakage power consumption, which refers to the power consumption generated by leakage current when the circuit is in a waiting or inactive state; dynamic power consumption is mainly the dynamic switching power consumption caused by dynamic switching current. Static power consumption is related to the process. Therefore, reducing power consumption in this embodiment mainly refers to reducing dynamic power consumption. Common methods for reducing power consumption include gated clock, dynamic voltage frequency scaling (Dynamic Voltage Frequency Scaling, DVFS), power gating (Power-Gating) and multi-threshold voltage design. The method for reducing power consumption in this embodiment belongs to a type of DVFS, which has the characteristics of high flexibility and strong applicability.

[0031] Specifically, see Figure 2 This embodiment will take a certain project as an example to introduce the solution of this embodiment in detail.

[0032] like Figure 2 As shown, in this embodiment, the integrated chip is interconnected by multiple masters and multiple slaves through a bus matrix. In the bus topology, all masters have access rights to all slaves.

[0033] To achieve dynamic adjustment of the clock frequency, this embodiment will dynamically adjust the clock frequency of the data path within an adjustable range according to the comparison result between the theoretical delay value and the actual delay value after the chip works normally.

[0034] Here, for the theoretical value of delay, an integrated architecture based on an integrated chip can be used to build a corresponding simulation scenario to determine the theoretical value of delay.

[0035] Specifically, this embodiment can test the theoretical value of the delay of each Master accessing each Slave under ideal conditions through a unit simulation test environment according to the application scenario. Figure 3 As shown, L11 can be defined as the specific access delay theoretical value of Master 1 to Slave 1, and L1n can be defined as the specific access delay theoretical value of Master 1 to Slave n. Similarly, Lmn is the theoretical access delay value of Master m to Slave n.

[0036] That is, in one embodiment, a corresponding simulation scenario is constructed according to the integrated architecture of the integrated chip; based on the simulation scenario, an ideal delay value for any one of the multiple hosts in the simulation scenario to access each slave is extracted, and the ideal delay value is used as the theoretical delay value for the host to access the slave.

[0037] In addition, for the actual delay value in the actual scenario, this embodiment can calculate in real time the actual delay value of each master to each slave in each transmission, and then use the average method according to the configuration options, and take into account the theoretical value deviation Here, Rmn can be used to represent the actual delay value of the access from the master to the slave in actual situations.

[0038] That is, in one embodiment, the real-time calculation module inside the integrated chip is used to calculate in real time the actual delay value of each transmission of the host accessing the slave; based on the actual delay value of each transmission, the actual delay value of each transmission is averaged, and the average is determined as the transmission path delay value of the host accessing the slave.

[0039] Here, the transmission path delay value can be compared with the delay theoretical value using the following calculation formula:

[0040] Formula (1)

[0041] Formula (2)

[0042] in, Rmn1 The actual access delay value of the first transmission from the host Master m to the slave Slave n; Rmn2 The actual access delay value of the second transmission from the host Master m to the slave Slave n; Rmnk is the actual access delay value of the kth transmission from the host Master m to the slave Slave n, k is the number of transmissions from the master m to the slave n, is the theoretical value deviation, Lm It is the theoretical value of the delay from the master m to the slave n.

[0043] When calculation formula (1) is satisfied, the clock node in the data path needs to be adjusted upward; when calculation formula (2) is satisfied, the clock node in the data path needs to be adjusted downward.

[0044] That is, in one embodiment, a clock frequency adjustment scheme for the host to access the transmission path where each slave is located is determined based on the comparison result, including: if the transmission path delay value is greater than a first value preset by the delay theoretical value, determining that the clock frequency adjustment scheme for the host to access the transmission path where each slave is located is to increase the clock frequency of the transmission path where the host is located to access the slave; if the transmission path delay value is less than a second value preset by the delay theoretical value, determining that the clock frequency adjustment scheme for the host to access the transmission path where each slave is located is to reduce the clock frequency of the transmission path where the host is located to access the slave.

[0045] Here, the preset first value is the same as the preset second value.

[0046] Due to different data paths (i.e., transmission paths), there may be multiple clock nodes. Therefore, after determining that a clock node in the data path needs to be adjusted up or down, the clock frequencies of multiple clock nodes on the data path can be adjusted. Here, the arbitration strategy for adjusting the clock nodes can select the round robin method.

[0047] like Figure 4 As shown, the clock nodes are the clocks used by different modules in the data path, C11 is the working clock of the master Master1, C12 is the bus matrix clock, and C13 is the clock used by the slave Slave 1.

[0048] That is, in one embodiment, increasing or decreasing the clock frequency of the transmission path where the host accesses the slave includes: determining the clock node of the transmission path where the host accesses the slave, the clock node including the host, the slave and / or the bus matrix; and adjusting the working clock of the clock node by using a polling scheduling method to increase or decrease the clock frequency of the transmission path where the host accesses the slave.

[0049] In addition, when adjusting, please note that the clock adjustment must be within a certain range. When designing the chip backend, each clock node needs a sign-off frequency, which is the highest clock frequency of the chip's clock node. The clock adjustment frequency cannot exceed the sign-off frequency of the clock node. At the same time, for some specific modules, there is a minimum clock frequency. When the clock is adjusted down, it cannot be lower than the minimum frequency value of the clock node.

[0050] That is, in one embodiment, the working clock of the clock node is adjusted by a polling scheduling method, including: when the working clock of the clock node is adjusted by a polling scheduling method, the upward adjustment frequency of each clock node cannot exceed the approval frequency of the clock node, and the downward adjustment frequency of each clock node cannot be lower than the lowest frequency of the clock node.

[0051] The core idea of ​​the method for reducing power consumption introduced in this embodiment is to calculate the actual delay value of the transmission path in real time, and compare it with the delay theoretical value by taking the average of multiple transmissions. If the actual delay value is significantly higher than the delay theoretical value, there may be multiple Masters accessing at the same time, resulting in insufficient response capability on the Slave side. In this case, the supply and demand relationship can be achieved by increasing the frequency of the data path node; if the actual delay value is significantly lower than the delay theoretical value, the data path may be relatively idle. In this case, the power consumption can be reduced by reducing the clock frequency of the path node.

[0052] The method for dynamically adjusting the clock frequency introduced in this embodiment can reduce the overall power consumption of the chip, play a role in energy saving, and has flexibility.

[0053] The chip power consumption reduction method based on dynamic frequency adjustment provided by the embodiment of the present invention, during the operation of the integrated chip, for any one of the multiple hosts, the transmission path delay value of the host accessing each slave is calculated in real time; the transmission path delay value is compared with the delay theoretical value, and the clock frequency adjustment scheme of the host accessing the transmission path where each slave is located is determined according to the comparison result; according to the clock frequency adjustment scheme of each host accessing the transmission path where each slave is located, the clock frequency adjustment scheme of the integrated chip is determined. The scheme provided by the present invention can reduce the power consumption of the entire chip and can be applied to various application scenarios of the chip.

[0054] In order to implement the method of an embodiment of the present invention, an embodiment of the present invention also provides a chip power consumption reduction system based on dynamic frequency adjustment, including: a processor and a memory for storing a computer program that can be run on the processor; wherein, when the processor is used to run the computer program, the steps of any one of the above methods are executed.

[0055] The above-mentioned system provided in this embodiment belongs to the same concept as the above-mentioned method embodiment. The specific implementation process thereof is detailed in the method embodiment and will not be repeated here.

[0056] In order to implement the method of the embodiment of the present invention, the embodiment of the present invention also provides a computer program product, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of the above method.

[0057] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiment of the present invention, the embodiment of the present invention further provides an electronic device (computer device). Specifically, in one embodiment, the computer device may be a terminal, and its internal structure diagram may be as follows: Figure 5 As shown. The computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05 and a memory (not shown in the figure) connected through a system bus. Among them, the processor A01 of the computer device is used to provide computing and control capabilities. The memory of the computer device includes an internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 in the non-volatile storage medium A06. The network interface A02 of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor A01, the method of any one of the above embodiments is implemented. The display screen A04 of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device A05 of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0058] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0059] The device provided by the embodiment of the present invention includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, the method of any one of the above embodiments is implemented.

[0060] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0061] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0062] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0063] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0064] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0065] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0066] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0067] It can be understood that the memory of the embodiment of the present invention can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memories described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memories.

[0068] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0069] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A method for reducing chip power consumption based on dynamic frequency adjustment, characterized in that: Applied to an integrated chip, the integrated chip includes a plurality of hosts, a plurality of slaves and a bus matrix, any one of the plurality of hosts is connected to each of the plurality of slaves through the bus matrix, the method includes: During the operation of the integrated chip, for any one of the multiple hosts, a transmission path delay value of the host accessing each slave is calculated in real time; Compare the transmission path delay value with the delay theoretical value, and determine a clock frequency adjustment scheme for the host to access the transmission path where each slave is located according to the comparison result; Determine the clock frequency adjustment scheme of the integrated chip according to the clock frequency adjustment scheme of the transmission path where each host accesses each slave; Wherein, determining the clock frequency adjustment scheme of the transmission path where the host accesses each slave according to the comparison result includes: If the transmission path delay value is greater than a preset first value of the delay theoretical value, determining that a clock frequency adjustment scheme for the host to access the transmission path where each slave is located is to increase the clock frequency of the host to access the transmission path where the slave is located; If the transmission path delay value is less than a preset second value of the delay theoretical value, the clock frequency adjustment scheme for the host to access the transmission path where each slave is located is determined to reduce the clock frequency of the host to access the transmission path where the slave is located.

2. The chip power consumption reduction method based on dynamic frequency adjustment according to claim 1, characterized in that: Methods for obtaining the theoretical value of delay include: According to the integrated architecture of the integrated chip, a corresponding simulation scenario is constructed; Based on the simulation scenario, an ideal delay value for any one of the multiple hosts in the simulation scenario to access each slave is extracted, and the ideal delay value is used as a theoretical delay value for the host to access the slave.

3. The chip power consumption reduction method based on dynamic frequency adjustment according to claim 1, characterized in that: Calculating in real time the transmission path delay value of the host accessing each slave, including: Using the real-time calculation module inside the integrated chip to calculate in real time the actual delay value of each transmission of the host accessing the slave; According to the actual delay value of each transmission, an average value of the actual delay value of each transmission is taken, and the average value is determined as the transmission path delay value of the host accessing the slave.

4. The chip power consumption reduction method based on dynamic frequency adjustment according to claim 3, characterized in that: Comparing the transmission path delay value with a theoretical delay value includes: The transmission path delay value is compared with the delay theoretical value using the following calculation formula: Formula (1) Formula (2) in, Rmn1 The actual access delay value of the first transmission from the host Master m to the slave Slave n; Rmn2 The actual access delay value of the second transmission from the host Master m to the slave Slave n; Rmnk is the actual access delay value of the kth transmission from the host Master m to the slave Slaven, k is the number of transmissions from the master m to the slave n, is the theoretical value deviation, Lm It is the theoretical value of the delay from the master m to the slave n.

5. The chip power consumption reduction method based on dynamic frequency adjustment according to claim 4, characterized in that: Increasing or decreasing the clock frequency of the transmission path where the host accesses the slave, comprising: Determine a clock node of a transmission path where the host accesses the slave, wherein the clock node includes a host, a slave and / or a bus matrix; The working clock of the clock node is adjusted by adopting a polling scheduling method to increase or decrease the clock frequency of the transmission path where the host accesses the slave.

6. The chip power consumption reduction method based on dynamic frequency adjustment according to claim 5, characterized in that: The working clock of the clock node is adjusted by using a polling scheduling method, including: When the working clock of the clock node is adjusted by polling scheduling, the upward adjustment frequency of each clock node cannot exceed the approval frequency of the clock node, and the downward adjustment frequency of each clock node cannot be lower than the minimum frequency of the clock node.

7. A chip power consumption reduction system based on dynamic frequency adjustment, characterized in that: The system comprises: a processor and a memory for storing a computer program that can be run on the processor; wherein the processor executes the steps of the method according to any one of claims 1 to 6 when running the computer program.

8. A storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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