A method and device for improving diagnostic coverage at gate-level netlist stage

Abstract

The present invention provides a method and device for improving diagnostic coverage at the gate-level netlist stage, comprising: obtaining chip information, and obtaining a gate-level netlist 1 based on the chip information; in the gate-level netlist 1, obtaining a unit 1 not covered by a security mechanism based on the chip information and storing it in a logic list 1; in the unit 1, obtaining a unit 2 that needs to be inserted with redundant logic based on a preset condition and storing it in a logic list 2; step S3: obtaining the redundant logic unit of the unit 2, inserting the redundant logic unit into the unit 2, and integrating to generate a gate-level netlist 2; judging whether the functions of the gate-level netlist 1 and the netlist 2 are consistent, and if so, executing step S6; step S6: obtaining the IP diagnostic coverage and IP area in the gate-level netlist 2, and judging whether the IP diagnostic coverage reaches the preset coverage and whether the IP area reaches the preset area, and if at least one of the conditions is not met, returning to step S3.

Description

Technical Field

[0001] The present invention relates to the field of chip design technology, and in particular to a method for improving diagnostic coverage at a gate-level netlist stage, a device for improving diagnostic coverage, an automotive chip, and a computer-readable storage medium. Background Art

[0002] Functional safety refers to the overall safety components of a system. Functional safety is critical for complex systems such as automobiles or industrial control. The diagnostic coverage of functional safety can prove whether the product is strictly restricted and can operate safely and reliably during the product life cycle. Therefore, as safety requirements increase, the diagnostic coverage of functional safety mainly quantifies and identifies the safety redundancy functions of systems and components to ensure product safety. For example, adding error correction code (ECC) or cyclic redundancy check (CRC) to the data path, using lockstep to increase safety redundancy for the central processing unit (CPU), and so on.

[0003] More and more consumer chips or industrial control chips have the demand for increased functional safety. At the same time, many automotive-grade chips also require higher functional safety standards as products are upgraded.

[0004] In the current mainstream design process, upgrading consumer or industrial control chips to functional safety chips or upgrading the functional safety level of existing automotive chips requires a full understanding of the system's functions and modifying its register transfer level circuit (RTL Circuit) for optimization. A complex IP or chip may have a design of more than 10 million gates, so upgrading or modifying the IP or chip usually requires a long chip development time and high costs.

[0005] Moreover, for self-developed IP, it is difficult to accurately and comprehensively cover the module or the cost of achieving functional safety is relatively high at the RTL level. For third-party IP, RTL level circuit modification means that the architecture of the IP needs to be further understood and analyzed, which will introduce a lot of time costs in addition to the aforementioned disadvantages. At the same time, since the RTL level circuit has been modified, it is also necessary to re-verify the function to ensure the correctness of the original function. Therefore, using traditional solutions for functional safety upgrades is bound to introduce greater development costs.

[0006] Therefore, it is necessary to provide a method for improving diagnostic coverage at the gate-level netlist stage, a device for improving diagnostic coverage, an automotive chip and a computer-readable storage medium to effectively solve the above problems. Summary of the invention

[0007] The present invention provides a method for improving the diagnostic coverage rate at the gate-level netlist stage, a device for improving the diagnostic coverage rate, an automobile chip and a computer-readable storage medium.

[0008] An embodiment of the present invention provides a method for improving diagnostic coverage at a gate-level netlist stage, comprising:

[0009] Step S1: Obtain chip information, and obtain a gate-level netlist 1 based on the chip information;

[0010] Step S2: in the gate-level netlist 1, based on the chip information, obtaining the unit 1 not covered by the security mechanism and storing it in the logic list 1;

[0011] Step S3: in the unit 1, based on the preset conditions, obtaining the unit 2 that needs to insert redundant logic and storing it in the logic list 2;

[0012] Step S4: obtaining the redundant logic unit to be inserted into each of the units 2 in the logic list 2, and inserting the redundant logic unit into each of the units 2, integrating the redundant logic unit obtained based on the unit 2 with the gate-level netlist 1 storing the unit 2 to generate a gate-level netlist 2;

[0013] Step S5: Determine whether the functions of the gate-level netlist 1 and the gate-level netlist 2 are consistent, if they are consistent, execute step S6;

[0014] Step S6: Obtain the IP diagnostic coverage and IP area in the gate-level netlist 2, and determine whether the IP diagnostic coverage reaches a preset coverage and whether the IP area reaches a preset area. If at least one of the conditions is not met, return to step S3.

[0015] Preferably, step S2 comprises:

[0016] Performing simulation error injection through VC_Z01X software to generate a diagnostic coverage report for the gate-level netlist 1;

[0017] Based on the chip information and the diagnostic coverage report, the unit 1 is obtained and stored in the logic list 1.

[0018] Preferably, step S3 comprises:

[0019] Acquiring classification information, and identifying and classifying the unit 1 based on the classification information;

[0020] Based on the preset condition, the unit 2 into which redundant logic needs to be inserted is selected from the classified unit 1, and stored in the logic list 2;

[0021] Among them, the preset conditions include the IP diagnostic coverage and the relationship between the IP area and the target conditions.

[0022] Preferably, step S4 comprises:

[0023] Step S41, obtaining the FPR value 1 of each of the cells 2, and storing the cell name and the FPR value 1 of each of the cells 2 in a two-dimensional data lookup table;

[0024] Step S42, based on the traversal of the driving logic and the load logic of each of the units 2, the circuit of each of the units 2 is obtained to form a corresponding virtual module, and the virtual module and other target units in the logic list 2 except the unit 2 included in the virtual module are stored in an independent database;

[0025] Step S43: obtaining the redundant logic unit based on the independent database.

[0026] Preferably, the step S42 includes:

[0027] Step S421, obtaining the driving logic of each of the units 2 based on the virtual module, and calculating its FPR value 2;

[0028] Step S422, determining whether the FPR value 2 of each of the driving logics becomes smaller, and if so, forming a new virtual module 2 based on the driving logic corresponding to the FPR value 2 and the virtual module;

[0029] Step S423, obtaining the load logic of each of the units 2 based on the virtual module, and calculating its FPR value 3;

[0030] Step S424 , determining whether the FPR value 3 of each load logic becomes smaller, and if so, forming a new virtual module 3 based on the load logic corresponding to the FPR value 3 and the virtual module.

[0031] Preferably, in step S6, simulation error injection is performed by using VC_Z01X software to obtain the IP diagnostic coverage in the gate-level netlist 2.

[0032] Furthermore, a device for improving diagnostic coverage is provided, comprising:

[0033] The acquisition module is used to execute step S1: acquire chip information, and obtain a gate-level netlist 1 based on the chip information; step S2: in the gate-level netlist 1, acquire a unit 1 not covered by the security mechanism based on the chip information and store it in a logic list 1; step S3: in the unit 1, acquire a unit 2 that needs to be inserted with redundant logic based on a preset condition and store it in a logic list 2;

[0034] A verification processing module, configured to execute step S4: obtaining redundant logic units of each of the units 2 in the logic list 2, inserting the redundant logic units into the unit 2, and integrating the redundant logic units obtained based on the unit 2 with the gate-level netlist 1 storing the unit 2 to generate a gate-level netlist 2;

[0035] The detection module is used to execute step S5: determine whether the functions of the gate-level netlist 1 and the gate-level netlist 2 are consistent, and if they are consistent, execute step S6; step S6: obtain the IP diagnostic coverage and IP area in the gate-level netlist 2, and determine whether the IP diagnostic coverage reaches the preset coverage and whether the IP area reaches the preset area. If at least one of the conditions is not met, return to step S3.

[0036] Furthermore, an automotive chip is provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above-described methods when executing the computer program.

[0037] Furthermore, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0038] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0039] The method for improving diagnostic coverage, the device for improving diagnostic coverage, the automotive chip and the computer-readable storage medium provided by the embodiments of the present invention propose an efficient solution to improve functional safety diagnostic coverage at the gate-level netlist stage. The solution can identify and classify units based on the gate-level netlist of the IP or chip without in-depth understanding of the functions of the IP, use algorithms to optimize units, and complete the generation of redundant units, thereby improving the IP diagnostic coverage to meet the defined functional safety rating standards. The method is simple to implement and saves development costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are some embodiments of the present invention, not all embodiments. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0041] Figure 1 A schematic flow chart of a method for improving diagnostic coverage provided by an embodiment of the present invention;

[0042] Figure 2 A schematic diagram of a process of step S4 provided for one embodiment of the present invention;

[0043] Figure 3a-3d A schematic diagram of a process of forming a virtual module from an independent unit in a logic unit list provided by an embodiment of the present invention;

[0044] Figure 4 A structural diagram of a method for improving diagnostic coverage by inserting redundant logic in a netlist provided by an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of the structure of a logic block and redundant logic in a practical application scenario provided for some embodiments of the present application;

[0046] Figure 6 A schematic diagram of a module of a device for improving diagnostic coverage provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0049] Based on the problems existing in the prior art, the embodiments of the present invention provide a new method for improving diagnostic coverage, a device for improving diagnostic coverage, an automotive chip and a computer-readable storage medium.

[0050] Figure 1A flow chart of a method for improving diagnostic coverage provided by an embodiment of the present invention.

[0051] Figure 1 As shown, an embodiment of the present invention provides a method for improving diagnostic coverage, including: Step S1: acquiring chip information, and obtaining a gate-level netlist 1 based on the chip information.

[0052] In a specific implementation, the chip information includes information inside the chip, including information about the chip IP. A synthesis tool is used to perform logic synthesis on the IP or the RTL of the entire chip to obtain a gate-level netlist 1 after synthesis.

[0053] Step S2: In the gate-level netlist 1 , cells 1 not covered by the security mechanism are obtained based on chip information and stored in the logic list 1 .

[0054] In some examples, step S2 includes: performing simulation error injection through VC_Z01X software to generate a diagnostic coverage report for gate-level netlist 1; and obtaining unit 1 based on chip information and the diagnostic coverage report and storing it in logic list 1, where unit 1 in logic list 1 is a unit not covered by the safety mechanism.

[0055] In specific implementations, fault injection simulation can be performed through dedicated software (such as Synopsys' VC_Z01X). This dedicated software is a high-performance fault injection and simulation solution for multiple purposes that meets the ISO 26262 automotive functional safety standard. By providing fault injection functions, the effectiveness of chip or IP error detection is ensured, and corresponding safety quality analysis reports can be provided. After fault injection simulation using this professional software, a diagnostic coverage report of the gate-level netlist 1 is generated.

[0056] The chip information also includes initial data of the functional safety of the chip. Data analysis is performed on the initial data and the diagnostic coverage report of the gate-level netlist 1, so as to extract the unit 1 not covered by the safety mechanism from the gate-level netlist 1, and store the unit 1 not covered by the safety mechanism in the logic list 1.

[0057] Step S3: In unit 1, based on preset conditions, obtain unit 2 that needs to insert redundant logic, and store it in logic list 2.

[0058] In some embodiments, step S3 includes: obtaining classification information, and identifying and classifying unit 1 based on the classification information. Based on preset conditions, selecting unit 2 that needs to insert redundant logic from the classified unit 1, and storing it in logic list 2. The preset conditions include the relationship between IP diagnostic coverage and IP area and target conditions.

[0059] In a specific implementation, the classification information is a classification rule of unit 1. First, a list of all units 1 is identified, and units 1 of the same type are classified into one category. For example, units 1 with the same clock are classified into one category.

[0060] In some examples, based on preset conditions, selecting the unit 2 that needs to be inserted with redundant logic from the classified units 1 may include selecting 50% from all the units 1 as the units 2 that need to be inserted with redundant logic when the step is first executed, and adjusting the proportion of the units 2 that need to be inserted with redundant logic to all the units 1 based on the relationship between the IP diagnostic coverage and the IP area and the target condition when returning to step S3 after the subsequent step S6 is executed. For example, a step value may be set, and when the IP diagnostic coverage is lower than the required value, 1%, 2%, 3%, 4%, 5% or 10% are additionally selected from all the units 1 as units 2 each time, etc.

[0061] Step S4: Obtain redundant logic cells of each unit 2 in logic list 2, insert redundant logic cells into unit 2, and integrate the redundant logic cells obtained based on unit 2 with gate-level netlist 1 storing unit 2 to generate gate-level netlist 2.

[0062] In some examples, such as Figure 2 As shown, step S4 includes:

[0063] Step S41 , obtaining the FPR value 1 of each cell 2 in the logic list 2 , and storing the cell name and the FPR value 1 of each cell 2 in a two-dimensional data lookup table.

[0064] Step S42, based on the traversal of the driving logic and load logic of each unit 2, the circuit of each unit 2 is obtained to form a corresponding virtual module, and the virtual module and other target units in the logic list 2 except the unit 2 included in the virtual module are stored in an independent database, for example, in the virtual module database (md_db) and the independent unit database (cl_db).

[0065] Among them, if unit 2 is stored in logical unit list 2, logical unit list 2 is (A, B, C, D, E), unit 2 that forms a virtual module is (A, B, C), which is stored in md_db, and the remaining unit 2 that does not form a virtual module is (D, E), which is an independent unit and is stored in cl_db.

[0066] In some examples, step S42 includes:

[0067] Step S421 , obtaining the driving logic of each unit 2 based on the virtual module, and calculating its FPR value 2 .

[0068] Step S422 , determining whether the FPR value 2 of each driving logic becomes smaller, if so, forming a new virtual module 2 based on the driving logic corresponding to the FPR value 2 and the virtual module.

[0069] Step S423, obtain the load logic of each unit 2 based on the virtual module, and calculate its FPR value 3.

[0070] Step S424 , determining whether the FPR value 3 of each load logic becomes smaller, if so, forming a new virtual module 3 based on the load logic corresponding to the FPR value 3 and the virtual module.

[0071] Step S43, obtaining a redundant logic unit based on the independent database.

[0072] Specifically, the calculation and traversal method for the functional safety penalty rate (FPR) of unit 2 (i.e., the target unit) and the corresponding virtual module is as follows. The calculation method for obtaining the FPR value 1 of unit 2 is as follows Figure 3a As shown in the figure, for the target unit U1, the input number (Input Number): M = 2, the output number (Output Number): N = 1, the gate cell number (Cell gates): C = 1, the Xor gate number (Xor Gates Number): X = N = 1, the or gate number (Or GatesNumber): O = N-1 = 0, FPR = (X + O) / C = 100%. The FPR value of unit 2 and the corresponding unit name are stored in the two-dimensional data lookup table (cl_lookup_table).

[0073] The first step in calculating the virtual module of unit 2 is as follows Figure 3b As shown, further drive logic (such as Figure 3b ) / load logic (not shown in the figure), Input Number: M = 3, Output Number: N= 1, Cell Gates Number: C = 2, Xor Gates Number: X = N = 1, Or Gates Number: O = N-1 = 0, FPR = (X + O) / C = 50%. The target unit U1 and the logic unit form new virtual modules 2 and 3.

[0074] This FPR value of 50% is less than the FPR value of 1 (100%) for unit 2. Therefore, if Figure 3cAs shown in the figure, continue to capture further driving logic, Input Number: M = 2, Output Number: N = 1, Cell Gates Number: C = 2.5, Xor Gates Number: X = N = 1, Or Gates Number: O = N-1 = 0, FPR = (X + O) / C = 40%. Add this new logic cell to the virtual module in the previous step to form a new virtual module 2.

[0075] The FPR value of 40% is less than the FPR value of the previous step (50%). Figure 3d As shown, continue to capture further driving logic, input number (Input Number): M = 4, output number (Output Number): N= 2, cell gate number (Cell Gates Number): C = 4, Xor Gates Number: X = N = 2, or gate number (Or Gates Number): O = N-1 = 1, FPR = (X + O) / C = 75%.

[0076] The FPR value of 75% is greater than the FPR value of the previous step (40%). Therefore, the iteration is stopped and the data is stored. Figure 3c The virtual module shown is used as the virtual module corresponding to the final unit 2.

[0077] For each unit 2, the drive logic and load logic are captured respectively and the corresponding FPR value is calculated and compared with the previous FPR value (the first FPR value with unit 2). If the FPR value is less than the previous FPR value, that is, the FPR value is optimized, the logic unit is retained to obtain a new virtual module until the FPR value deteriorates, and the boundary is divided, and the unit list and FPR value are stored in a new database (md_driver_db). At the same time, continue to capture the drive logic forward or continue to capture the load logic backward, and complete the FPR value calculation and comparison, boundary division and data storage. Until the drive circuit in the entire virtual module is traversed. Among them, the virtual module 2 and the corresponding FPR value 2 formed after the iteration of the drive logic module can be stored in the new drive database (md_driver_db). The virtual module 3 and the corresponding FPR value 3 formed after the iteration of the load logic module can be stored in the new load database (md_load_db). Until the drive circuit and load circuit in the entire virtual module are traversed.

[0078] The remaining target cells in the above virtual module and logic list 2 except the cell 2 included in the virtual module are stored in the virtual module database (md_db) and the independent cell database (cl_db).

[0079] Based on the virtual modules and independent units generated above, the generation of redundant logic units and verification logic in the final redundant logic unit is completed, and the integration of the redundant logic units and verification logic with the original design is completed.

[0080] Step S5: Determine whether the functions of gate-level netlist 1 and gate-level netlist 2 are consistent, if they are consistent, execute step S6.

[0081] In a specific implementation, determining whether the functions of gate-level netlist 1 and gate-level netlist 2 are consistent may include a logic equivalence check to ensure that adding redundant units has no impact on the functions of the original design.

[0082] In other implementations, the redundant logic unit list and the corresponding original logic list generated by the above method can be provided to a placement and routing tool to implement optimization guidance at the physical level.

[0083] In other embodiments, the redundant logic unit list generated by the above method can be used to quickly check circuit connectivity and functional paths.

[0084] In other embodiments, the method includes performing fault injection simulation on the gate-level netlist 2 generated by the method through software (such as Z01X of Synopsys) to verify the effectiveness of the added error detection redundant logic.

[0085] Step S6: Obtain the IP diagnostic coverage and IP area in the gate-level netlist 2, and determine whether the IP diagnostic coverage reaches a preset coverage and whether the IP area reaches a preset area. If at least one of the conditions is not met, return to step S3.

[0086] In specific implementation, the IP diagnostic coverage in gate-level netlist 2 can be obtained through software (such as Synopsys's Z01X). Ensure that its diagnostic coverage meets the required functional safety standards and that the area overhead meets the standards. If the software evaluation results show that the diagnostic coverage does not match the product definition, return to step S3. If the diagnostic coverage is better than the coverage defined by the safety goal, evaluate whether it is necessary to reduce the diagnostic coverage to improve area optimization. If the diagnostic coverage is lower than the coverage defined by the safety goal, re-evaluate the logic table, add logic groups to continue optimizing the system redundancy solution, and repeat steps S3-S6 until the defined safety goal is met.

[0087] This solution can not only enable IP or chips to achieve different functional safety goals, but also optimize area overhead as much as possible.

[0088] In actual applications, the structure of the IP after inserting redundant logic through this solution is as follows Figure 4 As shown. Figure 4 , which shows the structure diagram of adding redundant logic to the logic block. The upper part of the figure shows the original logic of the IP, and the lower part of the figure shows the insertion of redundant functions into the original logic block of the IP. After the redundant logic is inserted, the function of the original IP should not be changed, and the verification result should be consistent with the original IP function.

[0089] like Figure 5 As shown, for the logic block, there is a set of inputs (IN1-INn) and a set of outputs (OUT1-OUTm). At the same time, for the redundant logic, there is also a set of inputs (IN1-INn) and a set of outputs (CHK_OUT1-CHK_OUTm). The process implemented in this solution performs redundancy check on the path from data input to data output, thereby improving the diagnostic coverage of IP.

[0090] Each group of outputs of the logic block (OUT1-OUTm) is XORed with the outputs of the redundant logic (CHK_OUT1-CHK_OUTm). The final result is logically ORed to obtain the final check result (check error). When the signal is high, it means that the logic block or redundant logic has a hardware failure.

[0091] In summary, the method for improving diagnostic coverage provided by the embodiment of the present invention can significantly improve the diagnostic coverage of existing IP by inserting redundant structures in the gate-level netlist. It can also avoid repeated development of functional IP, reduce development costs, and improve development efficiency. By continuously optimizing between diagnostic coverage and area cost, the area cost caused by functional safety can be minimized.

[0092] Furthermore, the present application also provides a device for improving the diagnostic coverage, such as Figure 6 As shown, the device 10 for improving diagnostic coverage includes: an acquisition module 11, a verification processing module 12 and a detection module 13.

[0093] The acquisition module 11 is used to execute step S1: acquire chip information, and obtain a gate-level netlist 1 based on the chip information; step S2: in the gate-level netlist 1, acquire a unit 1 not covered by the security mechanism based on the chip information and store it in a logic list 1; step S3: in the unit 1, acquire a unit 2 that needs to insert redundant logic based on a preset condition and store it in a logic list 2;

[0094] The verification processing module 12 is used to execute step S4: obtain the redundant logic unit of each unit 2 in the logic list 2, insert the redundant logic unit into the unit 2, and integrate the redundant logic unit obtained based on the unit 2 with the gate-level netlist 1 storing the unit 2 to generate a gate-level netlist 2;

[0095] The detection module 13 is used to execute step S5: determine whether the functions of gate-level netlist 1 and gate-level netlist 2 are consistent, if they are consistent, execute step S6; step S6: obtain the IP diagnostic coverage and IP area in gate-level netlist 2, and determine whether the IP diagnostic coverage reaches the preset coverage and whether the IP area reaches the preset area. If at least one of the conditions is not met, return to step S3.

[0096] The device for improving diagnostic coverage provided in the present application can implement any embodiment of the method for improving diagnostic coverage described above.

[0097] Furthermore, the present application also provides an automotive chip, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the task scheduling method in any of the above embodiments when executing the computer program.

[0098] Furthermore, the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the task scheduling method in any of the above embodiments are implemented.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for improving diagnostic coverage at the gate-level netlist stage, characterized in that: include: Step S1: Obtain chip information, and obtain a gate-level netlist 1 based on the chip information; Step S2: in the gate-level netlist 1, obtaining the unit 1 not covered by the security mechanism based on the chip information and storing it in the logic list 1; Step S3: in the unit 1, based on preset conditions, obtaining the unit 2 that needs to insert redundant logic and storing it in the logic list 2; Step S4: obtaining the redundant logic units that need to be inserted into each of the units 2 of the logic list 2, and inserting the redundant logic units into each of the units 2, and integrating them to generate a gate-level netlist 2; Step S5: Determine whether the functions of the gate-level netlist 1 and the gate-level netlist 2 are consistent, if they are consistent, execute step S6; Step S6: Obtain the IP diagnostic coverage and IP area in the gate-level netlist 2, and determine whether the IP diagnostic coverage reaches a preset coverage and whether the IP area reaches a preset area. If at least one of the conditions is not met, return to step S3; The step S4 comprises: Step S41, obtaining the FPR value 1 of each of the cells 2, and storing the cell name and the FPR value 1 of each of the cells 2 in a two-dimensional data lookup table; Step S42, based on the traversal of the driving logic and the load logic of each of the units 2, the circuit of each of the units 2 is obtained to form a corresponding virtual module, and the virtual module and other units in the logic list 2 except the unit 2 included in the virtual module are stored in an independent database; Step S43, obtaining the redundant logic unit based on the independent database; Among them, the FPR value is the functional safety penalty rate of the unit 2 and the corresponding virtual module, FPR= (X + O) / C, X is the number of XOR gates, O is the number of OR gates, and C is the number of gate units.

2. The method for improving diagnostic coverage at the gate-level netlist stage according to claim 1, characterized in that: The step S2 comprises: Performing simulation error annotation by VC_Z01X software to generate a diagnostic coverage report for the gate-level netlist 1; Based on the chip information and the diagnostic coverage report, the unit 1 is obtained and stored in the logic list 1.

3. The method for improving diagnostic coverage at the gate-level netlist stage according to claim 1, characterized in that: The step S3 comprises: Acquiring classification information, and identifying and classifying the unit 1 based on the classification information; Based on the preset condition, the unit 2 into which redundant logic needs to be inserted is selected from the classified unit 1, and stored in the logic list 2; Among them, the preset conditions include the IP diagnostic coverage and the relationship between the IP area and the target conditions.

4. The method for improving diagnostic coverage at the gate-level netlist stage according to claim 1, characterized in that: The step S42 comprises: Step S421, obtaining the driving logic of each of the units 2 based on the virtual module, and calculating its FPR value 2; Step S422, determining whether the FPR value 2 of each of the driving logics becomes smaller, and if so, forming a new virtual module 2 based on the driving logic corresponding to the FPR value 2 and the virtual module; Step S423, obtaining the load logic of each of the units 2 based on the virtual module, and calculating its FPR value 3; Step S424 , determining whether the FPR value 3 of each load logic becomes smaller, and if so, forming a new virtual module 3 based on the load logic corresponding to the FPR value 3 and the virtual module.

5. The method for improving diagnostic coverage at the gate-level netlist stage according to claim 1, characterized in that: In the step S6, simulation error injection is performed by using VC_Z01X software to obtain the IP diagnostic coverage in the gate-level netlist 2.

6. A device for improving diagnostic coverage at the gate-level netlist stage, characterized in that: include: An acquisition module, used to execute step S1: acquire chip information, and obtain a gate-level netlist 1 based on the chip information; Step S2: in the gate-level netlist 1, based on the chip information, obtain the unit 1 not covered by the security mechanism and store it in the logic list 1; Step S3: in the unit 1, based on the preset conditions, obtain the unit 2 that needs to insert redundant logic and store it in the logic list 2; The verification processing module is used to execute step S4: obtain the redundant logic unit that needs to be inserted into each unit 2 in the logic list 2, and insert the redundant logic unit into the unit 2, and integrate to generate a gate-level netlist 2; The step S4 comprises: step S41, obtaining the FPR value 1 of each of the units 2, and storing the unit name and FPR value 1 of each of the units 2 in a two-dimensional data lookup table; step S42, based on the traversal of the driving logic and load logic of each of the units 2, obtaining the circuit of each of the units 2 to form a corresponding virtual module, and the virtual module and other units in the logic list 2 except the unit 2 included in the virtual module are stored in an independent database; step S43, obtaining the redundant logic unit based on the independent database; wherein the FPR value is the functional safety penalty rate of the unit 2 and the corresponding virtual module, FPR= (X + O) / C, X is the number of XOR gates, O is the number of OR gates, and C is the number of gate units; The detection module is used to execute step S5: determine whether the functions of the gate-level netlist 1 and the gate-level netlist 2 are consistent, and if they are consistent, execute step S6; step S6: obtain the IP diagnostic coverage and IP area in the gate-level netlist 2, and determine whether the IP diagnostic coverage reaches the preset coverage and whether the IP area reaches the preset area. If at least one of the conditions is not met, return to step S3.

7. An automotive chip, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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