ECG classification detection convolutional neural network coprocessor based on RISC-V

Abstract

The invention discloses an RISC-V-based ECG classification detection convolutional neural network coprocessor, and belongs to the technical field of calculation, reckoning or counting. The core of the method is the design of an RISC-V architecture accelerator platform for ECG classification detection convolution. Meanwhile, the invention relates to a coprocessor instruction system design based on NICE, so that data exchange aiming at ECG classification detection can be better carried out. The RISC-V architecture accelerator platform design comprises design optimization of each sub-module such as a state processing unit, a memory controller, a weight cache, an input / output buffer area, an input register, an output register, a PE array, activation and pooling. According to the method, a one-dimensional CNN efficient processing structure for ECG detection signal features is successfully realized, and the execution efficiency of a convolutional neural network coprocessor for ECG classification detection is improved in combination with an RISC-V extension instruction for ECG data convolution.

Description

Technical Field

[0001] The present invention relates to the field of coprocessors, and more specifically discloses a RISC-V-based ECG classification detection convolutional neural network coprocessor, which belongs to the technical field of calculation, inference or counting. Background Art

[0002] How to correctly use electrocardiogram (ECG) for clinical diagnosis of arrhythmia is of great significance.

[0003] Convolutional Neural Networks (CNN) are widely used in classification tasks in various fields, such as image recognition, speech recognition, etc., because of their wide learning ability and stability. CNN has many advantages for recognition tasks, but there are still many restrictions on deploying CNN models to wearable devices with limited computing resources and memory space. Given that CNN has good and stable classification characteristics, designing a one-dimensional convolutional neural network system specifically for ECG classification detection has important practical significance and broad application prospects.

[0004] However, CNN still has some inherent defects. First, conventional operations generally use 32-bit floating-point numbers, so if there are a large number of floating-point operations, a lot of power consumption will be consumed; secondly, saving the CNN model requires a lot of memory space, and the neural network model generally takes up a large space. These inherent defects make CNN have the defect of high power consumption when used for ECG classification. In order to overcome the inherent defects of CNN, the prior art proposes an accelerator for ECG classification detection. The existing accelerators for ECG classification detection are still insufficient in terms of computing efficiency and adaptability; the existing accelerators for ECG classification detection usually adopt a general CNN accelerator architecture, so the efficiency is low when processing one-dimensional convolution, resulting in high power consumption and large delay; the general CNN accelerator architecture cannot adapt well to the characteristics of ECG signals, and the classification accuracy and stability are insufficient; the accelerator for ECG classification detection has a low degree of integration with other components of the system, resulting in the inability to fully exert the overall performance.

[0005] Therefore, the present invention aims to propose a RISC-V-based ECG classification detection convolutional neural network coprocessor to overcome the defects of the accelerator for ECG classification detection. Summary of the invention

[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned background technology and provide a RISC-V-based ECG classification detection convolutional neural network coprocessor. The invention aims to integrate a specially designed RISC-V extended instruction set based on the characteristics of ECG signals to achieve the purpose of improving the execution efficiency of the one-dimensional convolutional neural network coprocessor, and solve the technical problems of low computational efficiency, poor adaptability and low system integration of existing ECG classification detection accelerators.

[0007] The present invention adopts the following technical solutions to achieve the above-mentioned invention object:

[0008] A RISC-V-based ECG classification detection convolutional neural network coprocessor, comprising: a state processing unit, a memory controller, a weight cache, an input / output buffer, an input register, a PE array, an output register, an activation module and a pooling module; the state processing unit is used to control the coprocessor forward reasoning and the convolution calculation in the forward reasoning process; the memory controller receives the ECG signal, weight and network parameters from the main processor, calculates and generates the storage address of the ECG signal, weight and network parameters, enables the weight cache, the input / output buffer, the input register, the PE array, the output register, the activation module and the pooling module; the weight cache is used to cache the weights of each layer of the neural network; the input / output buffer, used to cache the ECG signal from the main processor and the ECG input feature map of each layer of convolution operation completed by the PE array; input register, used to cache the ECG input feature map of each layer of convolution operation completed by the PE array; PE array, used to pulsate the ECG input feature map of the current layer of convolution operation, read the current layer weight from the weight cache, and output the current layer of convolution result; output register, used to cache the current layer of convolution result output by the PE array; activation module, used to activate the current layer of convolution result output by the PE array; pooling module, used to perform pooling operation on the activation data of the current layer of convolution result, and obtain the ECG input feature map of the next layer of convolution operation completed by the PE array.

[0009] As a further optimization scheme of a RISC-V-based ECG classification detection convolutional neural network coprocessor, the state processing unit includes a main state machine and a computing state machine; the main state machine is used to control the coprocessor to work in a loop process including an idle state, a parameter acquisition state, and a forward reasoning state; the computing state machine controls the PE array to complete a layer of convolution operation when the coprocessor works in the forward reasoning state.

[0010] As a further optimization solution for the RISC-V-based ECG classification detection convolutional neural network coprocessor, the memory controller receives ECG signals, weights and network parameters from the main processor through the NICE protocol.

[0011] As a further optimization solution for the RISC-V-based ECG classification detection convolutional neural network coprocessor, the memory controller receives the ECG signal, weights and network parameters from the main processor through the NICE protocol. Specifically, the ECG signal, weights and network parameters from the main processor are loaded into the row data cache through the lbuf instruction; the data in the row data cache is accumulated through the rowsum instruction, and the accumulated value is returned to the main processor; the data in the row data cache is stored in the main processor memory through the sbuf instruction.

[0012] As a further optimization solution for the RISC-V-based ECG classification and detection convolutional neural network coprocessor, the ECG signals, weights and network parameters from the main processor are transmitted by controlling the maximum bit width of the two registers, and the signals of the two registers transmitting data are controlled by calling a custom instruction set.

[0013] As a further optimization scheme of the RISC-V-based ECG classification detection convolutional neural network coprocessor, the first column of the PE array receives the ECG signal from the main processor or the ECG input feature map of the current layer convolution operation, and the data received by the first column of the PE array is pulsatingly input to each column of the PE array in turn, and the first row of the PE array receives the current layer weight, and each column of the PE array shares the current layer weight received by the first row of each column, and the calculation results of each column of the PE array are transmitted to the first row output.

[0014] As a further optimization solution for the RISC-V-based ECG classification detection convolutional neural network coprocessor, the weight cache is an on-chip cache containing 8 banks; the input / output buffer is an on-chip cache consisting of 2 SRAMs, each of which contains 8 banks.

[0015] As a further optimization solution for the RISC-V-based ECG classification detection convolutional neural network coprocessor, the input register multiplexes the ECG input feature map data of each layer of convolution operation completed by the PE array; the output register multiplexes the output of the current layer of convolution results output by the PE array, including writing, shifting and filling.

[0016] As a further optimization scheme for the RISC-V-based ECG classification detection convolutional neural network coprocessor, the activation module truncates the current layer convolution result output by the PE array.

[0017] As a further optimization solution for the RISC-V-based ECG classification detection convolutional neural network coprocessor, the pooling module performs maximum pooling on the activation data of the current layer convolution result.

[0018] The present invention adopts the above technical solution and has the following beneficial effects:

[0019] (1) The present invention combines the RISC-V architecture accelerator platform with the NICE custom instruction system, designs a one-dimensional CNN efficient processing structure for ECG detection signal characteristics, and forms a complete set of coprocessor and system design. This system not only supports efficient convolution calculations, but also can handle complex ECG classification tasks, and has strong practicality and broad application prospects.

[0020] (2) The present invention designs a systolic array processing unit for ECG data convolution, which reduces memory bottlenecks and increases data throughput, while also improving detection accuracy and processing speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a hardware architecture diagram of the ECG classification detection convolutional neural network coprocessor proposed in the present invention.

[0022] Figure 2 This is a schematic diagram of loading data into the PE array in the convolutional neural network coprocessor for ECG classification detection proposed in the present invention. DETAILED DESCRIPTION

[0023] The following is a detailed description of the RISC-V-based ECG classification detection convolutional neural network co-processing of the present invention with reference to the accompanying drawings and specific embodiments of the specification.

[0024] Embodiment 1: As attached Figure 1 , this embodiment provides a RISC-V-based ECG classification detection convolutional neural network coprocessor, which is implemented by the design of a RISC-V architecture accelerator platform for ECG classification detection convolution. The accelerator platform integrates a specially designed RISC-V extended instruction set, so that the one-dimensional convolutional neural network can be efficiently executed at the hardware level. The RISC-V extended instruction set provides hardware support for key operations such as convolution, activation function, and pooling operations, so that these operations can be executed with low latency and high parallelism in the PE array. The design of the RISC-V architecture accelerator platform for ECG classification detection convolution includes optimization of the state processing unit, memory controller, weight cache, input / output buffer, input register, output register, PE array, activation module and pooling module.

[0025] The state processing unit is used to control the working state of the accelerator. It consists of two state machines: the main state machine and the computing state machine. The computing state machine is controlled by the main state machine to control the convolution calculation process. The main state machine controls the forward reasoning of the accelerator as a whole. When it enters the CONV_CAL state, it will enter the computing state to perform convolution calculations and activate pooling operations. The state change process of the main state machine is: the initial state is the IDLE idle state, and waits for parameter acquisition; after obtaining the parameter address, wait for the ECG signal to be loaded into the input / output buffer through the memory controller, and save the weight data of all network layers to the weight cache. After the preparation work is completed, the accelerator starts the reasoning calculation, the computing state machine starts, and controls the accelerator to read and write data and perform convolution calculations on the current layer. During this period, the main state machine will determine whether the current layer has been calculated. If the current layer has been calculated and is not the last layer, it will continue to loop the reasoning of the next layer until the ECG detection classification result is output. The calculation state machine represents the calculation process of each layer. Since a feature data graph requires multiple batches of convolution calculations, the state machine loops multiple convolution calculations in the OR_CAL state until the entire convolution layer is completed. The state transition process of the calculation state machine is: the default is the IDLE idle state, then enters the weight loading state, and determines whether the weights are loaded; after the weights are loaded, enter the calculation state, otherwise continue to maintain the OR_FT_WT state; enter the convolution calculation state, it will continuously determine whether the current layer convolution calculation is completed, and enter the calculation end state if it is completed, otherwise continue to maintain the OR_CAL state, and after the current layer convolution calculation is completed, return to the IDLE state and wait for the next cycle.

[0026] The memory controller uses the Memory_Ctrl terminal to receive ECG signals from the CPU through NICE, controls the reading of different data including feature maps, current layer weights and network parameters and transmits them to input registers, PE arrays, and weight caches, and is also responsible for enabling each module. Specific functions include: a. Read SPI input ECG data; b. Read network layer configuration parameters; c. Read network layer weights; d. Calculate the input / output buffer address; e. Calculate the input / output buffer write input register address.

[0027] The on-chip cache includes weight cache and input / output buffer, which are mainly used to store weight data and feature map data, which occupy the main part. The weight cache and input / output buffer are divided into 8 banks for parallel output data to improve efficiency, as follows:

[0028] (a) The weight cache consists of 8 banks, each of which is 2048 bytes in size. The 8 input and output ports are used to receive and output weight values ​​in a certain order, for example, the systolic array outputs them in sequence and there is a clock cycle difference between adjacent banks. The weight values ​​are output to the PE array for calculation;

[0029] (b) The input / output buffer consists of two 4096*8-bit SRAMs, each with 8 banks. The 8 input and output ports provided by the 8 banks are used to receive the original ECG signal and the convolution operation results of each layer output by the output register, and output the data in the SRAM to the input register at the same time. The two SRAMs are used for ping-pong operation to improve the operation efficiency.

[0030] The input / output buffer involves data input and output, where data input is generated by the Pooling2IOB module. Each time, Bm(8) data is written in the format of map. It is controlled only by the Pooling2IOB module, and the write address is generated by the memory controller. The order of data input is: output the first part of Map0, output the first part of Map1, output the first part of Map2, and so on until the first part of MapN is output; then start the second part of the output Map data input; repeat the above operation until all output Maps are written, and the data is output to the input register. Each time, ceil(Hu / Bm) clocks of data are transmitted, and Bm data are output in the format of map. The order of data output is: (1) output the first part of InMap0, output the first part of InMap1, output the first part of InMap2, and so on until the first part of InMapN is output; (2) output the second parts of InMap0~M in sequence, repeat ceil(Hu / Bm) times; (3) repeat the operation; (4) until the transmission of all parts of InMap is completed.

[0031] The input register is used to cache all input data used by the systolic array in the next calculation, and plays the role of data input multiplexing. At the same time, there is a situation where the convolution kernel size K> the convolution kernel step size S. Using the input register can avoid repeated access to the on-chip cache. At the same time, the register stack of the input register can also achieve parallel output, thereby satisfying the subsequent PE array calculation process. The data required for one calculation of the PE array is extracted from the input buffer.

[0032] Where Hu is the number of input data involved in one calculation of the systolic array, which is related to the convolution kernel size K of the current layer, the convolution kernel step size S and the number of feature map input ports R of the PE array. Here, the size of the PE array is R*C=16*8. The calculation formula of Hu is as follows:

[0033] Hu= (R - 1) × S + K (1)

[0034] At the same time, according to the neural network parameters in Table 1, the size of each layer of convolution operation Hu can be obtained, thereby determining the size of the register stack in the input register to improve resource utilization, and finally determining the input register size, as shown in Table 2.

[0035] Layer Name CONV1 CONV2 CONV3 CONV4 CONV5 CONV6 GAP Dense Input feature map size 3600 894 220 105 48 22 10 1 Input feature map 1 8 16 32 64 64 72 72 Output feature map size 1793 442 213 98 45 20 1 1 Output feature map 8 16 32 64 64 72 72 17 Convolution kernel size 16 12 8 8 4 3 - - Convolution kernel step size 2 2 1 1 1 1 - - Pooling size 7 4 5 4 2 2 - - Pooling step size 2 2 2 2 2 2 - - Number of weights 128 1536 4096 16384 16384 13824 - 1241 Number of multiply-add operations 445K 1301K 1636K 3011K 1290K 461K - -

[0036] Table 1 Neural network parameters

[0037] Network layer index Hu Input regfile size (bytes) 1(conv1) 46 46 2(conv2) 42 42 3(conv3) 23 23 4(conv4) 19 19 5(conv5) 19 19 6(conv6) 18 18 7(GAP) 160 160 8(dense) 72 72

[0038] Table 2 Input regfile size of different network layers

[0039] The output register allows the convolution output of each layer to be input to the pooling module in order, which plays the role of output multiplexing. The first layer POOL_K=7, POOL_S=2 is used for explanation.

[0040] It is mainly divided into three steps. Process 1 is mainly data writing. Because the maximum pooling size is 7, the register stack size of the output register is set to 7. The output data of the PE array is sorted according to the maximum pooling bit width of 7, and 7*8bit data is stored each time. Once 7 data are filled, they are output and the remaining bits are filled with zeros; Process 2 is shifting. After the number is output in process 1, it is necessary to provide empty spaces for the following data in time. Therefore, all the data in the output register is shifted right by 2 units as a whole. At this time, the data is not filled, so it is not output; Process 3 is filling. The output value of the PE array continues to be written in the empty space after the shift. Once 7 data are filled, it is output.

[0041] The PE array contains a total of 128 PE units, arranged in a rectangular shape of 16 rows and 8 columns. The first column of PE receives 16-bit parallel ECG signals or input data, and pulses in from left to right in sequence; the first row of PE receives weight data, and the weight data does not pulse, but the PE units in the same column share the same weight, as shown by the green line. At the same time, the weight data flow of each column is received at an interval of one clock cycle, as shown by the blue line; the final calculation result data flow is passed from bottom to top to the first row of outputs, and each column output is separated by one clock cycle, as shown by the red line, and each column will eventually have 16 outputs. The specific process is as follows Figure 2 shown.

[0042] In the activation module, Relu is used as the activation function, and the output of the PE array is truncated. There are two activation modes [0:2] and [0:1], that is, if it is greater than the upper limit, the upper limit is taken, if it is less than the lower limit, the lower limit is taken, and in the region, the region itself is taken. The first two layers use the [0:2] mode, and the last four layers use the [0:1] mode. The pooling module uses the maximum pooling method to take the maximum result among P.

[0043] Embodiment 2: This embodiment designs a coprocessor instruction system based on NICE. The inline assembly syntax asm volatile("instructions") in C / C++ is used to embed assembly in the C code, and the lbuf, sbuf, and rowsum instructions are modified to pass in the convolution parameters. ECG classification detection is implemented using a convolutional neural network, which mainly includes convolution, activation, pooling, and fully connected layers. The coprocessor loads data from the main processor memory to the row data cache through the lbuf instruction, stores the data in the row data cache to the main processor memory through the sbuf instruction, and implements the row accumulation operation through the rowsum instruction, and returns the accumulated value to the main processor memory. The coprocessor responds to these instructions and realizes the efficient transmission and calculation functions of the convolution layer parameters during the CNN calculation process.

[0044] Specifically, in order to make full use of the register width, the coprocessor's custom instruction set uses two registers, rs1 and rs2, to pass CNN-related parameters. Since each register is 32 bits, the maximum width of the parameters passed in at one time is only 64 bits, so we only need to transfer each layer of parameters twice. In order to ensure efficient convolution calculations, the system completes the transmission and control of parameters through 4 specific signals:

[0045] ·nice_req_rs1[1:0]==2'b00 is a control signal;

[0046] ·nice_req_rs1[1:0]==2'b01 is configuration signal 1;

[0047] ·nice_req_rs1[1:0]==2'b10 is configuration signal 2;

[0048] ·nice_req_rs1[1:0]==2'b11 is the end signal.

[0049] In the calculation of each convolution layer, the system transmits parameters through the rs1 and rs2 registers, and passes each parameter to the coprocessor according to the requirements of the hierarchy and convolution operation. This design based on custom instructions not only optimizes the convolution operation of CNN at the hardware level, but also effectively reduces the data transmission time, thereby improving the overall system computing efficiency.

[0050] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above specific embodiments. The above specific embodiments and the description in the specification are only for further illustrating the principles and preparation effects of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A RISC-V-based ECG classification detection convolutional neural network coprocessor, characterized in that: include: A state processing unit, used to control the coprocessor forward reasoning and the convolution calculation during the forward reasoning process; A memory controller receives ECG signals, weights and network parameters from the main processor, calculates and generates storage addresses of ECG signals, weights and network parameters, enables weight cache, input / output buffer, input register, PE array, output register, activation module and pooling module; Weight cache, used to cache the weights of each layer of the neural network; Input / output buffer, used to cache ECG signals from the main processor and ECG input feature maps of each layer of convolution operation completed by the PE array; Input register, used to cache the ECG input feature map of each layer of convolution operation completed by the PE array; PE array, used to pulse transmit the ECG input feature map of the current layer convolution operation, read the current layer weight from the weight cache, and output the current layer convolution result; Output register, used to cache the current layer convolution result output by the PE array; The activation module is used to activate the convolution result of the current layer output by the PE array; and, The pooling module is used to perform pooling operations on the activation data of the current layer convolution result and obtain the ECG input feature map of the PE array to complete the next layer of convolution operation.

2. According to the RISC-V-based ECG classification detection convolutional neural network coprocessor of claim 1, it is characterized in that: The state processing unit includes a main state machine and a computing state machine; the main state machine is used to control the coprocessor to work in a loop process including an idle state, a parameter acquisition state, and a forward reasoning state; the computing state machine controls the PE array to complete a layer of convolution operation when the coprocessor works in the forward reasoning state.

3. According to the RISC-V-based ECG classification detection convolutional neural network coprocessor of claim 2, it is characterized in that: The memory controller receives ECG signals, weights and network parameters from the main processor via the NICE protocol.

4. According to the RISC-V-based ECG classification detection convolutional neural network coprocessor of claim 3, it is characterized in that: The memory controller receives the ECG signal, weight and network parameters from the main processor through the NICE protocol, specifically: loads the ECG signal, weight and network parameters from the main processor into the row data cache through the lbuf instruction; performs accumulation operation on the data in the row data cache through the rowsum instruction, and returns the accumulated value to the main processor; The data in the row data buffer is stored to the main processor memory through the sbuf instruction.

5. The RISC-V-based ECG classification detection convolutional neural network coprocessor according to claim 4, characterized in that: The ECG signals, weights and network parameters from the main processor are transmitted by controlling the maximum bit width of the two registers, and the signals of the two registers transmitting data are controlled by calling a custom instruction set.

6. The RISC-V-based ECG classification detection convolutional neural network coprocessor according to claim 5, characterized in that: The first column of the PE array receives the ECG signal from the main processor or the ECG input feature map of the current layer convolution operation. The data received by the first column of the PE array is pulsatingly input to each column of the PE array in sequence. The first row of the PE array receives the current layer weight. Each column of the PE array shares the current layer weight received by the first row of each column. The calculation results of each column of the PE array are transmitted to the first row for output.

7. A RISC-V-based ECG classification detection convolutional neural network coprocessor according to any one of claims 1 to 6, characterized in that: The weight cache is an on-chip cache including 8 banks; the input / output buffer is an on-chip cache consisting of 2 SRAMs, each of which includes 8 banks.

8. A RISC-V-based ECG classification detection convolutional neural network coprocessor according to any one of claims 1 to 6, characterized in that: The input register performs input multiplexing on the ECG input feature map data of each layer of convolution operation completed by the PE array; the output register performs output multiplexing including writing, shifting and filling on the current layer convolution result output by the PE array.

9. A RISC-V-based ECG classification detection convolutional neural network coprocessor according to any one of claims 1 to 6, characterized in that: The activation module performs truncation processing on the current layer convolution result output by the PE array.

10. A RISC-V-based ECG classification detection convolutional neural network coprocessor according to any one of claims 1 to 6, characterized in that: The pooling module performs maximum pooling processing on the activation data of the current layer convolution result.

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