Fuse unit detection method and test equipment

Abstract

The invention provides a fuse unit detection method and test equipment. The fuse unit detection method comprises the steps that a fuse unit array is read at a first temperature, first data are acquired, and the fuse unit array comprises a plurality of fuse units; reading the fuse unit array at a second temperature to obtain second data, the second temperature being lower than the first temperature; when the second data is not equal to the first data, determining a fuse unit to be processed according to a comparison result of the first data and the second data; and repairing the fuse unit to be processed at the second temperature. According to the embodiment of the invention, the reliability of the memory chip can be improved.

Description

Background Art

[0002] An electronic fuse (E-fuse) unit (hereinafter referred to as a fuse unit) is a one-time programmable device with two states: blown and unblown. In the default state, the fuse unit is in an unblown state, and after burning, the fuse unit is in a blown state. In DRAM, electronic fuse units are arranged in rows and columns, which is called a fuse unit array. Some fuse unit arrays can be used to pre-write DRAM factory information data, and other fuse unit arrays can be used to provide spare storage units for replacement when a storage unit in the DRAM fails.

[0003] During the use of the fuse cell array, different data may be read due to different temperatures. As a spare memory cell to replace the failed memory cell, this unreliability poses a great challenge to the yield of DRAM.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a fuse unit detection method and a test device, which are used to solve the problem that an electronic fuse unit array becomes abnormal with temperature changes.

[0006] According to a first aspect of an embodiment of the present disclosure, a fuse unit detection method is provided, comprising: reading a fuse unit array at a first temperature to obtain first data, the fuse unit array comprising a plurality of fuse units; reading the fuse unit array at a second temperature to obtain second data, the second temperature being lower than the first temperature; when the second data is not equal to the first data, determining a fuse unit to be processed according to a comparison result of the first data and the second data; and repairing the fuse unit to be processed at the second temperature.

[0007] In an exemplary embodiment of the present disclosure, reading the fuse cell array at the second temperature includes: reading the fuse cell array a first preset value of times to obtain a first preset value of sub-data; and performing a bitwise AND operation on the first preset value of sub-data to obtain second data.

[0008] In an exemplary embodiment of the present disclosure, determining a fuse unit to be processed based on a comparison result of first data and second data includes: performing a bit-by-bit comparison on the second data and the first data; when the nth bit of the second data is equal to a first value and the nth bit of the first data is equal to a second value, determining the fuse unit corresponding to the nth bit as the fuse unit to be processed, the first value corresponds to an unblown state of the fuse unit, and the second value corresponds to a blown state of the fuse unit.

[0009] In an exemplary embodiment of the present disclosure, determining the fuse unit to be processed based on the comparison result of the first data and the second data includes: performing a bitwise XOR operation on the second data and the first data to obtain a detection value; determining one or more target bits where the value 1 in the detection value is located; and determining the fuse unit corresponding to the one or more target bits as the fuse unit to be processed.

[0010] In an exemplary embodiment of the present disclosure, determining a fuse unit to be processed based on a comparison result of first data and second data includes: calculating a difference between the first data and the second data; determining one or more target bits where a value 1 is located based on the difference; and determining fuse units corresponding to the one or more target bits as fuse units to be processed.

[0011] In an exemplary embodiment of the present disclosure, repairing the fuse unit to be processed at the second temperature includes: re-blowing the fuse unit to be processed at the second temperature; re-reading the fuse unit to be processed; and determining that the repair is completed when all the fuse units to be processed are in a blown state.

[0012] In an exemplary embodiment of the present disclosure, re-blowing the fuse unit to be processed at the second temperature includes: blowing the fuse unit to be processed a second preset value of times at the second temperature, and the second preset value is greater than two.

[0013] In an exemplary embodiment of the present disclosure, repairing the fuse unit to be processed at the second temperature includes: when at least one fuse unit to be processed is in an unblown state, marking the unblown fuse unit to be processed as a fuse unit to be replaced; setting the fuse unit to be replaced to fail, and selecting a replacement fuse unit from multiple spare fuse units; and blowing the replacement fuse unit.

[0014] In an exemplary embodiment of the present disclosure, selecting a replacement fuse unit from a plurality of spare fuse units includes: determining a target word line and a target bit line to which the fuse unit to be replaced is connected; when there is an unused first spare fuse unit on the target word line, using the first spare fuse unit to replace the fuse unit to be replaced; when there is no unused first spare fuse unit on the target word line, if there is an unused second spare fuse unit on the target bit line, using the second spare fuse unit to replace the fuse unit to be replaced; when there is no unused second spare fuse unit on the target bit line, determining that the fuse unit array is failed.

[0015] In an exemplary embodiment of the present disclosure, the number of fuse units to be replaced is N, and selecting a replacement fuse unit from multiple spare fuse units includes: determining N unused third spare fuse units with the smallest address values ​​in the spare fuse unit array; using N third spare fuse units to replace N fuse units to be replaced, N≥1.

[0016] In an exemplary embodiment of the present disclosure, N≥2, N uses N third spare fuse units to replace N fuse units to be replaced, including: arranging the N fuse units to be replaced from small to large according to address values; arranging the N third spare fuse units from small to large according to address values; and using the N third spare fuse units to replace the fuse units to be replaced according to the corresponding arrangement sequence.

[0017] In an exemplary embodiment of the present disclosure, blowing the replacement fuse unit includes: blowing the replacement fuse unit a third preset value times, where the third preset value is greater than two.

[0018] In an exemplary embodiment of the present disclosure, after the replacement fuse unit is blown, the method includes: reading the replacement fuse unit; and when the replacement fuse unit is in an unblown state, reselecting a replacement fuse unit from a plurality of spare fuse units.

[0019] According to a second aspect of the present disclosure, an electronic device is provided, comprising: a memory; and a processor coupled to the memory, wherein the processor is configured to execute any one of the above methods based on instructions stored in the memory.

[0020] According to a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a program is stored, and when the program is executed by a processor, the fuse unit detection method as described in any one of the above items is implemented.

[0021] The disclosed embodiment reads data at a second, lower temperature and compares it with the data read at a first, higher temperature, thereby identifying fuse cells whose storage states are abnormal due to the decrease in temperature, and performing repairs such as additional blowing of the fuse cells, thereby maintaining the normal operation of the fuse cell array and improving the reliability of devices such as DRAM that use fuse cell arrays.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0024] Figure 1 is a flow chart of a fuse unit detection method in an exemplary embodiment of the present disclosure.

[0025] Figure 2It is a schematic diagram of first data and second data in one embodiment of the present disclosure.

[0026] Figure 3 is a circuit diagram for comparing second data with first data in one embodiment of the present disclosure.

[0027] Figure 4 It is a sub-flow chart of step S4 in one embodiment of the present disclosure.

[0028] Figure 5 is a flowchart of step S4 in another embodiment of the present disclosure.

[0029] Figure 6 Schematic diagram of a backup fuse unit in one embodiment of the present disclosure.

[0030] Figure 7 is a flowchart of step S45 in one embodiment of the present disclosure.

[0031] Figure 8 It is an overall flow chart of method 100 in one embodiment of the present disclosure.

[0032] Fig. 9 It is a detailed flowchart of steps S81-S83 in one embodiment of the present disclosure.

[0033] Fig.10 It is a detailed flowchart of step S84 in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0035] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0036] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0037] Figure 1 is a flow chart of a fuse unit detection method in an exemplary embodiment of the present disclosure.

[0038] refer to Figure 1 , the fuse unit detection method 100 may include:

[0039] Step S1, reading a fuse unit array at a first temperature to obtain first data, wherein the fuse unit array includes a plurality of fuse units;

[0040] Step S2, reading the fuse unit array at a second temperature to obtain second data, wherein the second temperature is lower than the first temperature;

[0041] Step S3, when the second data is not equal to the first data, determining a fuse unit to be processed according to a comparison result between the first data and the second data;

[0042] Step S4, repairing the fuse unit to be processed at the second temperature.

[0043] The disclosed embodiment reads data at a second, lower temperature and compares it with the data read at a first, higher temperature, thereby identifying fuse cells having abnormal storage states due to a decrease in temperature, and performing repairs such as additional blowing of the fuse cells, thereby maintaining the normal operation of the fuse cell array and improving the reliability of devices such as DRAM that use fuse cell arrays.

[0044] The embodiments of the present disclosure may be used to detect and repair a fuse cell array that has been used.

[0045] Next, each step of the fuse unit detection method 100 is described in detail.

[0046] In step S1 , a fuse cell array is read at a first temperature to obtain first data, wherein the fuse cell array includes a plurality of fuse cells.

[0047] The inventors of the present application have found in actual tests that the scenarios that lead to data reading anomalies in the fuse unit array are concentrated in low temperature environments. From a physical structure point of view, the fuse unit (E-fuse) forms an oxide layer (Oxide) between the gate (Gate) and the drain (Drain) ends. The process of writing data is to apply a voltage between the gate and the drain to break through the oxide layer to form a path, commonly known as breaking the fuse, also known as fusing the fuse unit. The resistance of a fuse unit in an unblown state is large, and it is usually regarded as storing data 0; the resistance of a fuse unit in a blown state is small, and it is usually regarded as storing data 1. Therefore, the data storage state of the fuse unit can be determined by reading the resistance of the fuse unit.

[0048] Whether the fuse unit is completely blown is largely affected by temperature and internal control timing. Studies have found that at high temperatures or room temperatures, the blown state of the fuse unit is relatively stable, but as the temperature decreases, the resistance of the fuse unit increases, causing the fuse unit to be judged as unblown when data is read, resulting in data reading errors. That is, there is a situation where the fuse unit is judged to store data 1 at high temperatures or room temperatures, and the fuse unit is judged to store data 0 at low temperatures.

[0049] In the embodiment of the present disclosure, in order to determine whether an abnormality occurs in the fuse unit, data of the fuse unit in a normal state is firstly collected.

[0050] In step S1, the first temperature is, for example, room temperature (25°C) or other temperatures that meet the normal operation of the fuse unit, so as to read the correct data stored in the fuse unit as the first data for subsequent comparison and identification.

[0051] It should be noted that before reading the fuse cell array, the fuse cell array needs to store data, rather than being in a blank state. When reading the fuse cell array, each fuse cell is tested by row and column. When the resistance of a fuse cell is greater than the reference resistance value, the fuse cell is judged to be in an unblown state; when the resistance of a fuse cell is less than the reference resistance value, the fuse cell is judged to be in a blown state. The fuse cell in the blown state is recorded as storage data 1, and the fuse cell in the unblown state is recorded as storage data 0.

[0052] The first data is a binary number. The number of bits of the first data is equal to the number of fuse units in the fuse unit array, and the digits in the first data are arranged in the order in which the fuse units are read, so that each bit in the first data uniquely corresponds to a fuse unit, and the storage state of the fuse unit corresponding to a certain bit in the first data can be located by the value of the bit.

[0053] In step S2, the fuse cell array is read at a second temperature to obtain second data, where the second temperature is lower than the first temperature.

[0054] In one embodiment, the second temperature may be lower than 0°C, or other low temperatures at which data anomalies of the fuse cell array occur. After reading the fuse cell array at the first temperature, the storage cell array may be placed in a low temperature environment for a period of time to provide sufficient conditions for the fuse cell to fail at low temperatures. In order to prevent the fuse cell from recovering from failure at room temperature, when reading the fuse cell array in step S2, it is necessary to maintain the low temperature environment in which the fuse cell array (the chip in which it is located) is located, and do not move the fuse cell array to other temperature states.

[0055] In addition, since the state of failure of the fuse unit at low temperature is an abnormal state, the abnormal state is unstable and there is a possibility that it cannot be detected at any time. In another embodiment of the present disclosure, the fuse unit array can be read a first preset value of times to obtain a first preset value of sub-data, and then the first preset value of sub-data are bitwise ANDed to obtain second data.

[0056] Figure 2 It is a schematic diagram of first data and second data in one embodiment of the present disclosure.

[0057] refer to Figure 2 , assuming that the first data is 1111 1110 0110 1000, the first preset value is equal to 4, and the four reading results of the fuse cell array at the second temperature are 1111 1110 01101000, 1111 0110 0010 1000, 1111 0110 0110 1000, and 0111 1110 0010 1000, respectively. Low temperature data anomalies occur in the second, third, and fourth readings. The results of the first reading, the second reading, the third reading, and the fourth reading are bitwise ANDed to obtain the data bits that all have low temperature data anomalies in the first preset value reading.

[0058] Next, the second data is compared with the first data to determine which fuse unit or fuse units have low temperature data anomalies.

[0059] In step S3, when the second data is not equal to the first data, a fuse unit to be processed is determined according to a comparison result between the first data and the second data.

[0060] In one embodiment, the second data and the first data can be compared bit by bit, and when the nth bit of the second data is equal to the first value and the nth bit of the first data is equal to the second value, the fuse unit corresponding to the nth bit is determined as the fuse unit to be processed, the first value corresponds to the unblown state of the fuse unit, and the second value corresponds to the blown state of the fuse unit. The first value is, for example, 0, and the second value is, for example, 1.

[0061] Figure 3 is a circuit diagram for comparing second data with first data in one embodiment of the present disclosure.

[0062] In one embodiment, the second data can be identified bit by bit, and the data bits that are 0 in the second data and 1 in the first data are marked, while the data bits in other situations are not marked. Figure 3 The circuit shown compares the second data with the first data bit by bit.

[0063] refer to Figure 3 In the detection circuit 300, the i-th bit D2[i] of the second data can be input to the first end of the first N-type transistor MN1, and the i-th bit D1[i] of the first data can be input to the control end of the first N-type transistor MN1. The second end of the first N-type transistor MN1 is connected to the gate of the first P-type transistor MP1 and the first end of the first resistor unit R1, the source of the first P-type transistor MP1 and the second end of the first resistor unit R1 are both connected to the power supply voltage VDD, the drain of the first P-type transistor MP1 is connected to the first end of the second resistor unit R2, the second end of the second resistor unit R2 is grounded, and the drain of the first P-type transistor MP1 is the output end of the circuit.

[0064] When the i-th bit D1[i] of the first data is 0, the first N-type transistor MN1 is turned off, the gate of the first P-type transistor MP1 is pulled up by the first resistance unit R1, the drain of the first P-type transistor MP1 is pulled down by the second resistance unit R2, and the i-th bit detection value Det[i] is 0.

[0065] When the i-th bit D1[i] of the first data is 1, the first N-type transistor MN1 is turned on, and the gate of the first P-type transistor MP1 receives the i-th bit D2[i] of the second data. If the i-th bit D2[i] of the second data is 1, the first P-type transistor MP1 is still turned off, and the i-th detection value Det[i] is 0; if the i-th bit D2[i] of the second data is 0, the first P-type transistor MP1 is turned on, and the i-th detection value Det[i] is 1.

[0066] Thus, when and only when the i-th bit D1[i] of the first data is 1 and the i-th bit D2[i] of the second data is 0, the detection circuit 300 outputs 1, and in other cases, the detection circuit 300 outputs 0. Finally, the detection data with more 0s than 1s (usually the number of fuse units with abnormal low temperature data is less than the number of normal fuse units) is formed, and the fuse unit with abnormal low temperature data can be quickly located. Figure 2 Taking the first data and the second data as an example, the output value of the detection circuit 300 is 1000 10000100 0000, and only three bits are 1, so the number and position of the faulty fuse units (fuse units to be processed) can be quickly located.

[0067] The detection circuit 300 can be used specifically to detect one bit of data, and each detection circuit 300 only outputs the detection value of the corresponding bit. In this case, multiple detection circuits 300 can be set according to the number of data bits, and each bit of data can be detected in parallel, and finally the fuse unit to be processed is determined according to the output values ​​of multiple detection circuits 300. In addition, the detection circuit 300 can also be used to detect the first data and the second data input in series, and output the detection data in series. In some embodiments, no matter how many detection circuits 300 are set, a latch circuit can be added to the output end of the detection circuit 300 to latch the detection result.

[0068] Figure 3 The above is only an example, and those skilled in the art can design a detection circuit according to actual needs to detect the data bit that is 0 in the second data and 1 in the first data, and the present disclosure does not impose any special restrictions on this.

[0069] In another embodiment, the second data and the first data may be directly subjected to a bitwise XOR operation to obtain a detection value, and then one or more target bits where the value 1 is located in the detection value are determined, and the fuse units corresponding to the one or more target bits are determined as fuse units to be processed. In this embodiment, the XOR operation may mark data bits with different values ​​in the second data and the first data as 1, and since the situation where the second data is 1 and the first data is 0 almost does not exist, the marked data bits in this case are all data bits that are 0 in the second data and 1 in the first data.

[0070] The XOR operation can be implemented by building one or more XOR gate circuits. Similarly, the second data and the first data input in series can be received by an XOR gate circuit, and the detection result can be output in series, and finally the detection result can be latched; or each bit of the second data and the first data can be detected in parallel by XOR gates with the same number of data bits, so as to output the detection result of each data bit in parallel. The present disclosure does not impose any special restrictions on this.

[0071] In one embodiment, the difference between the first data and the second data may be calculated, and then one or more target bits where the value 1 is located may be determined according to the difference, and fuse units corresponding to the one or more target bits may be determined as fuse units to be processed.

[0072] Since the case where a certain data bit is 1 in the second data and 0 in the first data almost never occurs, there are only two cases where the second data is the same as the first data and a certain data bit is 0 in the second data and 1 in the first data, therefore, the first data must be greater than the second data, and the difference between the first data and the second data must be greater than or equal to 0. Therefore, the difference between the first data and the second data can be directly calculated.

[0073] like Figure 2 In the embodiment shown, the first data 1111 1110 0110 1000 is subtracted from the second data 01110110 00101000, and the result is equal to 1000 1000 0100 0000. Figure 3 The detection results of the detection circuits shown are the same.

[0074] Therefore, using the difference value to determine the number and position of the faulty fuse units (fuse units to be processed) is more convenient in programming and has a higher positioning speed.

[0075] After determining the data bit that is 0 in the second data and 1 in the first data, mark it as the target bit. Since each data bit uniquely corresponds to a fuse unit, the address of the fuse unit to be processed can be directly located according to the mapping relationship between the data bit and the fuse unit, such as the row and column where the fuse unit to be processed is located, or the word line number and bit line number connected to the fuse unit to be processed.

[0076] In step S4, the fuse unit to be processed is repaired at the second temperature.

[0077] The repair of the embodiment of the present disclosure may include two methods: supplementary fusing (i.e., re-fusing) and replacement. Regardless of the method, in order to ensure the success rate of the repair, it can be carried out at the second temperature to avoid additional unnecessary low-temperature testing.

[0078] Figure 4 It is a sub-flow chart of step S4 in one embodiment of the present disclosure.

[0079] refer to Figure 4 In one embodiment, step S4 may include:

[0080] Step S41, re-blowing the fuse unit to be processed at a second temperature.

[0081] Step S42, re-reading the fuse unit to be processed.

[0082] Step S43: when all the fuse units to be processed are in the blown state, it is determined that the repair is completed.

[0083] exist Figure 4 In the illustrated embodiment, since the fuse unit to be processed itself has a low-temperature fuse failure fault, in order to overcome the fault and effectively blow the fuse, when the fuse unit to be processed is re-blown, the fuse unit to be processed may be blown a second preset value at a second temperature, and the second preset value is greater than two.

[0084] When there are multiple fuse units to be processed, the multiple fuse units to be processed can be re-blown, and then the fuse unit array can be re-read to obtain the third data. In step S43, by separately detecting the data bits corresponding to the fuse units to be processed in the third data, it is determined whether all the fuse units to be processed are in the blown state. In addition, it is also possible to first directly determine whether the third data is equal to the first data. If the third data is not equal to the first data, it is then determined which data bits in the third data are still 1 in the first data and 0 in the third data, that is, there is a low temperature data abnormality problem. The comparison method can refer to the aforementioned method of comparing the second data with the first data.

[0085] If, by comparing the third data with the first data, it is identified that there are still abnormal fuse units to be processed, it can be directly determined that the remaining fuse units to be processed cannot be repaired by re-fusing and can only be replaced. In addition, these fuse units to be processed can be blown again for a second preset value, and the fuse unit array can be read again. If the data read again is still not equal to the first data, there are still remaining fuse units to be processed, and it can be determined that the remaining fuse units to be processed cannot be repaired by re-fusing and can only be replaced.

[0086] Figure 5 is a flowchart of step S4 in another embodiment of the present disclosure.

[0087] refer to Figure 5 In another embodiment, step S4 may further include:

[0088] Step S44, when at least one of the to-be-processed fuse units is in an un-blown state, marking the to-be-processed fuse unit in an un-blown state as a to-be-replaced fuse unit;

[0089] Step S45, setting the fuse unit to be replaced to be invalid, and selecting a replacement fuse unit from a plurality of spare fuse units;

[0090] Step S46, blowing the replacement fuse unit.

[0091] After step S43 , the fuse unit that remains in the unblown state may be marked as a fuse unit to be replaced, and a spare fuse unit may be used to replace it.

[0092] The spare fuse unit can be arranged in the fuse unit array, distinguished from the general fuse unit by the connection position, and controlled by a separate switch to achieve activation. That is, the spare fuse unit is arranged in rows and columns like the general fuse unit, and has row and column addresses. In some embodiments, one or more spare fuse units are connected to a row or column of general fuse units through the same word line or bit line.

[0093] Figure 6 Schematic diagram of a backup fuse unit in one embodiment of the present disclosure.

[0094] refer to Figure 6 , fuse unit 61 connects word lines and bit lines, arranged in rows and columns, bit line BL is numbered i, word line WL is numbered j. A spare fuse unit 62 may be set for each bit line BL, and one or more spare fuse units 62 (only one is shown in the figure) may be controlled by one or more spare word lines WLn. A spare fuse unit may also be set for each word line WL, and one or more spare fuse units 62 (only one is shown in the figure) may be controlled by one or more spare bit lines BLn. The spare fuse units 62 connected to the word line WL and the bit line BL may be set at the same time, or the spare fuse unit 62 may be set only on the word line WL, or the spare fuse unit 62 may be set only on the bit line BL.

[0095] In some embodiments, the spare fuse unit 62 may be arranged between the fuse units 61. Figure 6 The fuse units connected to the word lines WLj are replaced with spare fuse units 62 (not shown), or Figure 6 The fuse cells connected to the bit line BLi are all replaced with spare fuse cells 62 (not shown), thereby improving the efficiency of enabling and controlling the spare fuse cells 62 .

[0096] The enabling of the spare fuse unit 62 can be controlled by an additional switch or by inputting signals to the word line and the bit line connected to the spare fuse unit 62. The enabling method of the spare fuse unit 62 can be determined according to how to use the spare fuse unit 62 to replace the failed fuse unit 61 in step S45.

[0097] Figure 7 is a flowchart of step S45 in one embodiment of the present disclosure.

[0098] refer to Figure 7 In one embodiment, step S45 may include:

[0099] Step S451, determining a target word line and a target bit line connected to the fuse unit to be replaced;

[0100] Step S452, when there is an unused first spare fuse unit on the target word line, use the first spare fuse unit to replace the fuse unit to be replaced;

[0101] Step S453, when there is no unused first spare fuse unit on the target word line, if there is an unused second spare fuse unit on the target bit line, use the second spare fuse unit to replace the fuse unit to be replaced;

[0102] Step S454 , when there is no unused second spare fuse cell on the target bit line, it is determined that the fuse cell array is failed.

[0103] Also refer to Figure 6 and Figure 7 When the fuse unit connected to the bit line BLi and the word line WLj is a fuse unit to be replaced, the bit line BLi and the word line WLj are determined as the target bit line and the target word line.

[0104] Next, if the word line WLj is connected to the backup fuse unit 62 connected to the backup bit line BLm, it is determined whether the backup fuse unit 62 connected to the backup bit line BLm is in an unused state. If so, the backup fuse unit 62 connected to the backup bit line BLm is set as the fuse unit to be replaced.

[0105] If the backup fuse unit 62 connected to the backup bit line BLm is in use, determine whether other unused backup fuse units 62 are connected to the word line WLj. If so, set the other unused backup fuse units 62 connected to the word line WLj as fuse units to be replaced.

[0106] If no other backup fuse unit 62 is connected to the word line WLj, or other backup fuse units 62 connected to the word line WLj are all in use, or if no backup fuse unit 62 is connected to the word line WLj, then the backup fuse unit 62 connected to the target bit line, ie, the bit line BLi, is searched.

[0107] If the bit line BLi is connected to a spare fuse unit 62 connected to a spare word line WLn, it is determined whether the spare fuse unit 62 connected to the spare word line WLn is in an unused state. If so, the spare fuse unit 62 connected to the spare word line WLn is set as a fuse unit to be replaced.

[0108] If the backup fuse unit 62 connected to the backup word line WLn is in use, determine whether other unused backup fuse units 62 are connected to the bit line BLi. If so, set the other unused backup fuse units 62 connected to the bit line BLi as fuse units to be replaced.

[0109] If no other spare fuse unit 62 is connected to the bit line BLi, or all other spare fuse units 62 connected to the bit line BLi are in use, or if no spare fuse unit 62 is connected to the bit line BLi, spare fuse units at other positions are searched.

[0110] The spare fuse units at other positions refer to spare fuse units that are not connected to the same word line or bit line as any fuse unit 61 , and may be connected via separate word lines and bit lines to avoid affecting the control of the fuse unit 61 .

[0111] In one embodiment, if the other spare fuse units 62 connected to the word line WLj are all in use and the other spare fuse units 62 connected to the bit line BLi are all in use, and no other spare fuse units are set, if the position of the fuse unit to be replaced involves the normal operation of the fuse unit array, it can be determined that the fuse unit array has failed.

[0112] After determining a replacement spare fuse unit 62 for a fuse unit to be replaced according to the above process, the fuse units to be replaced can continue to be traversed until all the fuse units to be replaced have been determined to have replacement spare fuse units 62 as replacement fuse units. Alternatively, when one or more fuse units to be replaced cannot be determined to be replacement fuse units and the positions of the one or more fuse units to be replaced involve the normal operation of the fuse unit array, it is determined that the fuse unit array has failed.

[0113] The above sequence is only an example. In actual application, the spare fuse unit connected to the target bit line may be selected first, and then the spare fuse unit connected to the target word line may be selected. The present disclosure does not limit the selection sequence of the spare fuse units.

[0114] In another embodiment, if a plurality of spare fuse units are not connected to the same word line or bit line as any fuse unit 61, it is also possible to select a plurality of replacement fuse units at a time according to the addresses of the spare fuse units.

[0115] When the number of fuse units to be replaced is N, selecting a replacement fuse unit from a plurality of spare fuse units may include: determining N unused third spare fuse units with the smallest address values ​​in the spare fuse unit array, and using the N third spare fuse units to replace the N fuse units to be replaced, where N≥1. In this embodiment, the N fuse units to be replaced may be arranged from small to large according to the address values, and similarly, the N third spare fuse units may be arranged from small to large according to the address values, and finally, the N third spare fuse units may be used to replace the fuse units to be replaced according to the arrangement sequence.

[0116] Since the fuse units to be replaced are all fuse units whose value is 0 at the second temperature and 1 at the first temperature, after the replacement fuse unit is determined, the replacement fuse unit needs to be blown to write data 1. In one embodiment, the replacement fuse unit can be blown for a third preset value, and the third preset value is greater than two to ensure that the data of the replacement fuse unit is written correctly.

[0117] If the replacement fuse unit is connected to the same word line or bit line as the fuse unit to be replaced, the replacement fuse unit can be directly written and read in the same way as the original access method. Figure 6 For example, if the fuse unit connected to the bit line BLi and the word line WLj is a fuse unit to be replaced, and the spare fuse unit 62 connected to the bit line BLi and the spare word line WLn is a replacement fuse unit, the fuse unit to be replaced is first set to be invalid, and the bit line BLi and the spare word line WLn are controlled at the same time to write data 1 to the replacement fuse unit. When it is necessary to read the location of the fuse unit to be replaced, the original bit line BLi and the word line WLj address are not used for reading, but the bit line BLi and the spare word line WLn are used for reading, and the bit lines are the same. Similarly, if the spare fuse unit 62 connected to the word line WLj and the spare bit line BLm is a replacement fuse unit, the original bit line BLi and the word line WLj address are not used for reading, but the word line WLj and the spare bit line BLm are used for reading, and the word lines are the same.

[0118] If the replacement fuse unit and the fuse unit to be replaced are not connected to the same word line or bit line, the replacement fuse unit can be directly written and read according to the recorded address mapping relationship. For example, when the location of the fuse unit to be replaced needs to be read, the original bit line BLi and word line WLj addresses are not used for reading, but the mapped addresses are used for reading.

[0119] After the replacement fuse unit is blown in step S45, the replacement fuse unit may be read, and when the replacement fuse unit is in an unblown state, a replacement fuse unit is selected again from a plurality of spare fuse units.

[0120] If there are multiple replacement fuse units, the multiple replacement fuse units can be batch-fused for a third preset value, and then the fuse unit array is read to obtain the fourth data. If the fourth data is equal to the first data, the repair is completed. If the fourth data is not equal to the first data, the method of the aforementioned embodiment is used to locate the fuse unit that still has a low-temperature fuse failure and data abnormality according to the difference between the fourth data and the first data, and the fuse unit or fuses are re-fused again according to the method of the above step S3. If the re-fusing still cannot be repaired, the replacement fuse unit is selected again until there is no optional replacement fuse unit, and the fuse unit array is judged to be failed.

[0121] Figure 8 It is an overall flow chart of method 100 in one embodiment of the present disclosure.

[0122] refer to Figure 8 In step S81, the chip having the fuse cell array may be tested cyclically, and a fuse cell array may be read to determine the second data and identify the fuse cell to be processed.

[0123] In step S82, the fuse unit to be processed is supplementarily blown, and low temperature instability detection and supplementary blowing are performed.

[0124] In step S83, the fuse unit that is still in an unblown state after the supplementary blowing is determined as a fuse unit to be replaced, and the strong failure fuse unit information is output.

[0125] In step S84, a replacement fuse unit corresponding to the fuse unit to be replaced is selected from the spare fuse units to replace the fuse unit to be replaced.

[0126] In step S85, it is determined whether the chip cycle is completed. If so, the fuse unit detection is completed. If not, and there are other fuse unit arrays to be detected, the process returns to step S81 for processing.

[0127] Fig. 9 It is a detailed flowchart of steps S81-S83 in one embodiment of the present disclosure.

[0128] refer to Fig. 9 In step S91, the fuse cell array may be cyclically read a first preset value of times at the second temperature, and in step S92, the read results of the first preset value of times are bitwise ANDed to obtain second data.

[0129] In step S93 , first data read from the fuse cell array at the first temperature is loaded.

[0130] In step S94, the second data is compared with the first data to identify the fuse unit to be processed.

[0131] In step S95, the location file of the fuse unit to be processed is output.

[0132] In step S96, the position file of the fuse unit to be processed is loaded, and the fuse unit to be processed is supplementarily blown.

[0133] In step S97, it is determined whether the data of the fuse cell array returns to normal at the second temperature after the supplementary fuse is blown. If so, the repair is terminated. If not, the process proceeds to step S98 to output the location file of the fuse cell to be replaced.

[0134] Fig.10 It is a detailed flowchart of step S84 in one embodiment of the present disclosure.

[0135] refer to Fig.10 In step S101, the position file of the fuse unit to be replaced outputted in step S98 is obtained, and the patching rule of the current fuse unit array is loaded. The patching rule includes, for example, what conditions a spare fuse unit meeting can be used as a replacement fuse unit, and in what order a replacement fuse unit is selected from a plurality of spare fuse units.

[0136] In step S102, a fuse unit to be replaced is determined, a replacement fuse unit is selected for the fuse unit to be replaced, and the fuse unit to be replaced is replaced.

[0137] In step S103, it is determined whether the replacement is successful, that is, there is a replacement fuse unit that meets the conditions. If so, the process proceeds to step S104, otherwise it is determined that the fuse unit array is invalid.

[0138] In step S104, it is determined whether all fuse units to be replaced have been replaced. If not, the process returns to step S102; if yes, the process proceeds to step S105.

[0139] In step S105, a third preset value of data is written to all replacement fuse units, ie, the fuses are blown.

[0140] In step S106, the fuse cell array is read to determine whether the read result is equal to the first data. If so, it is determined that the repair is completed; otherwise, it is determined that the fuse cell array is failed.

[0141] The disclosed embodiments can compensate for the failure characteristics of low-temperature fuse units by detecting fuse units that fail at low temperatures and performing supplementary fusing at low temperatures, thereby solving the problem of abnormalities in some fuse units at low temperatures and allowing subsequent tests to continue. For strongly failed fuse units that still have low-temperature data anomalies after supplementary fusing, dynamic replacement methods can be implemented to replace and repair them, thereby preventing the loss of a good product due to a strongly failed fuse unit and improving the yield of the product. The dual solution process of low-temperature supplementary fusing and strongly failed bit replacement can compensate for defects in process and design, greatly enhancing the burning quality of fuse units at low temperatures and improving the yield of products.

[0142] Corresponding to the above method embodiments, the present disclosure also provides a testing device that can be used to execute the above method embodiments.

[0143] The test device provided by the embodiment of the present disclosure is connected to the memory to be tested, and includes a processor, and the processor is used to execute the fuse unit detection method of any of the above embodiments to perform fuse unit detection on the memory to be tested.

[0144] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0145] In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0146] It will be appreciated by those skilled in the art that various aspects of the present invention may be implemented as a system, method or program product. Therefore, various aspects of the present invention may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as a "circuit", "module" or "system".

[0147] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the above method of the present specification is stored. In some possible implementations, various aspects of the present invention can also be implemented in the form of a program product, which includes a program code, and when the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of the present specification.

[0148] The program product for implementing the above method according to an embodiment of the present invention can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, an apparatus or a device.

[0149] The program product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0150] Computer readable signal media may include data signals propagated in baseband or as part of a carrier wave, in which readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Readable signal media may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0151] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0152] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0153] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0154] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A fuse unit detection method, characterized in that: include: Reading a fuse cell array at a first temperature to obtain first data, wherein the fuse cell array includes a plurality of fuse cells; Reading the fuse cell array at a second temperature to obtain second data, wherein the second temperature is lower than the first temperature; When the second data is not equal to the first data, determining a fuse unit to be processed according to a comparison result between the first data and the second data; The fuse unit to be processed is repaired at the second temperature.

2. The fuse unit detection method according to claim 1, characterized in that: The reading the fuse cell array at the second temperature comprises: Reading the fuse unit array a first preset value times to obtain a first preset value of sub-data; A bitwise AND operation is performed on the first preset value sub-data to obtain the second data.

3. The fuse unit detection method according to claim 1 or 2, characterized in that: The step of determining the fuse unit to be processed according to the comparison result between the first data and the second data comprises: performing a bitwise comparison on the second data and the first data; When the nth bit of the second data is equal to the first value and the nth bit of the first data is equal to the second value, the fuse unit corresponding to the nth bit is determined as the fuse unit to be processed, the first value corresponds to the unblown state of the fuse unit, and the second value corresponds to the blown state of the fuse unit.

4. The fuse unit detection method according to claim 1 or 2, characterized in that: The step of determining the fuse unit to be processed according to the comparison result between the first data and the second data comprises: Performing a bitwise XOR operation on the second data and the first data to obtain a detection value; Determine one or more target positions where the value 1 in the detection value is located; The fuse units corresponding to the one or more target bits are determined as fuse units to be processed.

5. The fuse unit detection method according to claim 1 or 2, characterized in that: The step of determining the fuse unit to be processed according to the comparison result between the first data and the second data comprises: Calculating a difference between the first data and the second data; Determine one or more target positions where the value 1 is located according to the difference; The fuse units corresponding to the one or more target bits are determined as fuse units to be processed.

6. The fuse unit detection method according to claim 1, characterized in that: The repairing of the fuse unit to be processed at the second temperature comprises: re-fusing the fuse unit to be processed at the second temperature; re-reading the fuse unit to be processed; When all the fuse units to be processed are in the blown state, it is determined that the repair is completed.

7. The fuse unit detection method according to claim 6, characterized in that: The re-fusing the fuse unit to be processed at the second temperature comprises: The fuse unit to be processed is blown a second preset value of times at the second temperature, and the second preset value is greater than two.

8. The fuse unit detection method according to claim 6, characterized in that: The repairing of the fuse unit to be processed at the second temperature comprises: When at least one of the to-be-processed fuse units is in an un-blown state, marking the to-be-processed fuse unit in an un-blown state as a to-be-replaced fuse unit; Setting the fuse unit to be replaced to fail, and selecting a replacement fuse unit from a plurality of spare fuse units; The replacement fuse unit is blown.

9. The fuse unit detection method according to claim 8, characterized in that: The selecting a replacement fuse unit from a plurality of spare fuse units comprises: Determining a target word line and a target bit line connected to the fuse unit to be replaced; When there is an unused first spare fuse unit on the target word line, using the first spare fuse unit to replace the fuse unit to be replaced; When there is no unused first spare fuse unit on the target word line, if there is an unused second spare fuse unit on the target bit line, use the second spare fuse unit to replace the fuse unit to be replaced; When there is no unused second spare fuse cell on the target bit line, it is determined that the fuse cell array is failed.

10. The fuse unit detection method according to claim 8, characterized in that: The number of fuse units to be replaced is N, and the selecting a replacement fuse unit from a plurality of spare fuse units comprises: Determine N unused third spare fuse units with the smallest address values ​​in the spare fuse unit array; N of the third spare fuse units are used to replace N of the fuse units to be replaced, where N≥1.

11. The fuse unit detection method according to claim 10, characterized in that: N≥2, N said using N said third spare fuse units to replace N said fuse units to be replaced comprises: Arrange the N fuse units to be replaced from small to large according to address values; Arranging the N third spare fuse units from small to large according to the address values; The N third spare fuse units are used to replace the fuse units to be replaced according to the arrangement sequence.

12. The fuse unit detection method according to claim 8, characterized in that: The fusing of the replacement fuse unit comprises: The replacement fuse unit is blown a third preset value times, where the third preset value is greater than two.

13. The fuse unit detection method according to claim 8, characterized in that: After the replacement fuse unit is blown, the method comprises: reading the replacement fuse unit; When the replacement fuse unit is in an unblown state, a replacement fuse unit is reselected from the plurality of spare fuse units.

14. A testing device, characterized in that: A device is connected to a memory to be tested, and includes a processor, wherein the processor is used to execute the fuse unit detection method according to any one of claims 1 to 13 to perform fuse unit detection on the memory to be tested.

15. A computer-readable storage medium having a program stored thereon, wherein when the program is executed by a processor, the fuse unit detection method according to any one of claims 1 to 13 is implemented.

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