Differential amplifier and ultraviolet spectrum rapid acquisition system

Abstract

The invention relates to the technical field of spectral signal detection and the technical field of flue gas component detection. The invention provides a differential amplifier. The differential amplifier comprises a U1A unit, a U1B unit, a U2A unit and a U2B unit, the U2A unit comprises an OPA2320AIDR chip, a resistor R2, a resistor R3, a resistor R4 and a resistor R6; the U2A unit is used for receiving and processing positive phase signals of the CMOS; the U2B unit comprises an OPA2320AIDR chip, a resistor R8, a resistor R9, a resistor R11 and a resistor R12; the U2B unit is used for receiving and processing a negative phase signal of the CMOS; the U1A unit comprises an OPA2320AIDR chip, a resistor 1 and a resistor R5; and the U1A unit is used for outputting the processed positive phase signal of the CMOS with relatively low impedance. The U1B unit comprises an OPA2320AIDR chip, a resistor R7 and a resistor R10; and the U1B unit is used for outputting the processed reverse phase signal of the CMOS with relatively low impedance. The circuit provided by the invention has the functions of surge prevention, static prevention, overvoltage and overcurrent prevention and reverse connection prevention.

Description

Technical Field

[0001] The invention relates to the technical fields of spectral signal detection and smoke component detection. Background Art

[0002] At present, the main light source solutions used in online UV analyzers are deuterium lamps and pulsed xenon lamps. Deuterium lamps are widely used in UV optical analysis instruments due to their high stability. The spectral coverage is mainly concentrated in the UV region, approximately 185 to 400 nm, which provides a good match for UV spectrum measurement. In contrast, although xenon lamps can also be used for UV spectrum measurement, their main advantage is that they provide a wide range of spectral coverage (from UV to near-infrared regions) and have a high-intensity light source.

[0003] Currently, the existing technical solutions mostly use the method of xenon lamp + MCU + AD + RAM to realize spectrum acquisition. The advantage is that the circuit structure is relatively simple, and the CMOS sensor with low acquisition speed requirements has sufficient data processing resources. The disadvantage is that when processing CMOS with high sensitivity, it cannot meet the required number of samples collected per unit time. Summary of the invention

[0004] In view of this, the present invention provides a differential amplifier, including: U1A unit, U1B unit, U2A unit and U2B unit; the U2A unit includes an OPA2320AIDR chip, a resistor R2, a resistor R3, a resistor R4 and a resistor R6; the U2A unit is used to receive and process the positive phase signal of CMOS; the U2B unit includes an OPA2320AIDR chip, a resistor R8, a resistor R9, a resistor R11 and a resistor R12; the U2B unit is used to receive and process the negative phase signal of CMOS; the U1A unit includes an OPA2320AIDR chip, a resistor R1 and a resistor R5; the U1A unit is used to output the positive phase signal of CMOS after processing with a lower impedance. The U1B unit includes an OPA2320AIDR chip, a resistor R7 and a resistor R10; the U1B unit is used to output the negative phase signal of CMOS after processing with a lower impedance.

[0005] The present invention also provides a UV spectrum rapid acquisition system, comprising: a differential amplifier, a photoelectric conversion unit, an emitter follower, a high-speed differential AD, an FPGA and an MCU;

[0006] The photoelectric conversion unit is used to convert the ultraviolet spectrum signal into a corresponding analog voltage signal;

[0007] The emitter follower is used to output the analog voltage signal of the photoelectric conversion unit to the differential amplifier without attenuation;

[0008] The differential amplifier is used to raise the unattenuated analog voltage signal output by the emitter follower by 1 / 2VCC and then output two sets of signals, an in-phase signal and an anti-phase signal, that is, converting the single-ended signal output by the CMOS into a differential signal;

[0009] The high-speed differential AD is used to convert the differential analog signal output by the differential amplifier into a digital signal; and at the same time receive the driving timing generated by the FPGA; the level conversion chip is connected to the photoelectric conversion unit and the FPGA respectively; the FPGA sends a control timing driving signal to the photoelectric conversion unit; the FPGA sends a driving timing signal to the high-speed differential AD and simultaneously receives the data converted and output by the high-speed differential AD, and outputs the processed data to the MCU.

[0010] Furthermore, the photoelectric conversion unit is a CMOS, and the model of the CMOS is S11639.

[0011] Furthermore, the model of the FPGA is EG4X20BG256B.

[0012] Furthermore, the high-speed differential AD and the FPGA communication interface adopt an LVDS interface.

[0013] The circuit provided by the invention has the functions of surge protection, static electricity protection, overvoltage and overcurrent protection and reverse connection protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a circuit structure diagram.

[0015] Figure 2 This is the S11639 drive timing diagram.

[0016] Figure 3 is the original spectrum.

[0017] Figure 4 is the concentration output graph.

[0018] Figure 5 This is a diagram of the components of a differential amplifier. DETAILED DESCRIPTION

[0019] Example

[0020] The device provided by the present invention adopts a master-slave matching method with better collection effect, high precision, large data transmission volume, and state machine data collection, which is not interrupted by any events, so that the obtained spectral data is safer and more reliable, while improving the computing speed of the analyzer product.

[0021] FPGA: It is an integrated chip mainly based on digital circuits, belonging to a type of programmable logic device (PLD); it appears as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices. In the present invention, it is a hardware system for data signal acquisition and processing.

[0022] MCU: (Microcontroller Unit) is a small computer chip that integrates all necessary components to perform computing and control tasks, mainly used in embedded systems. In this invention, it is the main control and calculation of the system.

[0023] LVDS: (Low Voltage Differential Signa ling) low voltage differential signal, using extremely low voltage swing high-speed differential transmission data, can achieve point-to-point or point-to-multipoint connection, with low power consumption, low bit error rate, low crosstalk and low radiation, etc. LVDS is the physical connection method between FPGA and high-speed differential AD conversion chip.

[0024] DOAS: Differential Optical Absorption Spectroscopy (DOAS) is a spectral monitoring technology. Its basic principle is to use the narrow-band absorption characteristics of gas molecules in the air to identify the gas components and deduce the concentration of trace gases based on the narrow-band absorption intensity.

[0025] The present invention provides an ultraviolet spectrum rapid acquisition system, which drives, acquires and analyzes sensor CMOS spectrum signals by utilizing a combination of FPGA and MCU.

[0026] like Figure 1 As shown, the present invention provides a UV spectrum rapid acquisition system, which is composed of MCU1, FPGA2, CMOS (photoelectric conversion unit) 3, emitter follower 4, high-speed differential AD 5, differential amplifier 6, level conversion chip 7, host computer processing unit 8 and reference voltage unit 9.

[0027] Wherein, the MCU is provided with an RS232 chip 11 and an RS485 chip 12;

[0028] The MCU is connected to the RS232 interface processing unit of the host computer through the TXD and RXD pins of the RS232 chip.

[0029] The MCU is connected to the instrument RS485 signal processing unit via the A and B pins of the RS485 chip.

[0030] The host computer processing unit is a PC or an analyzer. The host computer processing unit sends a control command to the MCU through the RS232 interface. The MCU identifies the command type and executes the corresponding action. Whether it is reading the spectrum or reading the concentration, the FPGA will issue a control timing to drive the CMOS detector S11639, so that the CMOS enters the detection output state. At the same time, the FPGA also generates a high-speed differential AD drive timing, so that it can convert and output data normally. The converted data is sent to the MCU by the FPGA in the form of a 16-bit parallel bus. The FPGA also outputs a falling edge trigger signal to notify the MCU to receive the data. When the MCU detects the falling edge trigger signal, it enters the interrupt to receive data, and the collected data is sent to the host computer processing unit after processing. The host computer processing unit sends instructions through RS232, including basic parameter settings, integration time settings, filtering times, reading spectrum, reading concentration, linear fitting, range and zero calibration commands. The MCU executes the commands of the host computer processing unit in the idle state, and sends the command data to the FPGA module through the parallel bus. After the FPGA detects and receives the corresponding instructions, it executes the internal drive CMOS detector S11639 and the high-speed differential AD acquisition chip AD7961 to collect the spectrum. Finally, the collected data is processed by software filtering, data truncation, DOAS technology processing and multi-order fitting, and the voltage signal of the spectrum is finally inverted to obtain useful spectral information and concentration data.

[0031] The MCU and FPGA are connected by a 16-bit parallel bus and an 8-bit control line to realize the functions of timing control and fast data transmission between chips.

[0032] The MCU and FPGA data communication adopts 16-bit parallel bus data transmission and 8-bit control line to complete the transmission of data and commands between modules. The MCU communication is provided with RS485 port and S232 port. The MCU is internally provided with RAM, which is a storage unit of 128K+64K. The MCU sends protocol frame data via RS232 or RS485, including frame header, command, data, checksum, frame tail and part. The MCU runs in the mode of state machine, waiting to receive commands and data from the host computer to execute corresponding functions. The model of the MCU is STM32F407.

[0033] The EEPROM is connected to the I / O port of the MCU via an I2C bus.

[0034] The driving port of the FPGA is connected to the SPI port of the high-speed differential AD and connected in LVDS mode. The signal connection between the FPGA and the CMOS is connected to each pin through a level conversion chip, which plays the role of conversion of level mismatch between chips and interface protection. The FPGA is used to generate the driving control timing of the CMOS, including two input signals and three output signals, the input signal CLK clock signal, the ST integration signal, the output timing signal Trig, the scanning end signal EOS and the spectrum image output Video signal, so that the CMOS enters the state of detecting and outputting the spectrum according to the driving control timing. The FPGA is also used to generate the driving timing of the high-speed differential AD conversion chip, so that the high-speed differential A / D conversion chip can normally convert and output the converted data according to the driving timing. After receiving the converted data, the FPGA sends it to the MCU in the form of a 16-bit parallel bus, and outputs a falling edge trigger signal to notify the MCU to receive the data. The model of the FPGA is EG4X20BG256B.

[0035] The high-speed differential AD is used to convert the analog signal output by the differential amplifier into a digital signal. The technical indicators of the high-speed differential AD are: 5MSPS sampling rate, 95.5dB signal-to-noise ratio (SNR), ±0.2LSB integral nonlinearity (INL) and ±0.14LSB differential nonlinearity (DNL). The high-speed differential AD and the FPGA communication interface adopts an LVDS interface, which can effectively reduce the bit error rate and PCB wiring difficulty of the communication between the high-speed differential AD acquisition chip and the FPGA. The model of the high-speed differential AD acquisition chip is AD7961.

[0036] The high-speed differential AD is connected to a reference voltage unit signal line, and the high-speed differential AD determines a detection range according to a set value of the reference voltage unit.

[0037] The differential amplifier includes a U1A unit, a U1B unit, a U2A unit and a U2B unit;

[0038] The U2A unit 3 pin of the OPA2320AIDR chip is connected to the R2 and R3 resistors with resistance values ​​of 110K and 150K, and the 150K resistor R4 is connected to the U2A unit 2 pin. The 150K resistor R6 is connected to the U2A unit pins 2 and 1; the U2A unit processes and outputs the positive phase signal of the CMOS.

[0039] The U2B unit pin 6 of the chip OPA2320AIDR is connected to R9 with a resistance of 150K, the resistor R8 with a resistance of 150K is connected to the U2B unit pin 7, and the R11 and R12 with a resistance of 150K are connected to the U2B unit pin 5; the U2B unit processes and outputs the anti-phase signal of the CMOS.

[0040] Pin 3 of the U1A unit of the chip OPA2320AIDR is connected to the OR resistor R5, and R1 of the OR resistor is respectively connected to pins 1 and 2 of the U1A unit; the U1A unit is used to output the processed CMOS positive phase signal with lower impedance.

[0041] Pin 5 of the U1B unit of the chip OPA2320AIDR is connected to the OR resistor R10, and the OR resistor R7 is respectively connected to the 6th and 7th pins of the U1B unit; the U1B unit is used to output the processed CMOS anti-phase signal with lower impedance.

[0042] The differential amplifier is used to pre-process the AC signal output by the CMOS, and use the op amp to realize the adder function to raise the signal by 1 / 2VCC, that is, to raise the negative half-axis signal to the positive half cycle, above the zero point. At the same time, the single-ended signal output by the CMOS is converted into a differential signal, that is, two sets of signals with the same phase and 180° reverse phase. The same phase signal and the reverse phase signal output by the differential amplifier are connected to the IN+ and IN- of the high-speed differential AD respectively.

[0043] The emitter follower is arranged between the CMOS and the differential amplifier. The spectrum signal output by the CMOS is connected to the emitter follower, and the amplification factor is ≈1. Its characteristics are high input impedance and low output impedance, which ensure that the signal is output to the subsequent circuit without attenuation. The output signal of the emitter follower is connected to the non-inverting input terminal R3 and the inverting input terminal R9 of the differential amplifier.

[0044] The photoelectric conversion unit is used to realize photoelectric conversion, which converts ultraviolet spectrum information into corresponding analog voltage signals. The photoelectric conversion unit is a CMOS, and the model of the CMOS is S11639. This model of CMOS has characteristics such as high sensitivity and high impedance, and supports a maximum operating frequency of 10MHZ. The operating frequency of the CMOS is set to 4M. The first port of the CMOS is connected to the first port of the FPGA; an isolation buffer chip is also provided between the CMOS and the FPGA, and the isolation buffer chip is used to add a level conversion chip to protect the level mismatch problem between interfaces and solve the problem that the I / O of the FPGA is damaged by static electricity due to improper operation when the S11639 is not connected.

[0045] The invention adopts a power supply with a direct current (DC) input of 9-36V, an anti-surge and anti-static interface and an overvoltage and overcurrent circuit.

[0046] The present invention adopts a high-speed differential AD acquisition chip. The differential input design can effectively suppress common mode noise, reduce the background noise of spectral signals, and increase the sampling rate. Both the analog input port and the digital output port adopt a differential mode.

[0047] The present invention can not only read the ultraviolet spectrum, but also has the greatest advantage of being able to invert the concentrations of SO2, NO, and NO2, and realize linear fitting, coefficient calibration and zero point calibration.

[0048] The present invention uses a deuterium lamp light source, and the circuit utilizes the ARM+FPGA combination characteristics to achieve the advantages of rapid spectrum acquisition and more precise timing control.

[0049] The present invention realizes the functions from spectrometer signal acquisition, signal preprocessing, software filtering, algorithm processing, linear fitting, data calibration to the final concentration output. Figure 5 As shown, it is based on Figure 4 The area or concentration value of each detected component obtained after software filtering, band interception and DOAS technology processing is displayed through a scatter plot.

[0050] The present invention is mainly used in online analyzers, and the working scene requires uninterrupted operation, and the longest possible operation is until the light source ages and cannot be used. This puts higher requirements on the circuit and software. The circuit part is equipped with surge protection, anti-static, overvoltage and overcurrent protection, and reverse connection protection functions. The MCU software part is equipped with a hardware watchdog and a software watchdog, which are responsible for monitoring the MCU program operation and the FPGA operation status respectively. Once an abnormality occurs, corresponding reset and rapid recovery processing will be performed.

[0051] The solution of the present invention adopts a deuterium lamp as a light source, which has the characteristics of continuous light emission and is more stable and reliable. The collected spectrum is more stable and accurate, and there is no need for an external trigger light source. The space for software control modules and hardware wiring is reduced, and spectral noise can be greatly reduced.

[0052] The single-ended to differential circuit of the present invention is composed of discrete components, and the performance is not lower than that of integrated chips after testing, and has better application flexibility. The disadvantage is that the number of components used is more than that of integrated chips, but the cost is much lower than that of chips.

Claims

1. A differential amplifier, characterized in that include: Unit U1A, Unit U1 B, Unit U2A and Unit U2B; The U2A unit includes an OPA2320AIDR chip, a resistor R2, a resistor R3, a resistor R4 and a resistor R6; the U2A unit is used to receive and process the positive phase signal of the CMOS; The U2B unit includes an OPA2320AIDR chip, a resistor R8, a resistor R9, a resistor R11 and a resistor R12; the U2B unit is used to receive and process the negative phase signal of the CMOS; The U1A unit includes: an OPA2320AIDR chip, a resistor 1 and a resistor R5; the U1A unit is used to output the processed CMOS positive phase signal with a lower impedance; The U1 B unit includes: an OPA2320AIDR chip, a resistor R7 and a resistor R10; the U1 B unit is used to output the processed CMOS anti-phase signal with a lower impedance.

2. Ultraviolet spectrum rapid acquisition system, including: The differential amplifier, photoelectric conversion unit, emitter follower, high-speed differential AD, FPGA and MCU as described in claim 1; The photoelectric conversion unit is used to convert the ultraviolet spectrum information into a corresponding analog voltage signal; The emitter follower is used to output the analog voltage signal of the photoelectric conversion unit to the differential amplifier without attenuation; The differential amplifier is used to raise the AC signal output by the emitter follower by 1 / 2VCC and convert the single-ended signal output by the CMOS into a differential signal; The high-speed differential AD is used to convert the analog signal output by the differential amplifier into a digital signal; and at the same time receive the driving timing generated by the FPGA; The level conversion chip is connected to the photoelectric conversion unit and the FPGA respectively; The FPGA sends a control timing drive signal to the photoelectric conversion unit; the FPGA sends a drive timing signal to the high-speed differential AD and simultaneously receives data output by the high-speed differential AD, converts the data and outputs it to the MCU.

3. The ultraviolet spectrum rapid acquisition system according to claim 2, characterized in that: The photoelectric conversion unit is a CMOS, and the model of the CMOS is S11639.

4. The ultraviolet spectrum rapid acquisition system according to claim 2, characterized in that: The model of the FPGA is EG4X20BG256B.

5. The ultraviolet spectrum rapid acquisition system according to claim 2 is characterized in that: The high-speed differential AD and the FPGA communication interface adopt an LVDS interface.

6. The ultraviolet spectrum rapid acquisition system according to claim 2, characterized in that: The MCU is provided with a RS232 port or a RS485 port.

7. The ultraviolet spectrum rapid acquisition system according to claim 2 is characterized in that: It also includes: an EEPROM; the EEPROM is connected to the MCU.

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