Frequency jittering circuit and electrical equipment

Abstract

The invention relates to a frequency jittering circuit and electrical equipment. The frequency jittering circuit comprises an energy storage device, and the first end of the energy storage device is connected with a target node; the charging and discharging module is used for charging and discharging the energy storage device; the clock signal output module is used for comparing the voltage of the target node with a target reference voltage to generate a clock signal and providing the clock signal to the charging and discharging module to control charging and discharging of the energy storage device; the reference voltage generation module is used for circularly outputting threshold voltages with different amplitudes as target reference voltages and providing the target reference voltages to the clock signal output module so as to change the charging and discharging duration of the energy storage device, so that the frequency of the clock signal is periodically changed, and the energy of the peak interference signal is dispersed through frequency jitter; the energy is distributed from discrete frequency points to a continuous interval, so that the amplitude of the fixed single-low point frequency is lowered, and the purpose of reducing electromagnetic interference is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a frequency jittering circuit and electrical equipment. Background Art

[0002] With the development of integrated circuit technology, current electrical equipment is optimized towards automation and intelligence. As a result, the circuit structure is becoming more and more complex, which in turn puts higher standards on the EMI (Electromagnetic Interference) of integrated circuits.

[0003] In traditional technology, electrical equipment involves circuits driven by fixed frequency signals, which can be output by crystal oscillator circuits or clock frequency generation circuits. However, if the operating frequency of the signal is fixed, it will generate large electromagnetic interference near the fixed frequency. If these interference signals are transmitted to other parts of the equipment through the transmission line, it will affect the normal operation of the equipment. In even worse cases, if they are transmitted to the power grid, they will interfere with the normal operation of other networked devices. Summary of the invention

[0004] Based on this, it is necessary to provide a frequency jittering circuit and electrical equipment to address the technical problem of electromagnetic interference caused by the fixed operating frequency of the signal in the above-mentioned electrical equipment.

[0005] A frequency jittering circuit, comprising:

[0006] An energy storage device, a first end of the energy storage device being connected to a target node;

[0007] A charging and discharging module, used for charging and discharging the energy storage device;

[0008] A clock signal output module, used for comparing the voltage of the target node with the target reference voltage to generate a clock signal, and providing the clock signal to the charge and discharge module to control the charging and discharging of the energy storage device;

[0009] The reference voltage generating module is used for cyclically outputting threshold voltages of different amplitudes as the target reference voltage provided to the clock signal output module to change the charge and discharge time of the energy storage device, thereby causing the frequency of the clock signal to change periodically.

[0010] In one of the embodiments, the reference voltage generating module includes a voltage dividing unit and a logic output unit;

[0011] The voltage dividing unit is used to generate a plurality of threshold voltages with different amplitudes;

[0012] The logic output unit is used to cyclically select threshold voltages of different amplitudes in sequence as target reference voltage outputs.

[0013] In one embodiment, the target reference voltage includes a first target reference voltage and a second target reference voltage, and the clock signal output module includes a first comparison unit, a second comparison unit and a latch unit.

[0014] The first comparison unit is used to output a first latch signal to the latch unit based on the voltage of the target node and the first target reference voltage;

[0015] The second comparison unit is used to output a second latch signal to the latch unit according to the voltage of the target node and the second target reference voltage;

[0016] The latch unit is used to output a clock signal according to the first latch signal and the second latch signal.

[0017] In one embodiment, the voltage dividing unit includes a first voltage dividing unit and a second voltage dividing unit, and the logic output unit includes a first logic output unit and a second logic output unit;

[0018] The first voltage dividing unit is used to generate a plurality of first threshold voltages with different amplitudes;

[0019] The first logic output unit is used for cyclically selecting first threshold voltages of different amplitudes in sequence as first target reference voltages to output to the first comparison unit;

[0020] The second voltage dividing unit is used to generate a plurality of second threshold voltages with different amplitudes;

[0021] The second logic output unit is used for cyclically selecting second threshold voltages of different amplitudes in sequence as second target reference voltages to output to the second comparison unit.

[0022] In one embodiment, the first logic output unit includes a gating element and a plurality of switch elements, the gating element includes a plurality of signal output terminals, one signal output terminal is correspondingly connected to a control terminal of a switch element, and the signal input terminal of the gating element is connected to a gating signal;

[0023] The gating element is used to cyclically turn on the switch elements in sequence under the control of the gating signal, so that the first threshold voltages with different amplitudes are cyclically transmitted to the first comparison unit in sequence through the switch elements.

[0024] In one embodiment, the second logic output unit includes an XOR gate, a D flip-flop, a first switch element, a second switch element and an inverter, the first input end of the XOR gate is connected to a selection signal, the second input end of the XOR gate is connected to a first end of the D flip-flop, the output end of the XOR gate is connected to a second end of the D flip-flop, the first end of the D flip-flop is connected to a control end of the first switch element, the first end of the D flip-flop is also connected to a control end of the second switch element through the inverter, and the third end of the D flip-flop is connected to the selection signal;

[0025] The second voltage dividing unit is used to generate two second threshold voltages with different amplitudes;

[0026] Under the control of the selection signal, the first switch element and the second switch element are alternately turned on, so that two second threshold voltages with different amplitudes are alternately transmitted to the second comparison unit.

[0027] In one embodiment, the selection signal is the clock signal.

[0028] In one embodiment, the first comparison unit includes a first comparator, the second comparison unit includes a second comparator, and the latch unit includes a first NOR gate and a second NOR gate;

[0029] A first end of the first comparator is connected to the output end of the logic output unit, a second end of the first comparator is connected to the first end of the energy storage device, a third end of the first comparator is connected to the first end of the first NOR gate, a second end of the first NOR gate is connected to the third end of the second NOR gate, a third end of the first NOR gate is connected to the first end of the second NOR gate, a first end of the second comparator is connected to the first end of the energy storage device, a second end of the second comparator is connected to the output end of the logic output unit, and a third end of the second comparator is connected to the second end of the second NOR gate.

[0030] In one embodiment, the charging and discharging module includes a reference current generating unit, a current transmitting unit and a switch unit, wherein the reference current generating unit is connected to the current transmitting unit, the current transmitting unit is connected to the first end of the energy storage device via the switch unit, and the control end of the switch unit is connected to the clock signal;

[0031] The reference current generating unit is used to generate a reference current;

[0032] Under the control of the clock signal, the switch unit is used to connect the reference current to charge the energy storage device, and is also used to ground the energy storage device to discharge.

[0033] In one embodiment, the reference current generating unit includes a first resistor, a first op amp and a first switch tube, the first input end of the first op amp is connected to a reference voltage, the second input end of the first op amp is connected to the first end of the first switch tube and is also grounded through the first resistor, the output end of the first op amp is connected to the control end of the first switch tube, and the second end of the first switch tube is connected to the current transfer unit.

[0034] In one embodiment, the current transfer unit includes a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube, the control ends of the second switch tube, the third switch tube and the fourth switch tube are connected to the second end of the first switch tube, the first end of the second switch tube is connected to the second end of the first switch tube, the second end of the second switch tube is connected to the second end of the third switch tube and the second end of the fourth switch tube, the first end of the third switch tube is connected to the control end and the second end of the fifth switch tube and the control end of the sixth switch tube, the first end of the fourth switch tube and the second end of the sixth switch tube are connected to the switch unit, and the first end of the fifth switch tube and the first end of the sixth switch tube are grounded.

[0035] In one embodiment, the switch unit includes a third switch element and a fourth switch element, the clock signal includes an inverted first clock signal and a second clock signal, the control end of the third switch element is connected to the first clock signal, the control ends of the fourth switch elements are connected to the second clock signal, the first end of the fourth switch tube is connected to the first end of the energy storage device through the third switch element, and the second end of the sixth switch tube is connected to the first end of the energy storage device through the fourth switch element.

[0036] In one embodiment, the energy storage device is a capacitor.

[0037] In one embodiment, an electrical device is provided, comprising the frequency jittering circuit as described in any of the above embodiments.

[0038] The above-mentioned frequency jittering circuit and electrical equipment include an energy storage device, a first end of the energy storage device is connected to the target node; a charging and discharging module, which is used to charge and discharge the energy storage device; a clock signal output module, which is used to compare the voltage of the target node with the target reference voltage to generate a clock signal, and provide it to the charging and discharging module to control the charging and discharging of the energy storage device; a reference voltage generating module, which is used to cyclically output threshold voltages of different amplitudes as target reference voltages provided to the clock signal output module to change the charging and discharging time of the energy storage device, thereby making the frequency of the clock signal change periodically, and dispersing the energy of the spike interference signal through frequency jittering, distributing the energy from discrete frequency points to a continuous interval, thereby lowering the amplitude of the fixed single low point frequency, so as to achieve the purpose of reducing electromagnetic interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A schematic diagram of a system block diagram of a frequency jittering circuit in an embodiment;

[0041] Figure 2 It is a schematic diagram of a system block diagram of a frequency jittering circuit in another embodiment;

[0042] Figure 3 A schematic diagram of a system block diagram of a frequency jittering circuit in another embodiment;

[0043] Figure 4 A schematic diagram of a partial circuit structure of a frequency jittering circuit in an embodiment;

[0044] Figure 5 is a schematic diagram of another circuit structure of a frequency jittering circuit in an embodiment;

[0045] Figure 6 Schematic diagram of the overall circuit structure of a frequency jittering circuit in one embodiment;

[0046] Figure 7 A schematic diagram of the working process of a charging and discharging module in one embodiment;

[0047] Figure 8 is a timing diagram of a clock signal in one embodiment;

[0048] Fig. 9 is a timing diagram of a clock signal in another embodiment;

[0049] Fig.10 This is a signal effect diagram before the frequency jitter circuit is applied in one embodiment;

[0050] Fig.11 FIG. 1 is a diagram showing the signal effect after the frequency jitter circuit is applied in one embodiment. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. The embodiments of the present application are given in the accompanying drawings, but the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0052] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0053] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0054] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0055] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0057] In an exemplary embodiment, Figure 1 As shown, a frequency jittering circuit is provided, including: an energy storage device 110, a first end of the energy storage device 110 is connected to a target node A; a charge and discharge module 120, used to charge and discharge the energy storage device 110; a clock signal output module 130, used to compare the voltage of the target node A with the target reference voltage to generate a clock signal CLOCK, and provide it to the charge and discharge module 120 to control the charging and discharging of the energy storage device 110; a reference voltage generating module 140, used to cyclically output threshold voltages of different amplitudes as a target reference voltage provided to the clock signal output module 130, so as to change the charging and discharging time of the energy storage device 110, thereby causing the frequency of the clock signal CLOCK to change periodically.

[0058] Specifically, the charge and discharge module 120 is connected to the first end of the energy storage device 110, and the second end of the energy storage device 110 is grounded or connected to a low voltage. The charge and discharge module 120 is used to switch the circuit connection relationship of the first end of the energy storage device 110, so that it is in a charging circuit or a discharging circuit, so as to charge and discharge the energy storage device 110. For example, when the charge and discharge module 120 connects the first end of the energy storage device 110 to the power supply end, the energy storage device 110 can be placed in a charging circuit to charge the energy storage device 110; when the charge and discharge module 120 connects the first end of the energy storage device 110 to form a discharging circuit, the energy storage device 110 can be discharged.

[0059] Exemplarily, the charge and discharge module 120 may include a current source or a current generating circuit to output a reference current to charge the energy storage device 110 . The charge and discharge module 120 may also be directly connected to an external power source to charge the energy storage device 110 .

[0060] It can be understood that the voltage of the target node A, that is, the voltage of the first terminal of the energy storage device 110 , may increase as the energy storage device 110 is charged, and may also decrease as the energy storage device 110 is discharged.

[0061] Further, the clock signal output module 130 can generate a clock signal CLOCK based on the comparison between the voltage of the target node A and the target reference voltage. At the same time, the clock signal CLOCK is also provided to the charge and discharge module 120 to control the charge and discharge state switching of the energy storage device 110. It can be understood that as the energy storage device 110 continues to charge, when the voltage charged to the target node A is greater than the target reference voltage, the clock signal CLOCK output by the clock signal output module 130 changes its level state and is provided to the charge and discharge module 120 to control the energy storage device 110 to switch to the discharge state. Further, as the energy storage device 110 continues to discharge, when the voltage discharged to the target node A is less than the target reference voltage, the clock signal CLOCK output by the clock signal output module 130 changes its level state again and is provided to the charge and discharge module 120 to control the energy storage device 110 to switch to the charge state. This cycle repeats to generate a clock signal CLOCK with a fixed frequency.

[0062] It should be noted that, although the target reference voltage used for comparison in the charging process and the target reference voltage used for comparison in the discharging process are both reference voltages, the voltage values ​​are different and can be understood as two reference voltages. In addition, the target reference voltage used for comparison in the charging process needs to be lower than the full-charge voltage of the energy storage device 110, and the target reference voltage used for comparison in the discharging process needs to be higher than the low-charge voltage of the energy storage device 110 to ensure that the clock signal output module 130 can change the level state of the clock signal CLOCK.

[0063] It can be understood that by designing the voltage amplitudes of the two target reference voltages according to the charge and discharge parameters of the energy storage device 110 to compare with the voltage of the target node A, a clock signal CLOCK of a required frequency is obtained.

[0064] Correspondingly, the reference voltage generation module 140 can output threshold voltages of different amplitudes, which are provided as target reference voltages to the clock signal output module 130 to adjust the frequency of the obtained clock signal CLOCK. Further, when multiple threshold voltages of different amplitudes are cyclically provided to the clock signal output module 130 in a fixed order, a clock signal CLOCK with a periodically changing frequency can be obtained.

[0065] Exemplarily, the reference voltage generating module 140 may be implemented by a voltage source, or by a voltage divider circuit, or by other voltage generating methods well known to those skilled in the art, as long as it can output multiple voltages of different amplitudes.

[0066] The above-mentioned frequency jittering circuit cyclically outputs threshold voltages of different amplitudes as the target reference voltage through the reference voltage generating module, and provides it to the clock signal output module to change the charging and discharging time of the energy storage device, thereby making the frequency of the clock signal change periodically. The energy of the peak interference signal is dispersed through frequency jittering, and the energy is distributed from discrete frequency points to a continuous interval, thereby lowering the amplitude of the fixed single low point frequency, so as to achieve the purpose of reducing electromagnetic interference.

[0067] In an exemplary embodiment, Figure 2 As shown, the reference voltage generating module 140 includes a voltage dividing unit 141 and a logic output unit 142; the voltage dividing unit 141 is used to generate a plurality of threshold voltages with different amplitudes; the logic output unit 142 is used to cyclically select threshold voltages with different amplitudes as target reference voltage outputs.

[0068] The voltage dividing unit 141 may realize voltage division through a resistor, or through a capacitor, or through a combination of a resistor and a capacitor.

[0069] Specifically, the voltage dividing unit 141 can be a device that divides voltage by connecting resistors of different resistance values ​​in series, and then outputs threshold voltages of different amplitudes through the common point of each resistor. The voltage dividing unit 141 can also be a device that divides voltage by connecting capacitors of different capacitance values ​​in series and in parallel, and then outputs threshold voltages of different amplitudes through the voltage dividing output nodes in the assembly. The voltage dividing unit 141 can also be a device that divides voltage by connecting resistors and capacitors in series or in parallel, and then outputs threshold voltages of different amplitudes through the corresponding voltage dividing output nodes.

[0070] Furthermore, the logic output unit 142 can be implemented by a logic gate circuit, and then the logic gate circuit is controlled in combination with a selection signal to realize cyclically selecting threshold voltages of different amplitudes as target reference voltage outputs. The specific structural form of the logic gate circuit is not limited, as long as the above functions can be realized. Of course, the logic output unit 142 can also be implemented by devices such as a counter or a data selector, and the output ports of the above devices are cyclically turned on in combination with the level change of the selection signal, so that threshold voltages of different amplitudes are output as target reference voltages.

[0071] Exemplarily, in order to output a target reference voltage for comparison during the charging process and a target reference voltage for comparison during the discharging process, the logic output unit 142 can select two threshold voltages of multiple different amplitudes output by the voltage divider unit 141 for output, or two groups of voltage divider units 141 and logic output units 142 can be correspondingly set to output two target reference voltages respectively.

[0072] In an exemplary embodiment, Figure 3As shown, the target reference voltage includes a first target reference voltage Vref1 and a second target reference voltage Vref2, and the clock signal output module 130 includes a first comparison unit 131, a second comparison unit 132 and a latch unit 133. The first comparison unit 131 is used to output a first latch signal to the latch unit 133 based on the voltage of the target node A and the first target reference voltage Vref1; the second comparison unit 132 is used to output a second latch signal to the latch unit 133 based on the voltage of the target node A and the second target reference voltage Vref2; the latch unit 133 is used to output the clock signal CLOCK according to the first latch signal and the second latch signal.

[0073] Among them, the first comparison unit 131 and the second comparison unit 132, one is used to control the energy storage device 110 to switch to a charging state, and the other is used to control the energy storage device 110 to switch to a discharging state. The latch unit 133 is used to jump the level state of the output clock signal CLOCK when receiving any one of the first latch signal and the second latch signal. The latch unit 133 can be implemented by using an SR latch or other devices that can realize signal state latching.

[0074] In an example, the process of the clock signal output module 130 outputting the clock signal CLOCK is explained by taking the first comparison unit 131 connected to the first target reference voltage Vref1 for comparison during charging and the second comparison unit 132 connected to the second target reference voltage Vref2 for comparison during discharging as an example.

[0075] As the energy storage device 110 continues to charge, when the voltage charged to the target node A is greater than the first target reference voltage Vref1, the first comparison unit 131 outputs a first latch signal to the latch unit 133, so that the clock signal CLOCK output by the latch unit 133 changes its level state, and is provided to the charge and discharge module 120, so as to control the energy storage device 110 to switch to the discharge state. As the energy storage device 110 continues to discharge, when the voltage discharged to the target node A is less than the second target reference voltage Vref2, the second comparison unit 132 outputs a second latch signal to the latch unit 133, so that the clock signal CLOCK output by the latch unit 133 changes its level state, and is provided to the charge and discharge module 120, so as to control the energy storage device 110 to switch to the charge state.

[0076] In an exemplary embodiment, two groups of voltage dividers 141 and logic output units 142 are provided to output two target reference voltages respectively, so as to achieve the frequency change of the clock signal CLOCK. Figure 3The voltage dividing unit 141 includes a first voltage dividing unit 1411 and a second voltage dividing unit 1412, and the logic output unit 142 includes a first logic output unit 1421 and a second logic output unit 1422; the first voltage dividing unit 1411 is used to generate a plurality of first threshold voltages with different amplitudes; the first logic output unit 1421 is used to cyclically select first threshold voltages with different amplitudes in sequence as the first target reference voltage Vref1 and output to the first comparison unit 131; the second voltage dividing unit 1412 is used to generate a plurality of second threshold voltages with different amplitudes; the second logic output unit 1422 is used to cyclically select second threshold voltages with different amplitudes in sequence as the second target reference voltage Vref2 and output to the second comparison unit 132.

[0077] Among them, the implementation means of the first voltage divider unit 1411 and the second voltage divider unit 1412 can refer to the implementation means description of the voltage divider unit 141 above, and the implementation means of the first logic output unit 1421 and the second logic output unit 1422 can refer to the implementation means description of the logic output unit 142 above, which will not be repeated here.

[0078] It can be understood that in order to control circuit cost and simplify circuit structure, the number of first threshold voltages can be set to multiple, and the number of second threshold voltages can be set to a smaller number such as one or two, and multiple first threshold voltages can be combined with the second threshold voltage in sequence for output, and then as long as the gating can be achieved to obtain multiple groups of first target reference voltage Vref1 and second target reference voltage Vref2, it will be sufficient.

[0079] In one example, the number of first threshold voltages is multiple, and correspondingly, the first logic output unit includes a gating element and multiple switching elements, the gating element includes multiple signal output terminals, one signal output terminal corresponds to the control terminal of a switching element, and the signal input terminal of the gating element is connected to the gating signal; the gating element is used to cyclically turn on each switching element in turn under the control of the gating signal, so that the first threshold voltages of different amplitudes are cyclically transmitted to the first comparison unit through each switching element in turn.

[0080] The gating element can be used to select multiple first threshold voltages as the first target reference voltage Vref1, and can be a logic gate circuit, a data selector, or a counter. Figure 4 As shown, the gating element is implemented by a counter. The type of switch element that can be selected is not limited, and can be a mechanical electric tube, an electronic switch, a micro switch or a switch tube device, as long as it can switch the conduction state according to the input signal of the control end.

[0081] Specifically, the gating element has a signal input terminal for receiving a gating signal. The gating element has multiple signal output terminals for connecting control terminals of multiple switch elements, and each switch element is connected in series on the transmission path from each first threshold voltage to the first comparison unit. Furthermore, under the control of the gating signal, the gating element can sequentially turn on each switch element through its signal output terminal, so that the first threshold voltages of different amplitudes are cyclically transmitted to the first comparison unit in sequence through each switch element.

[0082] In one example, the number of the second threshold voltages is two, referring to Figure 4 The second logic output unit includes an XOR gate, a D flip-flop D, a first switch element (switch S5), a second switch element (switch S6) and an inverter NOR. The first input end of the XOR gate is connected to the selection signal, the second input end of the XOR gate is connected to the first end of the D flip-flop D, the output end of the XOR gate is connected to the second end of the D flip-flop D, the first end of the D flip-flop is connected to the control end of the first switch element (switch S5), the first end of the D flip-flop is also connected to the control end of the second switch element (switch S6) through the inverter NOR, and the third end of the D flip-flop D is connected to the selection signal; the second voltage dividing unit is used to generate two second threshold voltages with different amplitudes; under the control of the selection signal, the first switch element (switch S5) and the second switch element (switch S6) are alternately turned on, so that the two second threshold voltages with different amplitudes are alternately transmitted to the second comparison unit.

[0083] Among them, the first end of the D trigger D is the Q end, which is used to connect the second input end of the XOR gate XOR and the control end of the two switch elements. According to the principle of the D trigger, its Q end is the output signal holding terminal, which can keep the output signal unchanged until the next trigger signal arrives, and then the alternating conduction of the two switch elements can be controlled according to the level state of the Q end. The second end of the D trigger D is the D end, which is used to connect the output end of the XOR gate XOR to control the next state change of the D trigger. The third end of the D trigger D is the clock signal end, which is used to access the selection signal as a trigger signal. It can be understood that the D trigger mentioned in this application can be triggered according to the change of the level state of the selection signal, or it can be triggered according to the leading edge (positive jump 0→1) in the selection signal. In this embodiment, when the rising edge in the selection signal arrives, the level state of the Q end of the D trigger jumps.

[0084] Specifically, in the first time period, assuming that the level state of the current selection signal is switched to 1, the level states of the two input terminals of the exclusive OR gate XOR are (1, 0), the level state of the output terminal is 1, and the clock signal terminal of the D flip-flop D is connected to the selection signal and the level state becomes 1 (rising edge), then the Q terminal output of the D flip-flop D becomes 1 and remains until the next rising edge of the selection signal arrives, the high level output of the Q terminal turns on the switch S5, and passes through the NOT gate NOR to turn off the switch S6, at this time, the second threshold voltage connected to the first switch element (switch S5) is output as the second target reference voltage Vref2.

[0085] In the second period, the level state of the selection signal is switched to 0, the level states of the two input terminals of the XOR gate XOR are (0, 1), the level state of the output terminal is 1, and the clock signal terminal of the D flip-flop D is connected to the selection signal without a rising edge change, then the Q terminal of the D flip-flop D remains at 1, and still outputs a high level to turn on the switch S5, and turns off the switch S6 through the NOT gate NOR. At this time, the second threshold voltage connected to the first switch element (switch S5) is still output as the second target reference voltage Vref2.

[0086] In the third period, the level state of the selection signal is switched to 1, the level states of the two input terminals of the exclusive OR gate XOR are (1, 1), and the level state of the output terminal is 0. The clock signal terminal of the D flip-flop D is connected to the selection signal and the level state becomes 1 (rising edge). Then the Q terminal output of the D flip-flop D becomes 0 and remains until the next rising edge of the selection signal. The low level output at the Q terminal turns off the switch S5 and turns on the switch S6 through the NOT gate NOR. At this time, the second threshold voltage connected to the second switch element (switch S6) is output as the second target reference voltage Vref2.

[0087] In the fourth time period, the level state of the selection signal is switched to 0, the level states of the two input terminals of the XOR gate XOR are (0, 0), the level state of the output terminal is 0, and the clock signal terminal of the D flip-flop D is connected to the selection signal without a rising edge change, then the Q terminal of the D flip-flop D remains at 0, and still outputs a low level to disconnect the switch S5, and turns on the switch S6 through the NOT gate NOR. At this time, the second threshold voltage connected to the second switch element (switch S6) is still output as the second target reference voltage Vref2.

[0088] Thereafter, the circuit state is cycled back to the first time period, and this cycle repeats to achieve the alternate conduction of the first switch element (switch S5) and the second switch element (switch S6), so that two second threshold voltages with different amplitudes are alternately transmitted to the second comparison unit.

[0089] It can be understood that the gating signal can be a square wave signal, and then when the level of the gating signal jumps, the gating element is controlled to change through the signal output end to turn on the switch element connected to the next signal input end. The gating signal can also be a control signal of multiple amplitudes, and then when the voltage amplitude of the gating signal changes, the gating element is controlled to change through the signal output end to turn on the switch element connected to the next signal input end. In the embodiment of the present application, refer to Figure 4 In order to save signal routing costs, the selection signal is implemented using the clock signal CLOCK.

[0090] In an exemplary embodiment, referring to Figure 4 The first comparison unit includes a first comparator COMP1, the second comparison unit includes a second comparator COMP2, and the latch unit includes a first NOR gate NAND1 and a second NOR gate NAND2; a first end of the first comparator COMP1 is connected to the output end of the logic output unit, a second end of the first comparator COMP1 is connected to the first end of the energy storage device, a third end of the first comparator COMP1 is connected to the first end of the first NOR gate NAND1, a second end of the first NOR gate NAND1 is connected to the third end of the second NOR gate NAND2, a third end of the first NOR gate NAND1 is connected to the first end of the second NOR gate NAND2, a first end of the second comparator COMP2 is connected to the first end of the energy storage device, a second end of the second comparator COMP2 is connected to the output end of the logic output unit, and a third end of the second comparator COMP2 is connected to the second end of the second NOR gate NAND2.

[0091] Among them, refer to Figure 4 The first end of the first comparator COMP1 is connected to the switch elements of the first logic output unit for accessing the first target reference voltage Vref1. The second end of the second comparator COMP2 is connected to the switch elements of the second logic output unit for accessing the second target reference voltage Vref2. The second end of the first comparator COMP1 and the first end of the second comparator COMP2 are connected to the target node A.

[0092] It should be noted that the clock signal CLOCK can be the first clock signal outputted from the output end of the first NOR gate NAND1, or the second clock signal outputted from the second NOR gate NAND2. The present application takes the first clock signal outputted from the output end of the first NOR gate NAND1 as the clock signal CLOCK as an example for explanation. It can be understood that the first clock signal and the second clock signal are inverted signals.

[0093] In an exemplary embodiment, Figure 5As shown, the charge and discharge module 120 includes a reference current generating unit 121, a current transfer unit 122 and a switch unit 123, the reference current generating unit 121 is connected to the current transfer unit 122, the current transfer unit 122 is connected to the first end of the energy storage device 110 via the switch unit 123, and the control end of the switch unit 123 is connected to the clock signal; the reference current generating unit 121 is used to generate a reference current; under the control of the clock signal CLOCK, the switch unit 123 is used to connect the reference current to charge the energy storage device 110, and is also used to ground the energy storage device 110 for discharge.

[0094] Specifically, after the reference current generating unit 121 generates the reference current, the current transmitting unit 122 transmits the reference current to the switch unit 123. The switch unit 123 can control the charging and discharging of the energy storage device 110. The method can be that when the switch unit 123 is in the on or off state, the charging and discharging of the energy storage device 110 are respectively realized, or when a plurality of switch elements are included and different switch elements are in the on state, the charging and discharging of the energy storage device 110 are respectively realized.

[0095] Exemplarily, the switch unit 123 may be implemented by a PMOS tube and an NMOS tube, and then under different level states of the clock signal CLOCK, the PMOS tube and the NMOS tube will be turned on respectively to realize charging or discharging of the energy storage device 110. The switch unit 123 may also be implemented by two trigger switches, and the control ends of the two trigger switches are respectively connected to the first clock signal output by the first NOR gate NAND1 and the second clock signal output by the second NOR gate NAND2, and then under the control of the two clock signals being turned on respectively, the energy storage device 110 is charged or discharged.

[0096] In an exemplary embodiment, referring to Figure 5 The reference current generating unit 121 includes a first resistor R, a first op amp EA and a first switch tube M1. The first input end of the first op amp EA is connected to the reference voltage Vref, the second input end of the first op amp EA is connected to the first end of the first switch tube M1 and is also grounded through the first resistor R, the output end of the first op amp EA is connected to the control end of the first switch tube M1, and the second end of the first switch tube M1 is connected to the current transfer unit 122.

[0097] In an exemplary embodiment, referring to Figure 5The current transfer unit 122 includes a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5 and a sixth switch tube M6. The control ends of the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 are connected to the second end of the first switch tube M1, the first end of the second switch tube M2 is connected to the second end of the first switch tube M1, the second end of the second switch tube M2 is connected to the second end of the third switch tube M3 and the second end of the fourth switch tube M4, the first end of the third switch tube M3 is connected to the control end and the second end of the fifth switch tube M5 and the control end of the sixth switch tube M6, the first end of the fourth switch tube M4 and the second end of the sixth switch tube M6 are connected to the switch unit, and the first end of the fifth switch tube M5 and the first end of the sixth switch tube M6 are grounded.

[0098] The first switch tube M1 , the second switch tube M2 , the third switch tube M3 , the fourth switch tube M4 , the fifth switch tube M5 and the sixth switch tube M6 are all NMOS tubes.

[0099] In an exemplary embodiment, referring to Figure 5 The switch unit 123 includes a third switch element (switch S1) and a fourth switch element (switch S2), the clock signal includes an inverted first clock signal and a second clock signal, the control end of the third switch element (switch S1) is connected to the first clock signal, and the control ends of the fourth switch element (switch S2) are connected to the second clock signal, the first end of the fourth switch tube M4 is connected to the first end of the energy storage device 110 through the third switch element (switch S1), and the second end of the sixth switch tube M6 is connected to the first end of the energy storage device 110 through the fourth switch element (switch S2).

[0100] The first input terminal of the first operational amplifier EA is the non-inverting input terminal of the first operational amplifier EA, and the second input terminal of the first operational amplifier EA is the inverting input terminal of the first operational amplifier EA.

[0101] Specifically, the reference current generating unit 121 is a constant current source set by using the virtual short and virtual short principle of the operational amplifier. After the first input terminal of the first operational amplifier EA is connected to the reference voltage Vref as the load, the output voltage of the first operational amplifier EA can change with the change of the load impedance, but its current does not change with the change of the load, so that the constant current source can be designed by combining the first resistor R, the first operational amplifier EA and the first switch tube M1 to output the reference current.

[0102] It can be understood that the magnitude of the reference current can be determined by the resistance value of the first resistor R, and the resistance value of the first resistor R can be designed according to the required magnitude of the reference current and the amplitude of the reference voltage Vref.

[0103] Furthermore, after the reference current generating unit 121 generates the reference current, the second switch tube M2, the third switch tube M3, and the fourth switch tube M4 can be turned on through the first switch tube M1, and then transmitted to the third switch tube M3 and the fourth switch tube M4 through the second switch tube M2. Then, the reference current flowing through the third switch tube M3 can control the fifth switch tube M5 and the sixth switch tube M6 to be turned on.

[0104] In the process of controlling the energy storage device 110 to charge and discharge, when the third switch element (switch S1) is closed due to the first clock signal connected to the control end, and the fourth switch element (switch S2) is disconnected due to the second clock signal connected to the control end, the energy storage device 110 can obtain a reference current to charge; when the third switch element (switch S1) is disconnected due to the first clock signal connected to the control end, and the fourth switch element (switch S2) is closed due to the second clock signal connected to the control end, the energy storage device 110 can be grounded to discharge.

[0105] The energy storage device 110 can be implemented by any device that can store energy, as long as it can be charged and discharged. Figure 5 , the energy storage device 110 is a capacitor C.

[0106] In a specific embodiment, the frequency jittering circuit provided in the present application is explained by taking a first threshold voltage having two amplitudes and a second threshold voltage having two amplitudes as an example.

[0107] like Figure 6 As shown, a frequency jittering circuit is provided, including a first resistor R, a first operational amplifier EA, a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a switch S1, a switch S2, a capacitor C, a first comparator COMP1, a second comparator COMP2, a first NOR gate NAND1, a second NOR gate NAND2, an XOR gate XOR, a D trigger D, a switch S3, a switch S4, a switch S5, a switch S6, an inverter NOR1, an inverter NOR2, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a resistor R5.

[0108] A first input end of the first operational amplifier EA is connected to a reference voltage Vref, a second input end of the first operational amplifier EA is connected to a first end of the first switch tube M1, and is also grounded through a first resistor R, an output end of the first operational amplifier EA is connected to a control end of the first switch tube M1, control ends of the second switch tube M2, the third switch tube M3, and the fourth switch tube M4 are connected to a second end of the first switch tube M1, a first end of the second switch tube M2 is connected to a second end of the first switch tube M1, a second end of the second switch tube M2 is connected to a second end of the third switch tube M3, and a second end of the fourth switch tube M4, a first end of the third switch tube M3 is connected to a control end and a second end of the fifth switch tube M5, and a control end of the sixth switch tube M6, a first end of the fourth switch tube M4 is connected to a first end (target node A) of the capacitor C through a switch S1, a second end of the sixth switch tube M6 is connected to a first end (target node A) of the capacitor C through a switch S2, and a second end of the capacitor C, a first end of the fifth switch tube M5, and a first end of the sixth switch tube M6 are grounded.

[0109] The non-inverting input terminal of the first comparator COMP1 is connected to the first terminal of the switch S3 and the first terminal of the switch S4, the inverting input terminal of the first comparator COMP1 is connected to the target node A, the output terminal of the first comparator COMP1 is connected to the first input terminal of the first NOR gate NAND1, the second input terminal of the first NOR gate NAND1 is connected to the output terminal of the second NOR gate NAND2, the output terminal of the first NOR gate NAND1 is connected to the first input terminal of the second NOR gate NAND2, the non-inverting input terminal of the second comparator COMP2 is connected to the target node A, the inverting input terminal of the second comparator COMP2 is connected to the first terminal of the switch S5 and the first terminal of the switch S6, and the output terminal of the second comparator COMP2 is connected to the second input terminal of the second NOR gate NAND2. The output terminal of the first NOR gate NAND1 is also connected to the control terminal of the switch S1, and the output terminal of the second NOR gate NAND2 is also connected to the control terminal of the switch S2.

[0110] Resistors R1, R2, R3, R4 and R5 are connected in series to form a voltage divider unit. After the series connection, the other end of resistor R1 is connected to the power supply terminal VDD, and the other end of resistor R5 is grounded. The common end of resistor R1 and resistor R2 is used as the output end of threshold voltage V1, connected to the second end of switch S3, and used to be transmitted to the non-inverting input end of the first comparator COMP1 as the first target reference voltage Vref1. The common end of resistor R2 and resistor R3 is used as the output end of threshold voltage V2, connected to the second end of switch S4, and used to be transmitted to the non-inverting input end of the first comparator COMP1 as the first target reference voltage Vref1. The common end of resistor R3 and resistor R4 is used as the output end of threshold voltage V3, connected to the second end of switch S5, and used to be transmitted to the inverting input end of the second comparator COMP2 as the second target reference voltage Vref2. The common end of resistor R4 and resistor R5 is used as the output end of threshold voltage V4, connected to the second end of switch S6, and used to be transmitted to the inverting input end of the second comparator COMP2 as the second target reference voltage Vref2.

[0111] The control end of switch S3 is directly connected to the clock signal CLOCK for control, and the control end of switch S4 is controlled by the clock signal CLOCK through inverter NOR2. The first input end of the XOR gate XOR is connected to the clock signal CLOCK, the second input end of the XOR gate XOR is connected to the Q end of the D flip-flop D, the output end of the XOR gate XOR is connected to the D end of the D flip-flop D, the Q end of the D flip-flop D is connected to the control end of switch S5, the Q end of the D flip-flop D is also connected to the control end of switch S6 through inverter NOR1, and the clock signal end of the D flip-flop D is connected to the clock signal CLOCK.

[0112] It is understandable that Figure 7 As shown in the flowchart, when the frequency-jittering circuit is started, the reference current generated conducts the fourth switch tube M4 and the sixth switch tube M6. Assuming that the initial state is that the switch S1 is closed and the switch S2 is open, the working current is provided to the capacitor C for charging. When the voltage charged to the target node A is higher than the first target reference voltage Vref1, the switch S1 is switched to open, the switch S2 is switched to close, and the capacitor C begins to discharge. When the voltage discharged to the target node A is lower than the second target reference voltage Vref2, the switch S2 is switched to open, the switch S1 is switched to close, and the cycle repeats to generate a clock signal CLOCK. Among them, the period of the clock signal CLOCK is the sum of the charging time and the discharging time of the capacitor C, that is:

[0113] T = C (Vref1-Vref2) / I cha +C (Vref1-Vref2) / I dis

[0114] Wherein, T is the period of the clock signal CLOCK, C is the capacitance of the capacitor C, Vref1 and Vref2 are the voltage values ​​of the first target reference voltage and the second target reference voltage, I cha is the charging current of capacitor C, I dis is the discharge current of the capacitor C. When the voltage values ​​of the first target reference voltage and the second target reference voltage are fixed, the period of the generated clock signal CLOCK will be fixed, and the frequency is also a fixed frequency, such as Figure 8 shown.

[0115] Furthermore, different threshold voltages can be obtained by connecting resistors of different resistance values ​​in series, for example Figure 6 By controlling the switch S3-S5 to be turned on in a cycle, different threshold voltages are selected to be input to the first comparator COMP1 and the second comparator COMP2, so as to control the charge and discharge time of the capacitor C, thereby changing the frequency of the clock signal CLOCK and realizing the frequency jittering function. The frequency diagram is shown in FIG. Fig. 9 shown.

[0116] The following is attached Figure 6 The specific working process of the corresponding frequency jitter circuit:

[0117] 1. When the clock signal CLOCK outputs a high level, switch S3 is turned on. After the clock signal CLOCK passes through the inverter NOR2, switch S4 is turned off. At this time, Vref1=V1; after the high level output by the clock signal CLOCK passes through the XOR gate, the input end of the XOR gate is (1, 0), and the output end is 1. The clock signal end of the D flip-flop becomes a high level due to the access to the clock signal CLOCK, so that the Q end of the D flip-flop outputs 1 and remains until the next clock signal rising edge arrives. The high level output of the Q end controls switch S5 to turn on, and controls switch S6 to turn off through the inverter NOR1. At this time, Vref2=V3. The clock cycle T1 is: T1=C(V1-V3) / I cha +C(V1-V3) / I dis .

[0118] 2. When the clock signal CLOCK changes from high level to low level, switch S3 is turned off. After the clock signal CLOCK passes through inverter NOR2, switch S4 is turned on. At this time, Vref1=V2; after the low level output of the clock signal CLOCK passes through the XOR gate XOR, the input end of the XOR gate XOR is (0, 1), and the output end is 1. The clock signal CLOCK connected to the clock signal end of the D flip-flop has no rising edge change, and the Q end of the D flip-flop does not change to 1. It still controls switch S5 to turn on, and controls switch S6 to turn off through inverter NOR1. At this time, Vref2=V3, and the clock period T2 is: T2=C(V2-V3) / Icha +C(V2-V3) / I dis .

[0119] 3. When the clock signal CLOCK changes from low level to high level, switch S3 is turned on. After the clock signal CLOCK passes through inverter NOR2, switch S4 is turned off. At this time, Vref1=V1; after the high level output of the clock signal CLOCK passes through the XOR gate, the input end of the XOR gate is (1, 1), and the output is 0. The clock signal CLOCK connected to the clock signal end of the D flip-flop becomes high level, making the Q end output of the D flip-flop become 0 and remain until the next rising edge of the clock signal. The high level output of the Q end controls switch S5 to turn off, and controls switch S6 to turn on through inverter NOR1. At this time, Vref2=V4, and the clock period T3 is: T3=C(V1-V4) / I cha +C (V1-V4) / I dis .

[0120] 4. When the clock signal CLOCK changes from high level to low level, switch S3 is disconnected. After the clock signal CLOCK passes through inverter NOR2, switch S4 is turned on. At this time, Vref1=V2; after the low level output of the clock signal CLOCK passes through the XOR gate XOR, the input end of the XOR gate XOR is (0, 0), and the output end is 1. The clock signal CLOCK connected to the clock signal end of the D flip-flop has no rising edge change, and the Q end of the D flip-flop does not change to 0. The switch S5 is still controlled to be disconnected, and the switch S6 is controlled to be turned on through the inverter NOR1. At this time, Vref2=V4, and the clock cycle T4 is: T4=C(V2-V4) / I cha +C(V2-V4) / I dis .

[0121] In this embodiment, multiple threshold voltages are obtained by dividing the voltages of multiple resistors, and the reference voltage of the comparator is changed by continuously changing the threshold voltage to control the output of the comparator, change the clock frequency, and realize the frequency jitter function, thereby solving the problem that the current frequency jitter function requires the addition of additional modules, occupies a large area, and is difficult to implement. At the same time, the threshold voltage selection control is realized through the clock signal output by the frequency oscillation circuit, and different threshold voltages are cyclically selected to change the reference voltage of the comparator at a low cost.

[0122] In an exemplary embodiment, an electrical device is provided, comprising the frequency jittering circuit according to any of the above embodiments.

[0123] It can be understood that the frequency jittering circuit can convert any fixed-frequency driving signal in the electrical equipment into a signal with a periodic frequency change. It disperses the energy of the peak interference signal through frequency jittering, distributes the energy from discrete frequency points to a continuous interval, and then lowers the amplitude of the fixed single low-point frequency, so as to achieve the purpose of reducing electromagnetic interference.

[0124] Before applying the frequency jitter circuit provided in this application to a certain electrical device, Fig.10 It can be seen that the driving signal contains more spike interference signals. After the frequency jitter circuit provided by the present application is used for driving, Fig.11 It can be seen that the crystal oscillator frequency doubling points of the driving signal have been improved, and the distribution has been flattened from the spike signal frequency point to a continuous interval, which can obviously achieve the purpose of reducing electromagnetic interference.

[0125] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0126] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A frequency jittering circuit, characterized in that: include: An energy storage device, a first end of the energy storage device being connected to a target node; A charging and discharging module, used for charging and discharging the energy storage device; A clock signal output module, used for comparing the voltage of the target node with the target reference voltage to generate a clock signal, and providing the clock signal to the charge and discharge module to control the charging and discharging of the energy storage device; The reference voltage generating module is used for cyclically outputting threshold voltages of different amplitudes as the target reference voltage provided to the clock signal output module to change the charge and discharge time of the energy storage device, thereby causing the frequency of the clock signal to change periodically.

2. The frequency jittering circuit according to claim 1, characterized in that: The reference voltage generating module comprises a voltage dividing unit and a logic output unit; The voltage dividing unit is used to generate a plurality of threshold voltages with different amplitudes; The logic output unit is used to cyclically select threshold voltages of different amplitudes in sequence as target reference voltage outputs.

3. The frequency jittering circuit according to claim 2, characterized in that: The target reference voltage includes a first target reference voltage and a second target reference voltage, and the clock signal output module includes a first comparison unit, a second comparison unit and a latch unit. The first comparison unit is used to output a first latch signal to the latch unit based on the voltage of the target node and the first target reference voltage; The second comparison unit is used to output a second latch signal to the latch unit according to the voltage of the target node and the second target reference voltage; The latch unit is used to output a clock signal according to the first latch signal and the second latch signal.

4. The frequency jittering circuit according to claim 3, characterized in that: The voltage dividing unit includes a first voltage dividing unit and a second voltage dividing unit, and the logic output unit includes a first logic output unit and a second logic output unit; The first voltage dividing unit is used to generate a plurality of first threshold voltages with different amplitudes; The first logic output unit is used for cyclically selecting first threshold voltages of different amplitudes in sequence as first target reference voltages to output to the first comparison unit; The second voltage dividing unit is used to generate a plurality of second threshold voltages with different amplitudes; The second logic output unit is used for cyclically selecting second threshold voltages of different amplitudes in sequence as second target reference voltages to output to the second comparison unit.

5. The frequency jittering circuit according to claim 4, characterized in that: The first logic output unit includes a gating element and a plurality of switch elements, the gating element includes a plurality of signal output terminals, one signal output terminal is correspondingly connected to a control terminal of a switch element, and the signal input terminal of the gating element is connected to a gating signal; The gating element is used to cyclically turn on the switch elements in sequence under the control of the gating signal, so that the first threshold voltages with different amplitudes are cyclically transmitted to the first comparison unit in sequence through the switch elements.

6. The frequency jittering circuit according to claim 4, characterized in that: The second logic output unit comprises an XOR gate, a D flip-flop, a first switch element, a second switch element and an inverter, the first input end of the XOR gate is connected to a selection signal, the second input end of the XOR gate is connected to a first end of the D flip-flop, the output end of the XOR gate is connected to a second end of the D flip-flop, the first end of the D flip-flop is connected to a control end of the first switch element, the first end of the D flip-flop is also connected to a control end of the second switch element through the inverter, and the third end of the D flip-flop is connected to the selection signal; The second voltage dividing unit is used to generate two second threshold voltages with different amplitudes; Under the control of the selection signal, the first switch element and the second switch element are alternately turned on, so that two second threshold voltages with different amplitudes are alternately transmitted to the second comparison unit.

7. The frequency jittering circuit according to claim 5 or 6, characterized in that: The selection signal is the clock signal.

8. The frequency jittering circuit according to claim 3, characterized in that: The first comparison unit includes a first comparator, the second comparison unit includes a second comparator, and the latch unit includes a first NOR gate and a second NOR gate; A first end of the first comparator is connected to the output end of the logic output unit, a second end of the first comparator is connected to the first end of the energy storage device, a third end of the first comparator is connected to the first end of the first NOR gate, a second end of the first NOR gate is connected to the third end of the second NOR gate, a third end of the first NOR gate is connected to the first end of the second NOR gate, a first end of the second comparator is connected to the first end of the energy storage device, a second end of the second comparator is connected to the output end of the logic output unit, and a third end of the second comparator is connected to the second end of the second NOR gate.

9. The frequency jittering circuit according to claim 1, characterized in that: The charging and discharging module comprises a reference current generating unit, a current transmitting unit and a switch unit, wherein the reference current generating unit is connected to the current transmitting unit, the current transmitting unit is connected to the first end of the energy storage device via the switch unit, and the control end of the switch unit is connected to the clock signal; The reference current generating unit is used to generate a reference current; Under the control of the clock signal, the switch unit is used to connect the reference current to charge the energy storage device, and is also used to ground the energy storage device to discharge.

10. The frequency jittering circuit according to claim 9, characterized in that: The reference current generating unit includes a first resistor, a first op amp and a first switch tube. The first input end of the first op amp is connected to a reference voltage. The second input end of the first op amp is connected to the first end of the first switch tube and is also grounded through the first resistor. The output end of the first op amp is connected to the control end of the first switch tube. The second end of the first switch tube is connected to the current transfer unit.

11. The frequency jittering circuit according to claim 10, characterized in that: The current transfer unit includes a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube. The control ends of the second switch tube, the third switch tube and the fourth switch tube are connected to the second end of the first switch tube. The first end of the second switch tube is connected to the second end of the first switch tube. The second end of the second switch tube is connected to the second end of the third switch tube and the second end of the fourth switch tube. The first end of the third switch tube is connected to the control end and the second end of the fifth switch tube and the control end of the sixth switch tube. The first end of the fourth switch tube and the second end of the sixth switch tube are connected to the switch unit. The first end of the fifth switch tube and the first end of the sixth switch tube are grounded.

12. The frequency jittering circuit according to claim 11, characterized in that: The switch unit includes a third switch element and a fourth switch element, the clock signal includes an inverted first clock signal and a second clock signal, the control end of the third switch element is connected to the first clock signal, the control ends of the fourth switch elements are connected to the second clock signal, the first end of the fourth switch tube is connected to the first end of the energy storage device through the third switch element, and the second end of the sixth switch tube is connected to the first end of the energy storage device through the fourth switch element.

13. The frequency jittering circuit according to claim 1, characterized in that: The energy storage device is a capacitor.

14. An electrical device, characterized in that: It comprises the frequency jittering circuit as claimed in any one of claims 1 to 13.

Images