Inner lead structure of flexible circuit board
By setting a redundant line between the internal lead between the soft circuit board and uniformly, the internal lead spacing is solved, and the problem of uneven flow of the etching liquid is solved, and the effect of the internal lead width is evenly distributed and the shape of the cross -section shape is achieved.
Patent Information
- Application Number
- CN202311151464.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-25
- Filing Date
- 2023-09-07
- Publication Date
- 2025-01-28
AI Technical Summary
The internal lead spacing of the flexible circuit board is inconsistent, resulting in uneven flow rate of the etching liquid, which in turn causes problems such as uneven distribution of the internal lead width and irregular cross-sectional shape.
Set a redundant line between the internal leaders with a large spacing to make the spatial spacing between the internal leaders be less than 50um, thereby uniformly to the flow rate of the etching solution.
By reducing the problem of uneven flow of etching solution, the etching of the internal lead is etched into a trapezoid, ensuring that the width distribution of the internal leadership is evenly distributed and the horizontal -cut shape is uniformly distributed.
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Figure CN119383834A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a flexible circuit board, in particular to an inner lead structure of the flexible circuit board. Background Art
[0002] A flexible printed circuit board is a flexible printed circuit board. A flexible printed circuit board is flexible in installation and is very suitable for today's thin and light electronic products. Generally, a flexible printed circuit board has a flexible substrate and a patterned circuit on the flexible substrate. The flexible substrate has a chip setting area for chip setting, and part of the patterned circuit will also extend to the chip setting area to connect with multiple bumps of the chip to provide signal transmission. The patterned circuit that extends to the chip setting area is called an inner lead. Since the main purpose of the inner lead is to provide electrical connection between the chip and the rest of the patterned circuit, the spacing between the bumps on the chip depends on their function and the arrangement method. Therefore, the spacing between the bumps is not equal, which also causes the spacing distribution between the inner leads to be quite inconsistent.
[0003] The patterned circuits on the flexible substrate are formed by wet etching, which uses flowing etching liquid to etch the metal layer not covered by the patterned photoresist, leaving the metal layer covered by the patterned photoresist. Therefore, when the spacing distribution between the inner leads is inconsistent, the flow rate of the etching liquid will be uneven due to the different sizes of the channel space of the patterned photoresist. The uneven flow rate of the etching liquid will cause the metal layer to be etched to different degrees, which will lead to uneven distribution of the width of the inner leads. What's worse, the cross-section of the inner leads with larger spacing will be etched into a trapezoid with narrow top and wide bottom due to the faster flow rate of the etching liquid. Summary of the invention
[0004] The main purpose of the present invention is to set redundant circuits between inner leads with larger spacing, so that the spacing between the inner leads is less than 50um, so as to avoid the problem of uneven etching liquid flow rate.
[0005] The present invention discloses an inner lead structure of a flexible circuit board, comprising a flexible circuit board, a circuit layer and a redundant circuit layer. The flexible circuit board has an upper surface, the upper surface has a chip setting area, the chip setting area is used to set a chip, the chip has a plurality of conductive elements, the plurality of conductive elements are set on a plurality of conductive points in the chip setting area, the circuit layer is set on the upper surface, the circuit layer has a plurality of inner leads, the connection end of each inner lead is located in the chip setting area, each of the connection ends is set on each of the conductive points and each of the conductive elements is electrically connected, there is a space between two adjacent inner leads, and the inner leads are connected to each other by a plurality of conductive elements. In the embodiment, the spacing between some of the spaces is greater than 50um, and the spacing between some of the spaces is not greater than 50um. The redundant circuit layer is arranged on the upper surface, and the redundant circuit layer has a plurality of first redundant circuits, and none of the plurality of first redundant circuits are electrically connected to any of the conductive elements. At least one of the first redundant circuits is arranged in the space with a spacing greater than 50um so that the space is divided into a plurality of spaces with a spacing less than 50um, wherein the number of the remaining spaces without the first redundant circuits and with a spacing greater than 50um accounts for less than 0.5% of the number of all the spaces.
[0006] Preferably, the redundant circuit layer has at least one second redundant circuit, and the second redundant circuit is not electrically connected to any of the conductive elements. The second redundant circuit is arranged in the space where the spacing is greater than 50um. The second redundant circuit divides the space into the space where the spacing is not greater than 50um and the space where the spacing is greater than 50um. The cross-section of the second redundant circuit is trapezoidal.
[0007] Preferably, the redundant circuit layer has at least two second redundant circuits, and the two second redundant circuits are arranged in the same space with a spacing greater than 50um. The two second redundant circuits are divided into a plurality of spaces with a spacing of no more than 50um and a space with a spacing greater than 50um. Each space with a spacing of no more than 50um is located between each second redundant circuit and each inner lead, and the space with a spacing greater than 50um is located between the second redundant circuits.
[0008] Preferably, each of the inner leads has a first exposed surface and a first connecting surface, the first connecting surface is connected to the upper surface of the flexible circuit board, and the difference between the width of the first connecting surface and the width of the first exposed surface is less than 2 um.
[0009] Preferably, each second redundant circuit has a second exposed surface and a second connecting surface, the second connecting surface is connected to the upper surface of the flexible circuit board, the width of the second connecting surface is greater than the width of the second exposed surface, and the difference between the width of the second connecting surface and the width of the second exposed surface is greater than 2um.
[0010] Preferably, the cross section of each of the inner leads adjacent to the second redundant circuit is rectangular.
[0011] Preferably, the ratio of the largest spacing to the smallest spacing in the space is less than 6.
[0012] Preferably, the width of each of the first redundant circuits is between 6 and 100 um, and the length of each of the first redundant circuits is greater than 70 um.
[0013] Preferably, each of the first redundant circuits has a first line segment and a second line segment, the first line segment and the second line segment are parallel to each of the inner leads, and there is a clearance space between the first line segment and the second line segment, and the width of the clearance space is between 10 and 30 um.
[0014] Preferably, a plurality of the first redundant circuits are disposed in the space with a spacing greater than 50 um so that the space is divided into a plurality of spaces with a spacing not greater than 50 um.
[0015] The present invention divides the space into a plurality of spaces with a spacing of no more than 50 um by setting at least one first redundant circuit in the space with a spacing of more than 50 um, so that the number of the remaining spaces without the first redundant circuit and with a spacing of more than 50 um accounts for less than 0.5% of the number of all the spaces, thereby reducing the problem of a faster flow rate of the etching liquid in the space with a larger spacing, thereby preventing the inner lead from being etched into a trapezoid. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 : A top view of an inner lead structure of a flexible printed circuit board according to one embodiment of the present invention.
[0017] Figure 2 : A cross-sectional view of an inner lead structure of a flexible printed circuit board according to one embodiment of the present invention.
[0018] Figure 3 : A partially enlarged view of the inner lead structure of a flexible printed circuit board according to the first embodiment of the present invention.
[0019] Figure 4 : A partial cross-sectional view of the inner lead structure of the flexible circuit board according to the first embodiment of the present invention.
[0020] Figure 5 : A partial enlarged view of the inner lead structure of a flexible printed circuit board according to the second embodiment of the present invention.
[0021] Figure 6 : A partial enlarged view of the inner lead structure of a flexible printed circuit board according to the third embodiment of the present invention.
[0022] Figure 7: A partial enlarged view of the inner lead structure of a flexible printed circuit board according to the fourth embodiment of the present invention.
[0023] Figure 8 : A partial cross-sectional view of the inner lead structure of the flexible printed circuit board according to the fourth embodiment of the present invention.
[0024]
Main component symbol description
[0025] 100: Inner lead structure of flexible printed circuit board 110: Flexible printed circuit board
[0026] 111: Upper surface 111a: Chip setting area
[0027] 111b: Transmission line setting area 111c: External lead setting area
[0028] 111d: contact point 120: circuit layer
[0029] 121: inner lead 121a: connection end
[0030] 121b: first exposed surface 121c: first connection surface
[0031] 122: Transmission line 123: External lead
[0032] 130: Redundant circuit layer 131: First redundant circuit
[0033] 131a: first line segment 131b: second line segment
[0034] 132: second redundant line 132a: second exposed surface
[0035] 132b: Second connection surface C: Chip
[0036] B: Conducting element S: Space
[0037] BS: Make way space W: Width
[0038] L: Length DETAILED DESCRIPTION
[0039] See also Figure 1, which is an embodiment of the present invention, a top view of an inner lead structure 100 of a flexible circuit board, the inner lead structure 100 of the flexible circuit board includes a flexible circuit board 110, a circuit layer 120 and a redundant circuit layer 130, the flexible circuit board 110 has an upper surface 111, the circuit layer 120 and the redundant circuit layer 130 are both arranged on the upper surface 111, the circuit layer 120 and the redundant circuit layer 130 in the figure are shown as a whole blank, but in fact the circuit layer 120 and the redundant circuit layer 130 are composed of a number of fine circuits. Among them, the redundant circuit layer 130 located on both sides of the circuit layer 120 does not provide signal transmission, but is used to increase the strength of the flexible circuit board 110, so as to facilitate the flexible circuit board 110 to perform different processes.
[0040] See also Figure 1 and Figure 2 , Figure 2 1 is a cross-sectional view of the inner lead structure 100 of the flexible printed circuit board. The upper surface 111 of the flexible printed circuit board 110 can be divided into a chip setting area 111a, a transmission line setting area 111b and an outer lead setting area 111c. The chip setting area 111a is located near the center of the upper surface 111, the outer lead setting area 111c is located at the upper and lower edges of the upper surface 111, and the transmission line setting area 111b is located between the chip setting area 111a and the outer lead setting area 111c. The chip setting area 111a is used to set a chip C. The chip C has a plurality of conductive elements B. The plurality of conductive elements B are set on a plurality of conductive points 111d in the chip setting area 111a. The plurality of conductive elements B are bumps or solder balls pre-formed on the chip C, but the present invention is not limited thereto.
[0041] The circuit layer 120 has a plurality of inner leads 121, a plurality of transmission lines 122, and a plurality of outer leads 123. The plurality of inner leads 121 are adjacent to the chip setting area 111a and partially extend into the chip setting area 111a. The plurality of outer leads 123 are located in the outer lead setting area 111c. The plurality of transmission lines 122 are located in the transmission line setting area 111b. The two ends of each transmission line 122 are respectively connected to each inner lead 121 and each outer lead 123 to provide electrical connection between each inner lead 121 and each outer lead 123. The plurality of inner leads 121, the plurality of transmission lines 122, and the plurality of outer leads 123 are formed by copper foil electroplated on the upper surface 111 through pattern etching.
[0042] See also Figure 2 and Figure 3 , Figure 3The figure is a partial enlarged view of the chip setting area 111a of the first embodiment of the inner lead structure 100 of the flexible printed circuit. The area above the horizontal dotted line in the figure is the chip setting area 111a where the chip is set, and the area below the horizontal dotted line is the transmission line setting area 111b. The portion of the inner lead 121 extending into the chip setting area 111a is defined as the connection end 121a of each inner lead 121. Each connection end 121a is disposed on each conductive contact point 111d, and is electrically connected to each conductive element B when the chip C is disposed in the chip setting area 111a. The conductive elements B of the chip C can be an alloy of tin and other metals. When the chip C is disposed in the chip setting area 111a by thermal compression, the conductive ends 121a of each inner lead 121 can be eutectic connected with each conductive element B, so that the chip C is electrically connected to the circuit layer 120. In this embodiment, there is a space S between two adjacent inner leads 121. Based on the different spacings between the conductive elements B of the chip C, the spacing of some of the spaces S is greater than 50um, while the spacing of some of the spaces S is not greater than 50um. Figure 3 Only one space with a pitch greater than 50 um is disclosed, but in fact the entire chip setting area 111a has multiple spaces with a pitch greater than 50 um due to the layout design of the multiple conductive elements B of the chip C. Figure 3 It is only a partial schematic diagram.
[0043] See also Figure 3 The redundant circuit layer 130 further has a plurality of first redundant circuits 131, and the plurality of first redundant circuits 131 are not electrically connected to any of the conductive elements B. At least one of the first redundant circuits 131 is disposed in the space S with a spacing greater than 50um so that the space S is divided into a plurality of spaces S with a spacing not greater than 50um, so that the number of the remaining spaces S without the first redundant circuit 131 and with a spacing greater than 50um accounts for less than 0.5% of the number of all the spaces S, and the ratio of the largest spacing to the smallest spacing in the space S is less than 6, thereby allowing the spaces between the circuits adjacent to the chip setting area 111a to be approximated.
[0044] Since the plurality of inner leads 121, the plurality of transmission lines 122 and the plurality of outer leads 123 are formed by wet etching, therefore, in this embodiment, by arranging the plurality of first redundant circuits 131 in the space S with a spacing greater than 50um, the ratio of the spacing of the space S between the plurality of inner leads 121 being not greater than 50um is greater than 99.5%, so that the flow rate of the etching liquid in the etching process through the space S between the plurality of inner leads 121 is similar, thereby avoiding the problem of uneven line width caused by different etching degrees of each inner lead 121. In addition, since the spacing of the space S between the plurality of inner leads 121 is not greater than 50um, the flow rate of the etching liquid through the space S is relatively slow, so that the cross-sections of the plurality of inner leads 121 and the plurality of first redundant circuits 131 are all rectangular, thereby avoiding the cross-section of the inner lead 121 being etched into a trapezoid with a narrow top and a wide bottom due to the excessive flow rate of the etching liquid.
[0045] See also Figure 4 Since the wet etching is isotropic etching, the cross-sections of the multiple inner leads 121 and the multiple first redundant circuits 131 actually formed are not rectangular in geometry, but have outer contours that are approximately rectangular. The rectangle described in this specification is defined as follows: each of the inner leads 121 has a first exposed surface 121b and a first connecting surface 121c, and the first connecting surface 121c is connected to the upper surface 111 of the flexible circuit board 110. The difference between the width of the first connecting surface 121c and the width of the first exposed surface 121b is less than 2um. Similarly, the difference between the width of the connecting surface and the exposed surface of each of the first redundant circuits 131 is also less than 2um, so that its outer contour is approximately rectangular.
[0046] For better, see Figure 3 The width W of each first redundant circuit 131 is between 6 and 100 um, and the length L of each first redundant circuit 131 is greater than 70 um, so as to avoid each first redundant circuit 131 affecting the fluidity of the bottom filling glue under the subsequent chip and prevent the stress of the flexible circuit board 110 from being too concentrated due to the setting of each first redundant circuit 131.
[0047] See also Figure 5, which is a second embodiment of the present invention, a partial enlarged view of the inner lead structure 100 of the flexible printed circuit board. In this embodiment, each of the first redundant circuits 131 has a first line segment 131a and a second line segment 131b, and the first line segment 131a and the second line segment 131b are parallel to each of the inner leads 121. There is a clearance space BS between the first line segment 131a and the second line segment 131b, and the width of the clearance space BS is between 10 and 30 um. In this embodiment, each of the first redundant circuits 131 is divided into two separate line segments, and the clearance space BS between the two line segments can be used for the bottom filling glue to pass through, which can further prevent each of the first redundant circuits 131 from affecting the flow of the bottom filling glue.
[0048] See also Figure 6 , which is the third embodiment of the present invention, a partial enlarged view of the inner lead structure 100 of the flexible printed circuit board. Since the spacing of the space S greater than 50um is relatively large, in this embodiment, a plurality of the first redundant circuits 131 are arranged in a single space S with a spacing greater than 50um so that the space S is divided into a plurality of spaces S with a spacing not greater than 50um. Arranging a plurality of the first redundant circuits 131 in a single space S with a spacing greater than 50um can reduce the width of each of the first redundant circuits 131, so as to avoid the problem of excessive concentration of stress on the flexible printed circuit board 110 due to the wider first redundant circuit 131, thereby causing peeling during thermal pressing of the chip C.
[0049] See also Figure 7 , which is the fourth embodiment of the present invention, the redundant circuit layer 130 has at least one second redundant circuit 132, the second redundant circuit 132 is not electrically connected to any of the conductive elements B, the second redundant circuit 132 is arranged in the space S with a spacing greater than 50um, and the second redundant circuit 132 divides the space S into the space S with a spacing not greater than 50um and the space S with a spacing greater than 50um. Due to the limitation of the circuit layout, this embodiment cannot divide the space S with a spacing greater than 50um into multiple spaces S with a spacing not greater than 50um by setting one or more of the first redundant circuits 131. Therefore, the second redundant circuit 132 is set in the space S as a sacrificial circuit to protect the multiple inner leads 121. Please refer to Figure 8In the wet etching process, the flow rate of the etching liquid in the space S with a spacing greater than 50um divided by the second redundant circuit 132 will be faster, but the flow rate of the etching liquid in the space S with a spacing less than 50um divided by the second redundant circuit 132 will be slower. Therefore, although the cross-section of the second redundant circuit 132 will be etched into a trapezoid with a narrow upper part and a wide lower part due to the faster flow rate of the etching liquid, the inner lead 121 adjacent to the second redundant circuit 132 will be adjacent to the space S with a spacing less than 50um due to the second redundant circuit 132. Therefore, the flow rate of the etching liquid for etching the inner lead 121 will not be too fast, so that the cross-section of the inner lead 121 adjacent to the second redundant circuit 132 is still a rectangle.
[0050] The second redundant circuit 132 is etched into a trapezoid as a sacrificial circuit in the present embodiment. Therefore, the second redundant circuit 132 has a second exposed surface 132a and a second connecting surface 132b. The second connecting surface 132b is connected to the upper surface 111 of the flexible circuit board 110. The width of the second connecting surface 132b is greater than the width of the second exposed surface 132a, and the difference between the width of the second connecting surface 132b and the width of the second exposed surface 132a is greater than 2um.
[0051] Please refer to Figure 7 and Figure 8 Since each space S is located between two inner leads 121, if there is only one second redundant circuit 132 in the space S, although the inner lead 121 adjacent to the second redundant circuit 132 can be protected by the second redundant circuit 132, the inner lead 121 located on the other side farther from the second redundant circuit 132 will still be affected by the etching liquid with a faster flow rate. Therefore, preferably, in this embodiment, the redundant circuit layer 130 has at least two second redundant circuits 132, and the two second redundant circuits 132 are arranged in the same space S with a spacing greater than 50um. The two second redundant circuits 132 divide the space S into a plurality of spaces S with a spacing not greater than 50um and spaces S with a spacing greater than 50um. Each space S with a spacing not greater than 50um is located between each second redundant circuit 132 and each inner lead 121, and the space S with a spacing greater than 50um is located between the second redundant circuits 132. In this embodiment, the second redundant circuit 132 divides the space S so that the inner leads 121 originally located on both sides of the space S are adjacent to the space S with a spacing of no more than 50 um, thereby avoiding being etched by an etching solution with a faster flow rate during etching, thereby preventing the cross-section of the multiple inner leads 121 from being etched into a trapezoid.
[0052] The present invention divides the space S into a plurality of spaces S with a pitch not greater than 50um by setting at least one first redundant circuit 131 in the space S with a pitch greater than 50um, so that the number of the remaining spaces S without the first redundant circuit 131 and with a pitch greater than 50um accounts for less than 0.5% of the number of all the spaces S, thereby reducing the problem of faster flow rate of the etching liquid in the space with a larger pitch, thereby preventing the inner lead 121 from being etched into a trapezoid.
[0053] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.
Claims
1. An inner lead structure of a flexible circuit board, characterized in that: Include: The flexible circuit board has an upper surface, the upper surface has a chip setting area, the chip setting area is used to set the chip, the chip has a plurality of conductive elements, and the plurality of conductive elements are set on a plurality of conductive points in the chip setting area; A circuit layer is disposed on the upper surface, the circuit layer has a plurality of inner leads, the connection end of each inner lead is located in the chip setting area, each connection end is disposed on each conductive point and each conductive element is electrically connected, and there is a space between two adjacent inner leads, wherein the spacing of some of the spaces is greater than 50um, and the spacing of some of the spaces is not greater than 50um; as well as A redundant circuit layer is arranged on the upper surface, and the redundant circuit layer has a plurality of first redundant circuits, and the plurality of first redundant circuits are not electrically connected to any of the conductive elements. At least one of the first redundant circuits is arranged in the space with a spacing greater than 50um so that the space is divided into a plurality of spaces with a spacing not greater than 50um, wherein the number of the remaining spaces without the first redundant circuits and with a spacing greater than 50um accounts for less than 0.5% of the number of all the spaces.
2. The inner lead structure of the flexible printed circuit board according to claim 1, characterized in that: The redundant circuit layer has at least one second redundant circuit, and the second redundant circuit is not electrically connected to any of the conductive elements. The second redundant circuit is arranged in the space where the spacing is greater than 50um. The second redundant circuit divides the space into the space where the spacing is not greater than 50um and the space where the spacing is greater than 50um. The cross-section of the second redundant circuit is trapezoidal.
3. The inner lead structure of the flexible printed circuit board according to claim 2, characterized in that: The redundant circuit layer has at least two second redundant circuits, and the two second redundant circuits are arranged in the same space with a spacing greater than 50um. The two second redundant circuits are divided into a plurality of spaces with a spacing not greater than 50um and a space with a spacing greater than 50um. Each space with a spacing not greater than 50um is located between each second redundant circuit and each inner lead, and the space with a spacing greater than 50um is located between the second redundant circuits.
4. The inner lead structure of the flexible printed circuit board according to claim 2 or 3, characterized in that: Each of the inner leads has a first exposed surface and a first connecting surface. The first connecting surface is connected to the upper surface of the flexible circuit board. The difference between the width of the first connecting surface and the width of the first exposed surface is less than 2 um.
5. The inner lead structure of the flexible printed circuit board according to claim 4, characterized in that: Each of the second redundant circuits has a second exposed surface and a second connecting surface, the second connecting surface is connected to the upper surface of the flexible circuit board, the width of the second connecting surface is greater than the width of the second exposed surface, and the difference between the width of the second connecting surface and the width of the second exposed surface is greater than 2um.
6. The inner lead structure of the flexible printed circuit board according to claim 2 or 3, characterized in that: The cross section of each of the inner leads adjacent to the second redundant circuit is rectangular.
7. The inner lead structure of the flexible printed circuit board according to claim 1, characterized in that: The ratio of the largest spacing to the smallest spacing in the space is less than 6.
8. The inner lead structure of the flexible printed circuit board according to claim 1, characterized in that: The width of each of the first redundant circuits is between 6 and 100 um, and the length of each of the first redundant circuits is greater than 70 um.
9. The inner lead structure of the flexible printed circuit board according to claim 1, characterized in that: Each of the first redundant circuits has a first line segment and a second line segment, the first line segment and the second line segment are parallel to each of the inner leads, and there is a clearance space between the first line segment and the second line segment, and the width of the clearance space is between 10 and 30 um.
10. The inner lead structure of the flexible printed circuit board according to claim 1, characterized in that: A plurality of the first redundant circuits are arranged in the space with a spacing greater than 50 um so that the space is divided into a plurality of spaces with a spacing not greater than 50 um.