Formation method of semiconductor device

Abstract

The invention provides a method for forming a semiconductor device. The method comprises the following steps of: forming a shallow trench isolation structure higher than the surface of a floating gate layer in a substrate in a peripheral region; etching partial width of the shallow trench isolation structure to enable the height of the shallow trench isolation structure above the floating gate layer to reach the standard and the width of the shallow trench isolation structure to be reduced, so that a step appears on the side surface of the shallow trench isolation structure; forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer covers the step of the shallow trench isolation structure; forming a control gate layer and a word line penetrating through the control gate layer and the floating gate layer on the surface of the gate dielectric layer in the storage area; a first control gate side wall is formed on the surface of the gate dielectric layer in the storage area, a second control gate side wall covering the side wall of the shallow trench isolation structure is formed on the surface of the gate dielectric layer in the peripheral area, and the second control gate side wall is located at the step of the shallow trench isolation structure; and removing parts of the gate dielectric layer, the floating gate layer and the liner oxide layer which are not covered, and exposing part of the surface of the substrate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor device. Background Art

[0002] Some memory semiconductors are divided into a memory region for forming a memory device and a peripheral region for forming related peripheral circuits.

[0003] Please refer to Figure 1 The memory semiconductor device of the prior art includes: a pad oxide layer 102, a floating gate layer 103, a gate dielectric layer 104 and a control gate layer 105 are sequentially formed on the surface of a substrate 101 in the storage area, and a first spacer 106 is formed on the surface of the control gate layer 105. A second spacer 107 is formed in the opening of the first spacer 106, and the second spacer covers the sidewalls of the pad oxide layer 102, the sidewalls of the floating gate layer 103, the sidewalls of the gate dielectric layer 104 and the sidewalls of the control gate layer 105, and the top end is connected to the first spacer 106, and the bottom end is connected to the substrate 101. The first spacer 106 and the second spacer 107 form a source line opening, and a source line 108 is formed in the source line opening. A control gate spacer 109 is formed on the outside of the source line, and the control gate spacer 109 is used to isolate the control gate from the word line formed subsequently. A shallow trench isolation structure 110 is formed in the substrate of the peripheral area, and the surface of the shallow trench isolation structure 110 is higher than the surface of the substrate 101. The sidewalls of the shallow trench isolation structure 110 are inclined, that is, the shallow trench isolation structure 110 is wide at the top and narrow at the bottom.

[0004] However, when the floating gate and control gate sidewalls 109 are formed in the storage area, they are still formed simultaneously in the peripheral area, and then the control gate sidewalls 109 and floating gate layer 103 in the peripheral area are removed by etching. However, since the shallow trench isolation structure 110 is inclined, the control gate sidewalls 109 will remain in the corners of the outer wall. Due to the obstruction of the control gate sidewalls 109, the floating gate layer 103 under the control gate sidewalls 109 cannot be removed cleanly, and appears as a continuous and uninterrupted long strip. The residue of the floating gate layer 103 caused the failure of the standby current in the product CP1 test. Summary of the invention

[0005] The object of the present invention is to provide a method for forming a semiconductor device, which can completely remove the floating gate layer in the peripheral area and reduce the failure rate of CP1 test.

[0006] In order to achieve the above object, the present invention provides a method for manufacturing a memory, comprising:

[0007] providing a substrate, dividing the substrate into adjacent storage areas and peripheral areas;

[0008] forming a pad oxide layer and a floating gate layer in sequence on the surface of the substrate;

[0009] forming a shallow trench isolation structure in the substrate of the peripheral region, wherein the surface of the shallow trench isolation structure is higher than the surface of the floating gate layer;

[0010] Etching a shallow trench isolation structure of a portion of height and a shallow trench isolation structure of a portion of width, so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure;

[0011] forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer simultaneously covers the step of the shallow trench isolation structure;

[0012] A control gate layer and a word line passing through the control gate layer and the floating gate layer are formed on the surface of the gate dielectric layer in the storage area, a first spacer is also formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second spacer;

[0013] A first control gate sidewall is formed on the surface of the gate dielectric layer in the storage area, the first control gate sidewall covers the first sidewall and the sidewall of the control gate layer, and at the same time, a second control gate sidewall is formed on the surface of the gate dielectric layer in the peripheral area, the second control gate sidewall covers the sidewall of the shallow trench isolation structure, and the second control gate sidewall is located at the step of the shallow trench isolation structure;

[0014] The uncovered portions of the gate dielectric layer, the floating gate layer and the pad oxide layer are removed to expose a portion of the surface of the substrate.

[0015] Optionally, in the method for manufacturing the memory, a method for forming a shallow trench isolation structure in the substrate of the peripheral region, wherein the surface of the shallow trench isolation structure is higher than the surface of the floating gate layer, comprises:

[0016] forming a sacrificial oxide layer on a surface of the floating gate layer;

[0017] Sequentially etching a portion of the sacrificial oxide layer, the floating gate layer, the pad oxide layer and the substrate in the peripheral region to form a shallow trench in the substrate;

[0018] Filling oxide into the shallow trench to form a shallow trench isolation structure;

[0019] The sacrificial oxide layer is removed.

[0020] Optionally, in the method for manufacturing the memory, the substrate includes a wafer.

[0021] Optionally, in the method for manufacturing the memory, the gate dielectric layer includes an ONO layer.

[0022] Optionally, in the method for manufacturing the memory, the floating gate layer and the control gate layer both include polysilicon.

[0023] Optionally, in the manufacturing method of the memory, a control gate layer and a word line passing through the control gate layer and the floating gate layer are formed on the surface of the gate dielectric layer in the storage area, a first spacer is further formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second spacer, comprising:

[0024] forming a control gate layer and a hard mask on a surface of the gate dielectric layer, wherein the hard mask has a first opening;

[0025] forming a first side wall in the first opening;

[0026] removing the control gate layer, the gate dielectric layer, the floating gate layer and the pad oxide layer not covered by the first sidewall spacer to expose the surface of the substrate;

[0027] forming a second sidewall spacer, wherein the second sidewall spacer covers the sidewall of the control gate layer, the sidewall of the gate dielectric layer, the sidewall of the floating gate layer and the sidewall of the pad oxide layer, and the first sidewall spacer and the second sidewall spacer form a source line opening;

[0028] A source line is formed in the source line opening.

[0029] Optionally, in the method for manufacturing the memory, the method for forming a source line in the source line opening includes:

[0030] Filling the source line opening with polysilicon to form a source line.

[0031] Optionally, in the method for manufacturing the memory, the pad oxide layer includes oxide.

[0032] Optionally, in the method for manufacturing the memory, the first spacer, the first control gate spacer and the second control gate spacer all include oxide.

[0033] Optionally, in the method for manufacturing the memory, the second sidewall spacer includes nitride.

[0034] The method for forming a semiconductor device provided by the present invention comprises: providing a substrate, dividing the substrate into adjacent storage areas and peripheral areas; forming a pad oxide layer and a floating gate layer on the surface of the substrate in sequence; forming a shallow trench isolation structure in the substrate in the peripheral area, wherein the surface of the shallow trench isolation structure is higher than the surface of the floating gate layer; etching a shallow trench isolation structure of a part of height and a shallow trench isolation structure of a part of width, so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure; forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer simultaneously covers the steps of the shallow trench isolation structure .... A control gate layer and a word line passing through the control gate layer and the floating gate layer are formed on the surface of the gate dielectric layer in the storage area, a first sidewall is also formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second sidewall; a first control gate sidewall is formed on the surface of the gate dielectric layer in the storage area, the first control gate sidewall covers the first sidewall and the sidewall of the control gate layer, and at the same time, a second control gate sidewall is formed on the surface of the gate dielectric layer in the peripheral area, the second control gate sidewall covers the sidewall of the shallow trench isolation structure, and the second control gate sidewall is located at the step of the shallow trench isolation structure; the uncovered part of the gate dielectric layer, the floating gate layer and the liner oxide layer are removed to expose part of the surface of the substrate. The shallow trench isolation structure formed by the present invention has a step, and the formed second control gate sidewall covers the step, so when removing the floating gate layer in the peripheral area, it will not be blocked by the second control gate sidewall, thereby removing the floating gate layer in the peripheral area cleanly, reducing the failure rate of the CP1 test. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the structure of a semiconductor device in the prior art;

[0036] Figure 2 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0037] Figures 3 to 7 is a schematic structural diagram of a semiconductor device during formation according to an embodiment of the present invention;

[0038] In the figure: 101-substrate, 102-liner oxide layer, 103-floating gate layer, 104-gate dielectric layer, 105-control gate layer, 106-first sidewall, 107-second sidewall, 108-source line, 109-control gate sidewall, 110-shallow trench isolation structure, 201-substrate, 201A-storage area, 201B-peripheral area, 202-liner oxide layer, 203-floating gate layer, 204-shallow trench isolation structure, 205-first oxide layer, 206-nitride layer, 207-second oxide layer, 208-control gate layer, 209-first sidewall, 210-second sidewall, 211-source line, 212-first control gate sidewall, 213-second control gate sidewall. DETAILED DESCRIPTION

[0039] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0040] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0041] Furthermore, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0042] Please refer to Figure 2 The present invention provides a method for manufacturing a memory, comprising:

[0043] S11: providing a substrate, and dividing the substrate into adjacent storage areas and peripheral areas;

[0044] S12: forming a pad oxide layer and a floating gate layer in sequence on the surface of the substrate;

[0045] S13: forming a shallow trench isolation structure in the substrate of the peripheral region, wherein a surface of the shallow trench isolation structure is higher than a surface of the floating gate layer;

[0046] S14: etching a shallow trench isolation structure of a part of its height and a shallow trench isolation structure of a part of its width, so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and its width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure;

[0047] S15: forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer also covers the step of the shallow trench isolation structure;

[0048] S16: forming a control gate layer and a word line passing through the control gate layer and the floating gate layer on the surface of the gate dielectric layer in the storage region, wherein a first spacer is further formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second spacer;

[0049] S17: forming a first control gate sidewall on the surface of the gate dielectric layer in the storage region, the first control gate sidewall covering the first sidewall and the sidewall of the control gate layer, and forming a second control gate sidewall on the surface of the gate dielectric layer in the peripheral region, the second control gate sidewall covering the sidewall of the shallow trench isolation structure, and the second control gate sidewall being located at a step of the shallow trench isolation structure;

[0050] S18: removing uncovered portions of the gate dielectric layer, the floating gate layer, and the pad oxide layer to expose a portion of the surface of the substrate.

[0051] Please refer to Figure 3 First, a substrate 201 is provided. The substrate 201 may be a silicon substrate, such as a wafer. The substrate is divided into adjacent storage areas 201A and peripheral areas 201B. Next, a pad oxide layer 202 is formed on the surface of the substrate 201. The material of the pad oxide layer 202 may be silicon dioxide and may be formed by deposition. Next, a floating gate layer 203 is formed on the surface of the pad oxide layer 202. The material of the floating gate layer 203 may be polysilicon and may be formed by deposition. Next, a sacrificial oxide layer is formed on the surface of the floating gate layer 203. The material of the sacrificial oxide layer may be silicon dioxide and may be formed by deposition. The sacrificial oxide layer, the floating gate layer 203, the pad oxide layer 202 and a portion of the thickness of the substrate 201 are etched downward from the surface of the sacrificial oxide layer, and the etching is stopped in the substrate 201, thereby forming a shallow trench in the substrate 201, and the shallow trench is filled with oxide to form a shallow trench isolation structure 204. Next, the sacrificial oxide layer is removed, so that the surface of the shallow trench isolation structure 204 is higher than the surface of the floating gate layer 203. Moreover, the height of the shallow trench isolation structure 204 at this time is higher than the height of the final shallow trench isolation structure 204.

[0052] Next, please refer to Figure 4 , a shallow trench isolation structure 204 of a partial height and a shallow trench isolation structure 204 of a partial width are etched, so that the height of the shallow trench isolation structure 204 located above the floating gate layer 203 meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure 204.

[0053] Next, please refer to Figure 5, a gate dielectric layer is formed on the surface of the floating gate layer 203, and the gate dielectric layer is an ONO layer. Specifically, the gate dielectric layer includes a first oxide layer 205, a nitride layer 206, and a second oxide layer 207. The materials of the first oxide layer 205 and the second oxide layer 207 can be silicon dioxide, and the material of the nitride layer 206 can be silicon nitride. The method for forming the gate dielectric layer can be a method of sequentially depositing the first oxide layer 205, the nitride layer 206, and the second oxide layer 207. Then, a control gate layer 208 and a hard mask are formed on the surface of the second oxide layer 207. The material of the control gate layer 208 is polysilicon. The hard mask is etched to form a first opening penetrating the hard mask in the hard mask. Then, a first sidewall 209 is formed on the sidewall of the hard mask in the first opening. Then, the control gate layer 117, the gate dielectric layer, the floating gate layer 203, and the pad oxide layer 202 that are not covered by the first sidewall 209 in the first opening are etched to expose the surface of the substrate 201. Next, a second spacer 210 is formed, and the second spacer 210 covers the sidewalls of the control gate layer 207, the sidewalls of the gate dielectric layer, the sidewalls of the floating gate layer, and the sidewalls of the pad oxide layer 202. The top of the second spacer 210 is connected to the first spacer 209, and the bottom is connected to the surface of the substrate 201. A source line opening is formed between the first spacer 209 and the second spacer 210. Next, polysilicon is filled in the source line opening, and the surface of the polysilicon is polished, so that a source line 211 is formed in the source line opening.

[0054] Next, please refer to Figure 6 A first control gate sidewall 212 is formed on the surface of the gate dielectric layer in the storage area 201A, and the first control gate sidewall 212 covers the first sidewall 209 and the sidewall of the control gate layer 208. At the same time, a second control gate sidewall 213 is formed on the surface of the gate dielectric layer in the peripheral area 201B, and the second control gate sidewall 213 covers the sidewall of the shallow trench isolation structure 204. The second control gate sidewall 213 is located at the step of the shallow trench isolation structure 204.

[0055] Next, please refer to Figure 7 , remove the uncovered portions of the gate dielectric layer, the floating gate layer 203 and the liner oxide layer 202 in the storage area 201A and the peripheral area 201B, exposing a portion of the surface of the substrate 201. At this time, since the second control gate sidewall 213 is on the step of the shallow trench isolation structure 204 and does not cover the floating gate layer 203, the floating gate layer 203 in the peripheral area 201B can be completely removed.

[0056] In summary, in the method for forming a semiconductor device provided in an embodiment of the present invention, the method includes: providing a substrate, dividing the substrate into adjacent storage areas and peripheral areas; forming a liner oxide layer and a floating gate layer in sequence on the surface of the substrate; forming a shallow trench isolation structure in the substrate of the peripheral area, wherein the surface of the shallow trench isolation structure is higher than the surface of the floating gate layer; etching a shallow trench isolation structure of a part of the height and a shallow trench isolation structure of a part of the width, so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and the width becomes smaller, thereby causing a step to appear on the side of the shallow trench isolation structure; forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer simultaneously covers the step of the shallow trench isolation structure ; A control gate layer and a word line passing through the control gate layer and the floating gate layer are formed on the surface of the gate dielectric layer in the storage area, a first sidewall is also formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second sidewall; a first control gate sidewall is formed on the surface of the gate dielectric layer in the storage area, the first control gate sidewall covers the first sidewall and the sidewall of the control gate layer, and at the same time, a second control gate sidewall is formed on the surface of the gate dielectric layer in the peripheral area, the second control gate sidewall covers the sidewall of the shallow trench isolation structure, and the second control gate sidewall is located at the step of the shallow trench isolation structure; the uncovered part of the gate dielectric layer, the floating gate layer and the liner oxide layer are removed to expose part of the surface of the substrate. The shallow trench isolation structure formed by the present invention has a step, and the formed second control gate sidewall covers the step, so when removing the floating gate layer in the peripheral area, it will not be blocked by the second control gate sidewall, so that the floating gate layer in the peripheral area is removed cleanly, reducing the failure rate of the CP1 test.

[0057] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for manufacturing a memory, characterized in that: include: providing a substrate, dividing the substrate into adjacent storage areas and peripheral areas; forming a pad oxide layer and a floating gate layer in sequence on the surface of the substrate; forming a shallow trench isolation structure in the substrate of the peripheral region, wherein the surface of the shallow trench isolation structure is higher than the surface of the floating gate layer; Etching a shallow trench isolation structure of a portion of height and a shallow trench isolation structure of a portion of width, so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure; forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer simultaneously covers the step of the shallow trench isolation structure; A control gate layer and a word line passing through the control gate layer and the floating gate layer are formed on the surface of the gate dielectric layer in the storage area, a first spacer is also formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second spacer; A first control gate sidewall is formed on the surface of the gate dielectric layer in the storage area, the first control gate sidewall covers the first sidewall and the sidewall of the control gate layer, and at the same time, a second control gate sidewall is formed on the surface of the gate dielectric layer in the peripheral area, the second control gate sidewall covers the sidewall of the shallow trench isolation structure, and the second control gate sidewall is located at the step of the shallow trench isolation structure; The uncovered portions of the gate dielectric layer, the floating gate layer and the pad oxide layer are removed to expose a portion of the surface of the substrate.

2. The method for manufacturing a memory according to claim 1, wherein: The method of forming a shallow trench isolation structure in a substrate in a peripheral region, wherein a surface of the shallow trench isolation structure is higher than a surface of the floating gate layer, comprises: forming a sacrificial oxide layer on a surface of the floating gate layer; Sequentially etching a portion of the sacrificial oxide layer, the floating gate layer, the pad oxide layer and the substrate in the peripheral region to form a shallow trench in the substrate; Filling oxide into the shallow trench to form a shallow trench isolation structure; The sacrificial oxide layer is removed.

3. The method for manufacturing a memory according to claim 1, wherein: The substrate includes a wafer.

4. The method for manufacturing a memory according to claim 1, wherein: The gate dielectric layer includes an ONO layer.

5. The method for manufacturing a memory according to claim 1, wherein: The floating gate layer and the control gate layer both include polysilicon.

6. The method for manufacturing a memory according to claim 1, wherein: A method for forming a control gate layer and a word line passing through the control gate layer and the floating gate layer on the surface of the gate dielectric layer in the storage region, wherein a first spacer is further formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second spacer comprises: forming a control gate layer and a hard mask on a surface of the gate dielectric layer, wherein the hard mask has a first opening; forming a first side wall in the first opening; removing the control gate layer, the gate dielectric layer, the floating gate layer and the pad oxide layer not covered by the first sidewall spacer to expose the surface of the substrate; forming a second sidewall spacer, wherein the second sidewall spacer covers the sidewall of the control gate layer, the sidewall of the gate dielectric layer, the sidewall of the floating gate layer and the sidewall of the pad oxide layer, and the first sidewall spacer and the second sidewall spacer form a source line opening; A source line is formed in the source line opening.

7. The method for manufacturing a memory according to claim 6, wherein: The method of forming a source line in the source line opening includes: Filling the source line opening with polysilicon to form a source line.

8. The method for manufacturing a memory according to claim 1, wherein: The pad oxide layer includes oxide.

9. The method for manufacturing a memory according to claim 1, wherein: The first spacer, the first control gate spacer and the second control gate spacer all include oxide.

10. The method for manufacturing a memory according to claim 1, wherein: The second spacer includes nitride.

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