Single-transistor ternary content addressable memory and preparation method thereof

Abstract

The invention relates to a single-transistor ternary content addressable memory based on a gate-induced leakage current effect and a preparation method of the single-transistor ternary content addressable memory. The memory comprises a substrate, a ferroelectric layer and a grid electrode which are arranged from bottom to top, a drain electrode doped region and a source electrode doped region are arranged in an active region of the substrate, and a drain electrode and a source electrode are respectively formed by depositing contact metal. The polarization state of the ferroelectric layer is adjusted by applying different pulse voltages to the grid electrode, and data storage and high-speed parallel search of ternary logic states (the state 0, the state 1 and the state X) are achieved. By utilizing the nonvolatile storage characteristic of the ferroelectric layer and the high-speed search characteristic of the GIDL effect, efficient ternary logic storage and data search functions are realized under extremely low area consumption, and the device has the advantages of high storage density, low power consumption, quick response and good process compatibility; the method can be widely applied to the fields of artificial intelligence, big data and efficient data processing.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic devices, and in particular to a single-transistor ternary content addressable memory based on gate induced leakage current effect and a preparation method thereof. Background Art

[0002] With the rapid development of big data and artificial intelligence technologies, how to perform large-scale data searches efficiently and energy-efficiently has become a core challenge in data processing systems. Ternary Content Addressable Memory (TCAM) supports parallel memory searches throughout the entire memory, providing a key hardware solution for this need. TCAM is widely used in data-intensive tasks such as deep learning, especially in scenarios that require processing massive amounts of data and have extremely high energy efficiency requirements. Therefore, improving TCAM integration and energy efficiency to meet the growing computing needs has become an urgent goal of technological development. However, traditional TCAM technology uses a multi-transistor structure, which has problems such as low area efficiency and high power consumption, making it difficult to meet large-scale and high-density integration requirements.

[0003] The current single-transistor TCAM technology solutions include ferroelectric tunneling field effect transistors and ferroelectric Schottky contact field effect transistors. However, due to asymmetric source-drain injection and Schottky contact, ferroelectric tunneling field effect transistors and ferroelectric Schottky contact field effect transistors still have complex manufacturing processes and difficulty in size miniaturization, and they do not meet the requirements of high-density integration. In response to the high-density integration difficulties of existing TCAM technology, the present invention proposes a single-transistor ternary content addressable memory based on gate-induced leakage current effect and a preparation method. This technology uses a symmetrical source-drain ohmic contact design consistent with traditional CMOS technology, has excellent size miniaturization characteristics and low manufacturing complexity, significantly improves storage density and energy efficiency, and is suitable for future large-scale high-density integrated TCAM array applications. Summary of the invention

[0004] The present invention provides a single-transistor ternary content addressable memory and a preparation method, aiming to solve the problems of low memory area efficiency, high power consumption and insufficient data processing speed in the prior art, having excellent size miniaturization characteristics and low manufacturing complexity, and being suitable for TCAM array applications for large-scale integration. The present invention realizes a single-transistor level ternary logic storage function through innovative design, and at the same time has the capability of high-speed parallel search.

[0005] To achieve the above objectives, Figure 1 As shown, the present invention provides a single-transistor ternary content addressable memory, including: a substrate, a ferroelectric layer and a gate arranged from bottom to top, a drain doping region and a source doping region are arranged in the active area of ​​the substrate, a source contact metal is deposited on the source doping region to form a source, and a drain contact metal is deposited on the drain doping region to form a drain.

[0006] When a positive voltage is applied to the gate of the transistor, the transistor channel is inverted and then turned on. Since the source and drain are self-aligned with heavy doping technology, when a negative gate voltage is applied, the channel energy band bends to generate gate-induced drain leakage current, so the transistor exhibits bidirectional conduction characteristics. Its transfer characteristic curve is shown in the attached figure. Figure 2 shown.

[0007] Based on the above structure, Figure 3 As shown, the present invention implements writing of ternary logic state data by applying different pulse voltages to the gate to adjust the polarization state of the ferroelectric layer, wherein the ternary logic state includes state 0, state 1, and state X. in: When the ferroelectric layer is polarized upward, it corresponds to state 1; when the ferroelectric layer is polarized downward, it corresponds to state 0; when the ferroelectric layer is in a state without macroscopic polarization, it corresponds to state X. In the process of data writing, the storage of ternary logic states is realized by applying different voltage signals to the gate. When state 1 needs to be written, a negative pulse voltage is applied to the gate, the polarization direction of the ferroelectric layer is upward, attracting holes to gather on the channel surface, resulting in an increase in the channel potential and a right shift in the transfer characteristic curve of the device; when state 0 needs to be written, a positive pulse voltage is applied to the gate, the polarization direction of the ferroelectric layer is downward, attracting electrons to the channel surface, reducing the channel potential and shifting the transfer characteristic curve to the left; when state X needs to be written, a reverse pulse voltage or zero voltage is applied to the gate, where the magnitude of the reverse pulse voltage matches the coercive electric field of the ferroelectric material, making the polarization in the ferroelectric layer disordered and without macroscopic polarization, thereby realizing the ignored state.

[0008] Correspondingly, the source and gate of the single-transistor ternary content addressable memory are controlled to be grounded, and when a negative pulse voltage is applied to the gate, data writing of state 1 is realized; when a positive pulse voltage is applied to the gate, data writing of state 0 is realized; when a 0V voltage is applied to the gate or a reverse pulse of a voltage magnitude corresponding to the coercive electric field corresponding to the ferroelectric material is applied to the gate, data writing of state X is realized. When the ferroelectric layer has not been polarized before, the ferroelectric layer is initialized by applying a 0V voltage to the gate and grounding the source; when the ferroelectric layer has been polarized, the polarization state of the ferroelectric layer is reversed by applying a reverse pulse voltage to the gate, and the magnitude of the reverse pulse voltage matches the coercive electric field of the ferroelectric material.

[0009] This scheme realizes data search in ternary logic state by setting gate input voltage and detecting current state of drain; in the search operation, the source is grounded and a constant bias voltage is applied to the drain.

[0010] In order to achieve high-speed parallel search, such as Figure 5As shown, the present invention connects multiple single-transistor ternary content addressable memory cells into an array, and correspondingly, multiple memories form a TCAM array by connecting the source electrodes together, connecting the gate electrodes horizontally, and connecting the drain electrodes vertically, thereby realizing parallel data search operations. In the array structure, the source electrodes of each storage cell are connected to the ground, the gate electrodes are connected horizontally to form a search line (SL), and the drain electrodes are connected vertically to form a match line (ML). When a specific voltage signal is input to the gate electrode, the change in the drain current can directly indicate the matching of the storage state and the search condition.

[0011] Specifically, by inputting a negative voltage to the gate, if the current state of the drain is low current, the search for data 0 is realized; by inputting a positive voltage to the gate, if the voltage state of the drain is low current, the search for data 1 is realized. 1) When the storage state is 1, searching for 0 will cause the GIDL effect to turn on due to the superposition of the polarization electric field and the search voltage, presenting a high current, indicating a mismatch; searching for 1 will maintain a low current, indicating a match.

[0012] 2) When the storage state is 0, the search 0 presents a low current, indicating a match; the search 1 presents a high current due to the superposition of the polarization electric field and the search voltage to turn on the GIDL effect, indicating a mismatch.

[0013] 3) When the storage state is X, the ferroelectric layer has no macroscopic polarization. Regardless of whether a positive voltage is applied to search for 1 or a negative voltage is applied to search for 0, the transistor cannot be turned on or reversed by the search voltage alone. It always presents a low-point flow state, that is, the output is always matched, indicating that this state can be ignored.

[0014] In the search process, the search voltage should be a small voltage, that is, it should be smaller than the switching voltage of the ferroelectric material to avoid the search causing polarization switching and thus data loss.

[0015] On the other hand, the present invention provides a method for preparing a single-transistor ternary content addressable memory, comprising the following steps: S1: cleaning substrate; S2: photolithography the substrate surface to form an active region on the substrate surface; S3: depositing ferroelectric material on the surface of the substrate to form a ferroelectric layer; S4: depositing gate metal on the ferroelectric layer by evaporation or sputtering process; S5: performing photolithography patterning on the gate metal and then using a dry etching process to form a gate; S5: using a self-aligned heavy doping ion implantation technique to implant doping metal into the active region to form a drain doping region and a source doping region; S6: Photolithographically depositing a drain metal on the drain doping region to form a drain, and photolithographically depositing a source metal on the source doping region to form a source.

[0016] The present invention greatly improves the area efficiency of the storage unit by adopting a single-transistor design. Compared with the multi-transistor structure of the traditional TCAM unit, it significantly reduces the consumption of hardware resources and improves the integration density of the memory. In addition, the non-volatile properties of ferroelectric materials enable the memory to retain data for a long time in the case of power failure, reducing static power consumption. The search mechanism based on the GIDL effect further improves the data retrieval speed and meets the needs of efficient data processing in the fields of artificial intelligence and big data. The design of the present invention has excellent CMOS process compatibility and is suitable for the manufacture and application of large-scale integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a two-dimensional cross-sectional schematic diagram of the single-transistor ternary content addressable memory provided by this scheme.

[0018] Figure 2 This is a schematic diagram of the voltage-current characteristics of the single-transistor ternary content-addressable memory provided by this solution.

[0019] Figure 3 It is a schematic diagram of the single-transistor ternary content addressable memory provided by this scheme after being written.

[0020] Figure 4 It is a schematic diagram of the principle of the single-transistor ternary content addressable memory provided by this scheme.

[0021] Figure 5 It is a schematic diagram of the single-transistor ternary content-addressable storage structure provided by this scheme.

[0022] In the figure: 1-substrate, 2-drain doped region, 3-source doped region, 4-drain metal, 5-source metal, 6-ferroelectric layer, 7-gate. DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0024] Those skilled in the art should understand that, in the disclosure of the present invention, the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.

[0025] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0026] like Figure 1 As shown, the present solution provides a single-transistor ternary content addressable memory, comprising: a substrate 1, a ferroelectric layer 6 and a gate 7 arranged from bottom to top, a drain doping region 2 and a source doping region 3 are arranged in the active region of the substrate, a contact source metal 5 is deposited on the source doping region 3 to form a source, and a contact drain metal 4 is deposited on the drain doping region 2 to form a drain.

[0027] The present invention provides a method for preparing a single-transistor ternary content addressable memory based on a gate induced leakage current effect, comprising the following steps: S1: cleaning substrate 1; S2: Photolithography the substrate surface to form an active region on the surface of substrate 1; S3: depositing ferroelectric material on the surface of the substrate to form a ferroelectric layer 6; S4: depositing gate metal on the ferroelectric layer by evaporation or sputtering process; S5: After performing photolithography patterning on the gate metal, a gate 7 is formed by using a dry etching process; S5: using a self-aligned heavy doping ion implantation technique to implant doping metal into the active region to form a drain doping region 2 and a source doping region 3; S6: Photolithographically depositing a drain metal 5 on the drain doping region 2 to form a drain, and photolithographically depositing a source metal 4 on the source doping region 3 to form a source.

[0028] In step S1, a suitable substrate is selected and cleaned. In an embodiment of the present scheme, the substrate is a semiconductor substrate, wherein the semiconductor substrate is selected from any one or a combination of two or more of Si, SOI, III-V compound semiconductors, C, and Ge.

[0029] In step S2, a photosensitive material is coated on the substrate by photolithography technology, and then the photosensitive material is exposed and developed to form a mask pattern, and then a wet or dry etching technology is used to etch away unnecessary parts according to the mask pattern to leave the active area, so as to disconnect the electrical connection between different transistors.

[0030] In step S3, a layer of ferroelectric material is deposited on the substrate surface by chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition processes to form a ferroelectric layer. In an embodiment of this solution, the ferroelectric material is selected from any one of a perovskite structure, a fluorite structure and a wurtzite structure material.

[0031] In step S4, a layer of metal material is deposited as gate metal on the ferroelectric layer by evaporation or sputtering process; and in step S5, the gate metal is patterned by photolithography technology to form a gate pattern, and then the gate is accurately etched out by dry etching technology, and the part not protected by the photoresist is removed.

[0032] In step S5, a highly doped drain doping region and a highly doped source doping region are formed in the active region below the gate using a self-aligned heavily doped ion implantation technique.

[0033] In step S6, a layer of metal material is deposited on the entire surface of the substrate by photolithography technology, and then chemical mechanical polishing (CMP) or wet etching is performed to remove excess metal, leaving only the metal covering the drain doping region and the source doping region to form a drain and a source, respectively.

[0034] In an embodiment of the present scheme, the metal of the drain, source and gate of the single-transistor ternary content addressable memory is any one of a metal monomer or a metal alloy, wherein the metal monomer is selected from one or more combinations of metal tungsten, metal titanium, metal copper, metal aluminum, metal platinum, metal iridium and metal ruthenium, and the metal alloy is selected from one or more combinations of tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide and tantalum silicide.

[0035] Based on the above structure, the present invention applies different pulse voltages to the gate to change the polarization state of the ferroelectric layer to achieve three-state storage of data. Figure 3 As shown, the ternary logic states include state 0, state 1, and state X, where: When the ferroelectric layer is polarized upward, it corresponds to state 1; when the ferroelectric layer is polarized downward, it corresponds to state 0; when the ferroelectric layer is in a state of no macroscopic polarization, it corresponds to state X. Specifically, Figure 4As shown, when it is necessary to write state 1, a negative pulse voltage is applied to the gate, the polarization direction of the ferroelectric layer is upward, holes are attracted to the channel surface, the channel potential is increased, and the transfer characteristic curve of the device moves to the right; when it is necessary to write state 0, a positive pulse voltage is applied to the gate, the polarization direction of the ferroelectric layer is downward, electrons are attracted to the channel surface, the channel potential is reduced, and the transfer characteristic curve of the device moves to the left; when it is necessary to write state X, a reverse pulse voltage or zero voltage is applied to the gate to make the polarization in the ferroelectric layer disordered, thereby achieving the ignore state.

[0036] Based on the above design, Figure 5 As shown in FIG. 1 , a parallel data search operation is realized by connecting multiple single-transistor ternary content addressable memory cells into an array. In the array structure, the source of each storage cell is grounded, the gate is connected horizontally to form a search line (SL), and the drain is connected vertically to form a match line (ML). When a specific voltage signal is input to the gate, the change in drain current can directly indicate the matching of the storage state and the search condition.

[0037] Specifically, by inputting a negative voltage to the gate, if the current state of the drain is low current, the search for data 0 is realized; by inputting a positive voltage to the gate, if the voltage state of the drain is low current, the search for data 1 is realized. Where: 1) When the storage state is 1, searching for 0 will cause the GIDL effect to turn on due to the superposition of the polarization electric field and the search voltage, presenting a high current, indicating a mismatch; searching for 1 will maintain a low current, indicating a match.

[0038] 2) When the storage state is 0, the search 0 presents a low current, indicating a match; the search 1 presents a high current due to the superposition of the polarization electric field and the search voltage to turn on the GIDL effect, indicating a mismatch.

[0039] 3) When the storage state is X, the ferroelectric layer has no macroscopic polarization. Regardless of whether a positive voltage is applied to search for 1 or a negative voltage is applied to search for 0, the transistor cannot be turned on or reversed by the search voltage alone. It always presents a low-point flow state, that is, the output is always matched, indicating that this state can be ignored.

[0040] During the search process, the search voltage should be a small voltage, that is, it should be smaller than the switching voltage of the ferroelectric material to avoid polarization switching caused by the search, thereby losing data.

[0041] At this time, since each single-transistor ternary content addressable memory independently executes the search logic of data 0 or data 1, when multiple single-transistor ternary content addressable memories are arranged in an array, data search can be performed on all single-transistor ternary content addressable memories at the same time, thereby realizing parallel data search. This means that as long as the data of one single-transistor ternary content addressable memory matches the search condition, its drain current will be reflected, thereby quickly locating the location of the target data.

[0042] The present invention is not limited to the above-mentioned optimal implementation mode. Anyone can derive other various forms of products under the inspiration of the present invention. However, no matter what changes are made in the shape or structure, all technical solutions that are the same or similar to those of the present application fall within the protection scope of the present invention.

Claims

1. A single-transistor ternary content addressable memory, characterized in that: include: A substrate, a ferroelectric layer and a gate are arranged from bottom to top, a drain doping region and a source doping region are arranged in the active region of the substrate, a source contacting metal is deposited on the source doping region to form a source, and a drain contacting metal is deposited on the drain doping region to form a drain; different pulse voltages are applied to the gate to adjust the polarization state of the ferroelectric layer, so as to realize the writing of ternary logic state data, wherein the ternary logic state includes state 0, state 1 and state X.

2. The single-transistor ternary content addressable memory according to claim 1, characterized in that: The source and gate of the single-transistor ternary content addressable memory are controlled to be grounded. When a negative pulse voltage is applied to the gate, data writing of state 1 is realized; when a positive pulse voltage is applied to the gate, data writing of state 0 is realized; When a voltage of 0V is applied to the gate or a reverse pulse of a voltage corresponding to the coercive electric field corresponding to the ferroelectric material is applied to the gate, data writing of state X is achieved.

3. The single-transistor ternary content addressable memory according to claim 2, characterized in that: When the ferroelectric layer has not been polarized before, the ferroelectric layer is initialized by applying a 0V voltage to the gate and grounding the source; when the ferroelectric layer is already polarized, the polarization state of the ferroelectric layer is reversed by applying a reverse pulse voltage to the gate, and the magnitude of the reverse pulse voltage matches the coercive electric field of the ferroelectric material.

4. The single-transistor ternary content addressable memory according to claim 1, characterized in that: Data search in the ternary logic state is achieved by setting the gate input voltage and detecting the current state of the drain; in the search operation, the source is grounded and a constant bias voltage is applied to the drain.

5. The single-transistor ternary content addressable memory according to claim 4, characterized in that: By inputting a negative voltage to the gate, if the current high and low state of the drain is low current, the search for data 0 is achieved; by inputting a positive voltage to the gate, if the voltage high and low state of the drain is low current, the search for data 1 is achieved.

6. The single-transistor ternary content addressable memory according to claim 4, characterized in that: During the search operation, the voltage input to the gate is less than the switching voltage of the ferroelectric layer to avoid loss of stored data due to changes in the polarization state.

7. The single-transistor ternary content addressable memory according to claim 1, characterized in that: The plurality of memories form a TCAM array in a manner of having their sources commonly grounded, gates connected horizontally, and drains connected vertically.

8. A single transistor ternary content addressable memory, characterized in that: include: The substrate, ferroelectric layer and gate are arranged from bottom to top, the active area of ​​the substrate is provided with a drain doping area and a source doping area, a contact source metal is deposited on the source doping area to form a source, and a contact drain metal is deposited on the drain doping area to form a drain.

9. The single-transistor ternary content addressable memory according to claim 8, characterized in that: The substrate is a semiconductor substrate, wherein the semiconductor substrate is selected from any one or a combination of two or more of Si, SOI, III-V compound semiconductors, C, and Ge.

10. The single-transistor ternary content addressable memory according to claim 8, characterized in that: The ferroelectric layer adopts any one of a perovskite structure ferroelectric material, a fluorite structure ferroelectric material and a wurtzite structure ferroelectric material.

11. The single-transistor ternary content addressable memory according to claim 8, characterized in that: The metal of the drain, source and gate is any one of a metal monomer or a metal alloy, wherein the metal monomer is selected from one or more combinations of metal tungsten, metal titanium, metal copper, metal aluminum, metal platinum, metal iridium, and metal ruthenium, and the metal alloy is selected from one or more combinations of tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

12. A method for preparing a single-transistor ternary content addressable memory, characterized in that: The following steps are involved: S1: cleaning substrate; S2: photolithography the substrate surface to form an active region on the substrate surface; S3: depositing ferroelectric material on the surface of the substrate to form a ferroelectric layer; S4: depositing a gate metal on the ferroelectric layer by evaporation or sputtering; S5: performing photolithography patterning on the gate metal and then forming a gate by dry etching; S5: using a self-aligned heavy doping ion implantation technique to implant doping metal into the active region to form a drain doping region and a source doping region; S6: Photolithographically depositing a drain metal on the drain doping region to form a drain, and photolithographically depositing a source metal on the source doping region to form a source.

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