Silicon carbide power diode device structure and preparation method thereof

Abstract

The invention discloses a silicon carbide power diode device structure and a preparation method thereof. The silicon carbide power diode device structure comprises a back metal layer, a silicon carbide substrate, a silicon carbide epitaxy, a P + doped region formed by multiple times of ion implantation, a field oxide layer growing on the silicon carbide epitaxy in a thermal oxidation mode, Schottky contact metal, a first front metal layer, a first passivation layer and a second passivation layer. And a second front metal layer is arranged on the surface of the first front metal layer. The invention innovatively provides a silicon carbide power diode device structure with a second front metal layer. In this way, the purpose of thinning the front metal layer to reduce the stress of the passivation layer is achieved, and the reliability of the device is improved. The device structure of the special metal structure can be realized through the scheme of combining the field plate and the terminal ring and through the terminal of the field limiting ring structure, and the device structure has originality in the field of semiconductor devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon carbide power diode device structure and its fabrication method. Background Technology

[0002] As the application market for silicon carbide power devices becomes more mature, reliability issues are also regarded as one of the major bottlenecks in the development of silicon carbide power devices. Especially for outdoor applications such as new energy vehicles and photovoltaics, the requirements for the devices' ability to withstand high temperature and humidity as well as continuous thermal shock are becoming increasingly stringent.

[0003] The reverse bias capability of silicon carbide power diodes is largely provided by the termination region. Traditional device structures, to prevent moisture and mobile ions from entering the termination, primarily employ single-layer to multi-layer materials as passivation layers to protect the termination structure. Nitrides, silicon dioxide, and polyimide are the main materials used. Currently, the passivation materials for most silicon carbide power diodes are deposited by PECVD, growing over the field oxide layer and extending onto the front metal layer, such as... Figure 1 As shown.

[0004] Currently, silicon nitride (Si3N4) is an indispensable material for traditional passivation layers. Silicon nitride is an inert dielectric with good chemical stability, high resistivity, high temperature resistance, and thermal shock resistance. It also has a dense structure, high hardness, good hydrophobicity, and low vacuum density, making it difficult for gases and water vapor to pass through. During temperature cycling (TC), temperature shock (TS), or the heating-cooling process in practical applications, the thermal expansion coefficient of silicon nitride is much smaller than that of metals and encapsulating resins (EMC), leading to interlayer stress concentration points at the steps of the silicon nitride layers. See details... Figure 2 The passivation layer is highly susceptible to cracking at the step. Contaminating ions (such as Na+) and water vapor can pass through the cracks and directly affect the electric field distribution at the terminal. In severe cases, this can lead to excessive reverse leakage current in the device, which may eventually cause device failure.

[0005] This application solves the problem of poor silicon nitride step coverage by adjusting the structure of the front metal layer, greatly reducing the stress at the passivation layer step and significantly improving the reliability of silicon carbide power diodes.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the general background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] In view of the problems existing in the prior art, the purpose of this invention is to provide a silicon carbide power diode device structure and its fabrication method to solve the problems existing in the prior art.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: A silicon carbide power diode device structure includes a back metal layer, a silicon carbide substrate, a silicon carbide epitaxial layer, a P+ doped region formed by multiple ion implantations, a field oxide layer thermally oxidized on the silicon carbide epitaxial layer, a Schottky contact metal, a first front metal layer, a first passivation layer, and a second passivation layer; the second front metal layer is disposed on the surface of the first front metal layer.

[0009] Furthermore, the second front metal layer extends the metal layer outwards above the field oxide layer to form a field plate terminal.

[0010] Furthermore, the second front metal layer is not pressed onto the P+ terminal ring to form a field plate structure.

[0011] Furthermore, the materials used to prepare the Schottky contact metal include Al, Ti, Ni, and Mo.

[0012] Furthermore, the materials used to prepare the first and second front metal layers include Al, Ag, Au, and Ni.

[0013] Furthermore, the thickness of the second front metal layer is ≤0.5um.

[0014] Furthermore, the first passivation layer is a hydrophobic film, and the material includes SiN, SiO2 / SiN composite structure, and Al2O3; the material of the second passivation layer is polyimide.

[0015] A method for fabricating a silicon carbide power diode device structure, the method comprising the following steps: S1. The silicon carbide substrate is an N-type substrate with a diameter between 4 inches and 12 inches, a crystal form of 4H-SiC, a thickness of 350 μm, and a doping concentration of 1e18 / cm². 3 Up to 1e20 / cm 3 between; S2. After removing contaminants from the silicon carbide substrate by RCA cleaning, silicon carbide epitaxial growth is performed on the silicon carbide substrate. The growth method is chemical vapor deposition or physical vapor deposition. The thickness of the silicon carbide epitaxial layer is between 5-30 μm. S3. After the silicon carbide epitaxial layer is cleaned and aligned by etching, a mask layer is deposited, the pattern is transferred to the mask by photolithography, and then the ion implantation area is exposed by etching. S4. High-temperature ion implantation of Al ions forms P+ implantation regions in the active and terminal regions. The implantation regions of the active regions are strip-shaped, square, hexagonal, or circular. Ion implantation is performed once or multiple times to activate the implanted ions and form P+ doped regions. The mask layer is then removed by etching and cleaning. S5. Silicon dioxide is deposited on the silicon carbide epitaxial surface, and then the silicon dioxide dielectric layer is etched to expose the active region, forming a complete structure of the field oxide layer. S6. A Schottky metal layer is deposited on the silicon carbide epitaxial surface by sputtering or evaporation. After deposition, an annealing process is performed to form the Schottky contact metal. The annealing temperature is between 400-600℃ and the annealing time is between 30s and 60min. The Schottky contact metal is one or a composite structure of two or more of Ti, TiN, Ni, Ag, W, Pt, and Mo, with a thickness between 50-500nm. S7. A front metal layer is deposited on the Schottky contact metal by sputtering or evaporation. After deposition, an etch barrier layer is formed by photolithography to transfer the pattern, and then the first front metal layer is formed by etching. The etching method is dry etching, wet etching, or a combination of both. The first front metal layer is one of Al, Cu, Ag, and Au, or a combination of two or more of them, with a thickness between 3-5 μm. S8. A second front metal layer is deposited on top of the first front metal layer by sputtering or evaporation. The second front metal layer is formed by etching after deposition. The etching method is dry etching, wet etching, or a combination of both. The second front metal layer is one of Al, Cu, Ag, and Au, or a combination of two or more of them, with a thickness between 0.2-0.5 μm. S9. The first passivation layer and the second passivation layer are deposited using the PEVCD method. The material of the first passivation layer includes SiN, SiO2 / SiN composite film, and Al2O3 hydrophobic structure to block pollutant ions and water vapor from entering the terminal area. S10. A second passivation layer is grown on the surface of the first passivation layer and the second front metal layer. The second passivation layer is a polyimide or composite passivation layer structure, grown by PECVD. It is used to buffer the stress between the first passivation layer and the molding resin, reduce the stress between the metal and the film layer, and eliminate the hidden danger of cracking below the passivation layer step, protect the terminal structure of the device, and improve the reliability of the device. S11. An ohmic contact metal is grown on the back side of a silicon carbide substrate. This growth is carried out by sputtering or evaporation and the back metal layer is finally formed by a high-temperature annealing process. When growing the ohmic contact metal, a back thinning process is selected to remove scratches, contaminants and defects on the back side of the silicon carbide substrate and to optimize the forward conduction capability of the device. The material of the back metal layer is one or a composite structure of two or more of Ti, Ni, Ag, Au and Cu.

[0016] By adopting the above technical solution, the present invention has the following beneficial effects: This application innovatively proposes a silicon carbide power diode device structure with a second front-side metal layer. This approach achieves the goal of thinning the front-side metal layer to reduce passivation layer stress, thereby improving device reliability. This unique metal structure can be implemented either through a combination of a field plate and a termination ring, or through a field-limiting ring structure, demonstrating originality in the field of semiconductor devices. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the device structure of a silicon carbide power diode in the prior art.

[0019] Figure 2 This is a schematic diagram of the structure of silicon carbide power diode devices in the prior art where interlayer stress concentration points occur.

[0020] Figure 3 This is a schematic diagram of the field plate structure formed by the silicon carbide power diode device structure of the present invention.

[0021] Figure 4 This is a schematic diagram of the silicon carbide power diode device structure of the present invention without the formation of a field plate structure.

[0022] Figure 5 This is a schematic diagram of the structure formed in step S1 of the method for fabricating the silicon carbide power diode device structure of the present invention.

[0023] Figure 6 This is a schematic diagram of the structure formed in step S2 of the method for fabricating the silicon carbide power diode device structure of the present invention.

[0024] Figure 7 This is a schematic diagram of the structure formed in step S3 of the method for fabricating the silicon carbide power diode device structure of the present invention.

[0025] Figure 8 This is a schematic diagram of the structure formed in step S4 of the method for fabricating the silicon carbide power diode device structure of the present invention.

[0026] Figure 9 This is a schematic diagram of the structure formed in step S5 of the method for fabricating the silicon carbide power diode device structure of the present invention.

[0027] Figure 10This is a schematic diagram of the structure formed in step S6 of the method for fabricating the silicon carbide power diode device structure of the present invention.

[0028] Figure 11 This is a schematic diagram of the structure formed in step S7 of the method for fabricating the silicon carbide power diode device structure of the present invention.

[0029] Figure 12 This is a schematic diagram of the structure formed in step S8 of the method for fabricating the silicon carbide power diode device structure of the present invention.

[0030] Figure 13 This is a schematic diagram of the structure formed in step S9 of the method for fabricating the silicon carbide power diode device structure of the present invention.

[0031] Figure 14 This is a schematic diagram of the structure formed in step S10 of the method for fabricating the silicon carbide power diode device structure of the present invention.

[0032] Figure 15 This is a schematic diagram of the structure formed in step S11 of the method for fabricating the silicon carbide power diode device structure of the present invention. Detailed Implementation

[0033] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0035] The present invention proposes a silicon carbide power diode device structure, characterized in that it includes a back metal layer 110, a silicon carbide substrate 101, a silicon carbide epitaxial layer 102, a P+ doped region 103 formed by multiple ion implantations, a field oxide layer 104 thermally oxidized on the silicon carbide epitaxial layer, a Schottky contact metal 105, a first front metal layer 106, a first passivation layer 108, and a second passivation layer 109; a second front metal layer 107 is disposed on the surface of the first front metal layer 106.

[0036] Combination Figure 3 As shown, the second front metal layer 107 extends outwards from the metal layer above the field oxide layer 104 to form a field plate terminal. The main advantage of this scheme is that it has low process requirements, and the second front metal layer 107 can be extended to a suitable length according to the process.

[0037] Combination Figure 4 As shown, the second front metal layer 107 does not press on the P+ terminal ring to form a field plate structure. The preparation method of this scheme is completely consistent with the scheme of forming a field plate terminal. The key point is that the second front metal layer 107 does not press on the P+ terminal ring to form a field plate structure. Compared with the scheme of forming a field plate terminal, the extension length of the second front metal layer 107 is limited, but the distribution of the terminal electric field is optimized.

[0038] In this embodiment, the Schottky contact metal 105 is made of Al, Ti, Ni, and Mo. The first front metal layer 106 and the second front metal layer 107 are made of Al, Ag, Au, and Ni. The thickness of the second front metal layer 107 is ≤0.5 μm. The first passivation layer 108 is a hydrophobic film made of SiN, SiO2 / SiN composite structure, or Al2O3; the second passivation layer 109 is made of polyimide.

[0039] Combination Figure 5-15 The method for fabricating a silicon carbide power diode device structure proposed in this invention comprises the following steps: S1, Silicon carbide substrate 101: An N-type substrate is selected, with a diameter between 4 inches and 12 inches, a crystal form of 4H-SiC, a thickness of 350 μm, and a doping concentration of 1e18 / cm². 3 Up to 1e20 / cm 3 between; S2. After removing contaminants from the silicon carbide substrate 101 by RCA cleaning, silicon carbide epitaxial growth 102 is performed on the silicon carbide substrate 101. The growth method is chemical vapor deposition or physical vapor deposition. The thickness of the silicon carbide epitaxial growth 102 is between 5-30 μm. S3. After the silicon carbide epitaxial layer 102 is cleaned and aligned by etching, a mask layer is deposited, the pattern is transferred to the mask by photolithography, and then the ion implantation area is exposed by etching. S4. P+ implantation regions are formed by high-temperature ion implantation of Al ions to form active and terminal regions; the implantation regions of the active regions are strip-shaped, square, hexagonal, or circular; ion implantation is performed once or multiple times to activate the implanted ions and form P+ doped regions 103; then the mask layer is removed by etching and cleaning. S5. Silicon dioxide is deposited on the surface of silicon carbide epitaxial layer 102, and then the silicon dioxide dielectric layer is etched to expose the active region, forming the complete structure of field oxide layer 104. S6. A Schottky metal layer is deposited on the surface of the silicon carbide epitaxial layer 102 by sputtering or evaporation. After deposition, an annealing process is performed to form the Schottky contact metal 105. The annealing temperature is between 400-600℃ and the annealing time is between 30s and 60min. The Schottky contact metal 105 is a composite structure of one or more of Ti, TiN, Ni, Ag, W, Pt, and Mo, with a thickness between 50-500nm. S7. A front metal layer is deposited on the Schottky contact metal 105 by sputtering or evaporation. After deposition, an etch barrier layer is formed by photolithography to transfer the pattern, and then the first front metal layer 106 is formed by etching. The etching method is dry etching, wet etching, or a combination of both. The first front metal layer 106 is one of Al, Cu, Ag, and Au, or a combination of two or more of them, with a thickness between 3-5 μm. S8. A second front metal layer 107 is deposited on top of the first front metal layer 106. This deposition is performed by sputtering or evaporation. The second front metal layer 107 is formed by etching after deposition. This etching method is dry etching, wet etching, or a combination of both. The second front metal layer 107 is one of Al, Cu, Ag, and Au, or a combination of two or more of them, and its thickness is between 0.2-0.5 μm. S9. The first passivation layer 108 and the second passivation layer 109 are deposited using the PEVCD method. The material of the first passivation layer 108 includes SiN, SiO2 / SiN composite film, and Al2O3 hydrophobic structure to block pollutant ions and water vapor from entering the terminal area. S10. A second passivation layer 109 is grown on the surface of the first passivation layer 108 and the second front metal layer 107. The second passivation layer 109 is a polyimide or composite passivation layer structure and is grown by PECVD. It is used to buffer the stress between the first passivation layer 108 and the molding resin, reduce the stress between the metal and the film layer, and eliminate the hidden danger of cracking below the passivation layer step, protect the terminal structure of the device, and improve the reliability of the device. S11. An ohmic contact metal is grown on the back side of the silicon carbide substrate 101. This growth is carried out by sputtering or evaporation and the back metal layer 110 is finally formed by high-temperature annealing. When growing the ohmic contact metal, a back thinning process is selected to remove scratches, contaminants and defects on the back side of the silicon carbide substrate 101 and to optimize the forward conduction capability of the device. The material of the back metal layer 110 is one or a composite structure of two or more of Ti, Ni, Ag, Au and Cu.

[0040] In summary, by introducing the second front metal layer 107, this invention innovatively realizes a new device structure based on existing silicon carbide power diode technology. This allows the waterproof first passivation layer 108 to extend only to the second front metal layer 107, and the thickness of the second front metal layer 107 (≤0.5um) is much smaller than that of traditional metal layers (≥4um). This greatly reduces the stress at the step of the first passivation layer 108, which is mainly made of silicon nitride, and at the same time greatly reduces the risk of passivation layer cracking when the overall device is subjected to temperature cycling, temperature shock tests, or thermal shocks in actual applications.

[0041] Compared with traditional silicon carbide power diodes, the novel device structure proposed in this invention greatly reduces the risk of passivation cracking, significantly improves device reliability, and effectively reduces the failure rate of the device during long-term use.

[0042] This invention innovatively proposes a silicon carbide power diode device structure with a second front-side metal layer. This approach achieves the goal of thinning the front-side metal layer to reduce passivation layer stress, thereby improving device reliability. This unique metal structure can be implemented either through a combination of a field plate and a termination ring, or through a field-limiting ring structure, demonstrating originality in the field of semiconductor devices.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon carbide power diode device structure, characterized in that: It comprises a back metal layer (110), a silicon carbide substrate (101), a silicon carbide epitaxy (102), a P+ doped region (103) formed by multiple ion implantations, a field oxide layer (104) grown by thermal oxidation on the silicon carbide epitaxy, a Schottky contact metal (105), a first front metal layer (106), a first passivation layer (108) and a second passivation layer (109); a second front metal layer (107) is arranged on the surface of the first front metal layer (106).

2. The silicon carbide power diode device structure according to claim 1, characterized in that: The second front metal layer (107) extends the metal layer outward to above the field oxide layer (104) to form a field plate terminal.

3. The silicon carbide power diode device structure according to claim 1, characterized in that: The second front metal layer (107) is not pressed on the P+ terminal ring to form a field plate structure.

4. The silicon carbide power diode device structure according to claim 1, characterized in that: The preparation materials of the Schottky contact metal (105) include Al, Ti, Ni, and Mo.

5. The silicon carbide power diode device structure according to claim 1, characterized in that: The first front metal layer (106) and the second front metal layer (107) are made of materials including Al, Ag, Au, and Ni.

6. The silicon carbide power diode device structure according to claim 1, characterized in that: The thickness of the second front metal layer (107) is ≤0.5 um.

7. The silicon carbide power diode device structure according to claim 1, characterized in that: The first passivation layer (108) is a hydrophobic film, and the material thereof includes SiN, SiO2 / SiN composite structure, and Al2O3; the material of the second passivation layer (109) is polyimide.

8. A method for preparing a silicon carbide power diode device structure according to any one of claims 1 to 7, characterized in that: The preparation method comprises the following steps: S1. Silicon carbide substrate (101) is an N-type substrate with a diameter of 4 inches to 12 inches, a crystal form of 4H-SiC, a thickness of 350um, and a doping concentration of 1e18 / cm 3 To 1e20 / cm 3 between; S2, after performing RCA cleaning on the silicon carbide substrate (101) to remove contamination, growing silicon carbide epitaxy (102) on the silicon carbide substrate (101); the growth method is chemical vapor deposition or physical vapor deposition; the thickness of the silicon carbide epitaxy (102) is between 5 and 30 um; S3, after the silicon carbide epitaxy (102) is cleaned and the in-place etching mark is completed, a mask layer is deposited, a pattern is transferred to the mask by photolithography, and then the ion implantation area is exposed by etching; S4, forming a P+ implantation region in an active region and a terminal region by high-temperature ion implantation of Al ions; the implantation region in the active region is in the shape of a strip, square, hexagon or circle; the ion implantation is one or more times, and the implanted ions are activated to form a P+ doping region (103); and then the mask layer is removed by etching and cleaning methods; S5, depositing silicon dioxide on the surface of the silicon carbide epitaxial layer (102), and then etching the silicon dioxide dielectric layer to expose the active area, thereby forming a complete structure of the field oxide layer (104); S6. Depositing a Schottky metal layer on the surface of the silicon carbide epitaxial (102), the deposition being performed by sputtering or evaporation; performing annealing after the deposition to form a Schottky contact metal (105); the annealing temperature is between 400-600° C., and the annealing time is between 30 seconds and 60 minutes; the Schottky contact metal (105) is one of Ti, TiN, Ni, Ag, W, Pt, and Mo, or a composite structure of two or more thereof, and has a thickness between 50 and 500 nm; S7, depositing a front metal layer on the Schottky contact metal (105), the deposition being performed by sputtering or evaporation; after the deposition, transferring a pattern by photolithography to form an etching barrier layer, and then forming a first front metal layer (106) by etching; the etching method is dry etching, wet etching or a combination of the two methods; the first front metal layer (106) is one of Al, Cu, Ag, Au or a combination of two or more thereof, and has a thickness of 3-5 μm; S8, depositing a second front metal layer (107) on the first front metal layer (106), the deposition being performed by sputtering or evaporation; etching after deposition to form the second front metal layer (107); the etching method being dry etching, wet etching or a combination of the two; the second front metal layer (107) is one of Al, Cu, Ag, Au or a combination of two or more thereof, and has a thickness between 0.2 and 0.5 um; S9, using a PEVCD method to deposit a first passivation layer (108) and a second passivation layer (109); the material of the first passivation layer (108) includes SiN, SiO2 / SiN composite film layer, and Al2O3 hydrophobic structure to prevent contamination ions and water vapor from entering the terminal area; S10, growing a second passivation layer (109) on the surface of the first passivation layer (108) and the second front metal layer (107); the second passivation layer (109) is a polyimide or composite passivation layer structure, grown by a PECVD method; and is used to buffer the stress between the first passivation layer (108) and the molding resin, reduce the stress between the metal and the film layer, and eliminate the hidden danger of cracking below the step of the passivation layer, thereby protecting the terminal structure of the device and improving the reliability of the device; S11. An ohmic contact metal is grown on the back side of the silicon carbide substrate (101). The growth is performed by sputtering or evaporation, and a back metal layer (110) is finally formed by a high-temperature annealing process. When the ohmic contact metal is grown, a back thinning process is selected to remove scratches, stains and defects on the back side of the silicon carbide substrate (101) and optimize the forward conduction capability of the device. The material of the back metal layer (110) is one of Ti, Ni, Ag, Au, Cu, or a composite structure of two or more thereof.

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