Gallium nitride device and preparation method thereof

Abstract

The invention discloses a gallium nitride device and a preparation method thereof. The gallium nitride device comprises a substrate; the channel layer is positioned on one side of the substrate; the composite barrier layer comprises a first barrier layer, a second barrier layer and a third barrier layer; the first barrier layer is located on the side, away from the substrate, of the channel layer; the second barrier layer is located on the side, away from the channel layer, of the first barrier layer; the second barrier layer is used as an etching barrier layer and is used for protecting the first barrier layer; the third barrier layer is located on the side, away from the first barrier layer, of the second barrier layer; a doped III-V group semiconductor layer and a gate electrode; the source electrode is located on the side, away from the channel layer, of the first barrier layer; and the drain electrode is positioned on one side, far away from the channel layer, of the first barrier layer. According to the technical scheme provided by the embodiment of the invention, in the process of etching the doped III-V group semiconductor layer, the first barrier layer at one side of the channel layer is prevented from being over-etched, so that the electrical performance of the gallium nitride device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium nitride device and a preparation method thereof. Background Art

[0002] Gallium nitride devices have excellent electrical properties because of the presence of a large concentration of two-dimensional electron gas (2DEG) in the heterojunction formed by the channel layer and the barrier layer.

[0003] In the process of forming a gate structure of an existing gallium nitride device, during the process of patterning the doped III-V semiconductor layer in the gate structure, the barrier layer on one side of the channel layer is easily over-etched, thereby affecting the electrical performance of the gallium nitride device. Summary of the invention

[0004] The present invention provides a gallium nitride device and a preparation method thereof, so as to avoid over-etching of a barrier layer on one side of a channel layer, thereby improving the electrical performance of the gallium nitride device.

[0005] According to one aspect of the present invention, there is provided a gallium nitride device, comprising:

[0006] substrate;

[0007] A channel layer, located on one side of the substrate;

[0008] A composite barrier layer, the composite barrier layer comprising a first barrier layer, a second barrier layer and a third barrier layer; the first barrier layer is located on a side of the channel layer away from the substrate; the second barrier layer is located on a side of the first barrier layer away from the channel layer; the second barrier layer is used as an etching stop layer for protecting the first barrier layer; the third barrier layer is located on a side of the second barrier layer away from the first barrier layer;

[0009] a doped III-V group semiconductor layer, located on a side of the third barrier layer away from the second barrier layer;

[0010] A gate, located on a side of the doped III-V semiconductor layer away from the third barrier layer;

[0011] A source electrode, located at a side of the first barrier layer away from the channel layer;

[0012] The drain is located on a side of the first barrier layer away from the channel layer.

[0013] Optionally, the second barrier layer includes aluminum nitride, and the etching gas for etching the doped Group III-V semiconductor layer includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

[0014] Optionally, the second barrier layer includes AlGaN, and the content of Al atoms in the second barrier layer is greater than the content of Al atoms in the first barrier layer; and the etching gas for etching the doped III-V semiconductor layer includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

[0015] Optionally, a vertical projection area of ​​the third barrier layer on the substrate is smaller than a vertical projection area of ​​the second barrier layer on the substrate;

[0016] The vertical projection area of ​​the third barrier layer on the substrate is greater than or equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate.

[0017] Optionally, a vertical projection area of ​​the third barrier layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate;

[0018] The third barrier layer includes a first part, a second part and a third part, the first part covers the area between the gate structure and the source, the second part covers the area between the gate structure and the drain, the third part is located between the doped III-V semiconductor layer and the second barrier layer, the thickness of the first part is less than the thickness of the third part, and the thickness of the second part is less than the thickness of the third part.

[0019] According to another aspect of the present invention, there is provided a method for preparing a gallium nitride device, comprising:

[0020] providing a substrate;

[0021] forming a channel layer on one side of the substrate;

[0022] forming a first barrier layer on a side of the channel layer away from the substrate;

[0023] forming a second barrier layer on a side of the first barrier layer away from the channel layer, wherein the second barrier layer is used as an etching stop layer to protect the first barrier layer;

[0024] forming a third barrier layer on a side of the second barrier layer away from the first barrier layer; the first barrier layer, the second barrier layer and the third barrier layer serve as a composite barrier layer;

[0025] forming a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer;

[0026] Patterning the doped III-V semiconductor layer;

[0027] forming a source electrode on a side of the first barrier layer away from the channel layer;

[0028] forming a drain on a side of the first barrier layer away from the channel;

[0029] Before patterning the doped III-V semiconductor layer, a gate is formed on a side of the doped III-V semiconductor layer away from the third barrier layer; or, after forming a drain on a side of the first barrier layer away from the channel layer, a gate is formed on a side of the doped III-V semiconductor layer away from the third barrier layer.

[0030] Optionally, forming a second barrier layer on a side of the first barrier layer away from the channel layer includes:

[0031] A second barrier layer including aluminum nitride is formed on a side of the first barrier layer away from the channel layer, and an etching gas for etching the doped III-V semiconductor layer includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

[0032] Optionally, forming a second barrier layer on a side of the first barrier layer away from the channel layer includes:

[0033] A second barrier layer including AlGaN is formed on a side of the first barrier layer away from the channel layer, and a content of Al atoms in the second barrier layer is greater than a content of Al atoms in the first barrier layer; and an etching gas for etching the doped III-V semiconductor layer includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

[0034] Optionally, forming a third barrier layer on a side of the second barrier layer away from the first barrier layer comprises:

[0035] forming a third barrier layer on a side of the second barrier layer away from the first barrier layer, wherein a vertical projection area of ​​the third barrier layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate;

[0036] forming a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer, wherein a vertical projection area of ​​the doped III-V semiconductor layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate;

[0037] The doped III-V semiconductor layer is etched using an etching gas including a chlorine-based etching gas doped with oxygen (O) or fluorine (F) to form a third barrier layer whose vertical projection area on the substrate is smaller than the vertical projection area of ​​the second barrier layer on the substrate, and whose vertical projection area on the substrate is greater than or equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate.

[0038] Optionally, forming a third barrier layer on a side of the second barrier layer away from the first barrier layer comprises:

[0039] forming a third barrier layer on a side of the second barrier layer away from the first barrier layer, wherein a vertical projection area of ​​the third barrier layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate;

[0040] forming a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer, wherein a vertical projection area of ​​the doped III-V semiconductor layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate;

[0041] The doped III-V semiconductor layer is etched using an etching gas including a chlorine-based etching gas doped with oxygen (O) or fluorine (F) to form a third barrier layer whose vertical projection area on the substrate is equal to the vertical projection area of ​​the second barrier layer on the substrate; and the third barrier layer includes a first part, a second part and a third part, the first part covers the area between the gate structure and the source, the second part covers the area between the gate structure and the drain, the third part is located between the doped III-V semiconductor layer and the second barrier layer, the thickness of the first part is less than the thickness of the third part, and the thickness of the second part is less than the thickness of the third part.

[0042] In the technical solution provided by the embodiment of the present invention, a second barrier layer is arranged between the first barrier layer and the third barrier layer in the composite barrier layer. In the process of patterning the doped III-V semiconductor layer by etching, even if the third barrier layer is overetched, the second barrier layer is used as an etching stop layer and can also be called an in-situ passivation layer to protect the first barrier layer, and the first barrier layer above the channel layer will not be overetched, which can effectively reduce the interface defects of the first barrier layer, thereby avoiding etching damage to the first barrier layer, thereby avoiding affecting the dynamic characteristics and off-state leakage characteristics of the device, optimizing the dynamic characteristics of the enhanced gallium nitride device, reducing the off-state leakage current, reducing the gate leakage current, and improving the gate withstand voltage and reliability. And because there is no over-etching of the first barrier layer above the channel layer, the thickness of the first barrier layer above the channel layer is not lost, thereby avoiding affecting the 2DEG concentration of the device, thereby avoiding affecting the resistance and saturation current of the device, thereby improving the electrical performance of the device.

[0043] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 It is a flow chart of a method for preparing a gallium nitride device provided by the prior art;

[0046] Figure 2 and Figure 3 yes Figure 1 The structural schematic diagram corresponding to each relevant step in the figure;

[0047] Figure 4 is a schematic structural diagram of a gallium nitride device provided by an embodiment of the present invention;

[0048] Figure 5 is a schematic structural diagram of another gallium nitride device provided by an embodiment of the present invention;

[0049] Figure 6 is a flow chart of a method for preparing a gallium nitride device provided by an embodiment of the present invention;

[0050] Figure 7-Figure 11 yes Figure 6 A schematic diagram of the structure of the relevant steps in FIG.

[0051] Fig.12 yes Figure 6 A schematic diagram of a process flow included in S250;

[0052] Fig.13 yes Figure 6 Another flow chart of S250 included in FIG. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0054] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0055] As described in the above background technology, in the current preparation process of GaN devices, when patterning the doped III-V semiconductor layer in the gate structure, the barrier layer on one side of the channel layer is easily over-etched, thereby affecting the electrical performance of the GaN device. Figure 1 as well as Figure 2 and Figure 3 As shown, Figure 1 It is a flow chart of a method for preparing a gallium nitride device provided by the prior art. Figure 2 and Figure 3 yes Figure 1 The structural schematic diagram corresponding to each relevant step in the process, the preparation method of the gallium nitride device includes: S110, providing a stacked structure of a substrate, a channel layer, a barrier layer and a doped III-V semiconductor layer; S120, patterning the doped III-V semiconductor layer; S130, forming a gate on the side of the doped III-V semiconductor layer away from the barrier layer; S140, forming a source and a drain on the side of the barrier layer away from the channel layer. The doped III-V semiconductor layer and the gate constitute a gate structure. In the process of patterning the doped III-V semiconductor layer in the gate structure, it is easy to over-etch the barrier layer on one side of the channel layer, thereby affecting the electrical properties of the gallium nitride device. Figure 2 and Figure 3 The reference numerals included are as follows: 100 - substrate, 101 - channel layer, 102 - barrier layer, 103 - doped Group III-V semiconductor layer, 104 - gate, 105 - source, 106 - drain.

[0056] In order to avoid over-etching the barrier layer on one side of the channel layer, thereby improving the electrical performance of the gallium nitride device, the embodiment of the present invention provides the following technical solution:

[0057] like Figure 4 As shown, Figure 4: is a schematic structural diagram of a gallium nitride device provided by an embodiment of the present invention, the gallium nitride device comprises: a substrate 200; a channel layer 201, located on one side of the substrate 200; a composite barrier layer 001, the composite barrier layer 001 comprises a first barrier layer 202, a second barrier layer 203 and a third barrier layer 204; the first barrier layer 202 is located on a side of the channel layer 201 away from the substrate 200; the second barrier layer 203 is located on a side of the first barrier layer 202 away from the channel layer 201; the second barrier layer 203 is used as an etching stop layer , used to protect the first barrier layer 202; the third barrier layer 204 is located on the side of the second barrier layer 203 away from the first barrier layer 202; the doped III-V semiconductor layer 205 is located on the side of the third barrier layer 204 away from the second barrier layer 203; the gate 206 is located on the side of the doped III-V semiconductor layer 205 away from the third barrier layer 204; the source 207 is located on the side of the first barrier layer 202 away from the channel layer 201; the drain 208 is located on the side of the first barrier layer 202 away from the channel layer 201.

[0058] For example, Figure 4 As shown, the gallium nitride device also includes a buffer layer 209, which is used to alleviate the lattice mismatch problem between the substrate 200 and the channel layer 201. The channel layer 201 includes one or more of a GaN layer, an AlGaN layer, and an InGaN layer. The first barrier layer 202 and the third barrier layer 204 can be one or more of an AlGaN layer, an AlN layer, and an InGaN layer. The doped III-V semiconductor layer 205 is pGaN. The gallium nitride device in the embodiment of the present invention is an enhancement mode GaN high electron mobility transistor (HEMT).

[0059] Optionally, the thickness of the second barrier layer 203 is greater than or equal to 0.1 nm and less than or equal to 3 nm. On the one hand, it can be used as an etching stop layer, and on the other hand, the on-resistance of the device is not reduced due to excessive thickness.

[0060] According to the technical solution provided by the embodiment of the present invention, a second barrier layer 203 is arranged between the first barrier layer 202 and the third barrier layer 204 in the composite barrier layer 001. In the process of patterning the doped III-V semiconductor layer 205 by an etching process, even if the third barrier layer 204 is over-etched, since the second barrier layer 203 is used as an etching stop layer, which can also be called an in-situ passivation layer for protecting the first barrier layer 202, the first barrier layer 202 on the channel layer 201 will not be over-etched, which can effectively reduce the interface defects of the first barrier layer 202, thereby avoiding etching damage to the first barrier layer 202, and further avoiding affecting the dynamic characteristics and off-state leakage characteristics of the device, optimizing the dynamic characteristics of the enhanced gallium nitride device, reducing the off-state leakage current, reducing the gate leakage current, and improving the gate withstand voltage and reliability. Furthermore, since the first barrier layer 202 on the channel layer 201 will not be over-etched, the thickness of the first barrier layer 202 on the channel layer 201 will not be lost, thereby avoiding affecting the 2DEG concentration of the device, and further avoiding affecting the device resistance and saturation current, thereby improving the electrical performance of the device.

[0061] Optionally, based on the above technical solution, Figure 4 As shown, the second barrier layer 203 includes aluminum nitride, and the etching gas for etching the doped III-V semiconductor layer 205 includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

[0062] Specifically, the second barrier layer 203 includes aluminum nitride, and the etching gas for etching the doped III-V semiconductor layer 205 includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F). The aluminum in the second barrier layer 203 and the oxygen (O) in the etching gas generate dense and difficult-to-volatile Al2O3, and the aluminum in the second barrier layer 203 and the fluorine (F) in the etching gas generate dense and difficult-to-volatile AlF3, so that the etching rate of the etching gas for the doped III-V semiconductor layer 205 and the third barrier layer 204 is greater than the etching rate for the second barrier layer 203, so that the second barrier layer 203 is used as an etching stop layer for protecting the first barrier layer 202.

[0063] Optionally, based on the above technical solution, Figure 4 As shown, the second barrier layer 203 includes AlGaN, and the content of Al atoms in the second barrier layer 203 is greater than that in the first barrier layer; the etching gas for etching the doped III-V semiconductor layer 205 includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

[0064] Specifically, the content of Al atoms in the second barrier layer 203 is greater than the content of Al atoms in the first barrier layer 202; the etching gas for etching the doped III-V semiconductor layer 205 includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F), and the aluminum in the second barrier layer 203 and the oxygen (O) in the etching gas generate dense and difficult to volatilize Al2O3, and the aluminum in the second barrier layer 203 and the fluorine (F) in the etching gas generate dense and difficult to volatilize AlF3, so that the etching rate of the etching gas for the doped III-V semiconductor layer 205 and the third barrier layer 204 is greater than the etching rate for the second barrier layer 203, so that the second barrier layer 203 is used as an etching stop layer to protect the first barrier layer 202.

[0065] The second barrier layer 203 includes AlGaN, and the content of Al atoms in the second barrier layer 203 is greater than that in the first barrier layer, or the second barrier layer 203 includes aluminum nitride, so that the second barrier layer 203 also has the effect of reducing gate leakage current and improving gate withstand voltage and reliability.

[0066] Optionally, based on the above technical solution, Figure 4 As shown, the vertical projection area of ​​the third barrier layer 204 on the substrate 200 is smaller than the vertical projection area of ​​the second barrier layer 203 on the substrate 200; the vertical projection area of ​​the third barrier layer 204 on the substrate 200 is greater than or equal to the vertical projection area of ​​the doped III-V semiconductor layer 205 on the substrate 200. Exemplarily, in the figure, the vertical projection area of ​​the third barrier layer 204 on the substrate 200 is equal to the vertical projection area of ​​the doped III-V semiconductor layer 205 on the substrate 200.

[0067] Specifically, in the above technical solution, in the process of patterning the doped III-V semiconductor layer 205 by etching, the third barrier layer 204 is overetched, and the third barrier layer 204 covering the area between the gate structure and the source 207 and the third barrier layer 204 covering the area between the gate structure and the drain 208 are removed. However, since the second barrier layer 203 is used as an etching stop layer, which can also be called an in-situ passivation layer, and is used to protect the first barrier layer 202, the first barrier layer 202 above the channel layer 201 will not be overetched, thereby improving the electrical performance of the device. The gate structure includes a doped III-V semiconductor layer 205 and a gate 206.

[0068] Optionally, based on the above technical solution, Figure 5 As shown, Figure 52 is a schematic structural diagram of another gallium nitride device provided by an embodiment of the present invention, wherein the vertical projection area of ​​the third barrier layer 204 on the substrate 200 is equal to the vertical projection area of ​​the second barrier layer 203 on the substrate 200; the third barrier layer 204 includes a first portion 2041, a second portion 2042 and a third portion 2043, the first portion 2041 covers an area between the gate structure and the source 207, the second portion 2042 covers an area between the gate structure and the drain 208 covered by the third barrier layer 204, the third portion 2043 is located between the doped III-V semiconductor layer 205 and the second barrier layer 203, the thickness of the first portion 2041 is less than the thickness of the third portion 2043, and the thickness of the second portion 2042 is less than the thickness of the third portion 2043.

[0069] Specifically, in the above technical solution, in the process of patterning the doped III-V semiconductor layer 205 by etching, the third barrier layer 204 is overetched, and the third barrier layer 204 covering the area between the gate structure and the source 207 and the third barrier layer 204 covering the area between the gate structure and the drain 208 are not completely removed. The third barrier layer 204 and the second barrier layer 203 in the area that are not completely removed play a role in protecting the first barrier layer 202, thereby further improving the electrical performance of the device.

[0070] The present invention also provides a method for preparing a gallium nitride device. Figure 6 As shown, Figure 6 1 is a flow chart of a method for preparing a gallium nitride device provided by an embodiment of the present invention. The method for preparing a gallium nitride device comprises the following steps:

[0071] S210 , providing a substrate.

[0072] like Figure 7 As shown, a substrate 200 is provided.

[0073] S220 , forming a channel layer on one side of the substrate.

[0074] like Figure 7 As shown, a channel layer 201 is formed on one side of a substrate 200 by an epitaxial process, and the channel layer 201 includes one or more of a GaN layer, an AlGaN layer, and an InGaN layer. In other optional embodiments, a buffer layer 209 may be formed on one side of the substrate 200 before forming the channel layer 201, and the buffer layer 209 is used to alleviate the lattice mismatch problem between the substrate 200 and the channel layer 201.

[0075] S230 , forming a first barrier layer on a side of the channel layer away from the substrate.

[0076] like Figure 7As shown, a first barrier layer 202 is formed on a side of the channel layer 201 away from the substrate 200 by an epitaxial process. The first barrier layer 202 may be one or more of an AlGaN layer, an AlN layer, and an InGaN layer.

[0077] S240 , forming a second barrier layer on a side of the first barrier layer away from the channel layer, wherein the second barrier layer is used as an etching stop layer to protect the first barrier layer.

[0078] As shown in FIG. 7 , a second barrier layer 203 is formed on a side of the first barrier layer 202 away from the channel layer 201 . The second barrier layer 203 is used as an etching stop layer to protect the first barrier layer 202 .

[0079] S250, forming a third barrier layer on a side of the second barrier layer away from the first barrier layer. The first barrier layer, the second barrier layer and the third barrier layer serve as a composite barrier layer.

[0080] like Figure 7 As shown, a third barrier layer 204 is formed on the side of the second barrier layer 203 away from the first barrier layer 202. The third barrier layer 204 can be one or more of an AlGaN layer, an AlN layer, and an InGaN layer. The first barrier layer 202, the second barrier layer 203, and the third barrier layer 204 serve as a composite barrier layer 001.

[0081] S260 , forming a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer.

[0082] like Figure 7 As shown, a doped III-V group semiconductor layer 205 is formed on a side of the third barrier layer 204 away from the second barrier layer.

[0083] S270, patterning the doped III-V semiconductor layer.

[0084] like Figure 8 and Fig. 9 As shown, the doped III-V semiconductor layer 205 is patterned.

[0085] S280 , forming a source electrode on a side of the first barrier layer away from the channel layer.

[0086] like Figure 4 As shown, a source 207 is formed on a side of the first barrier layer 202 away from the channel layer.

[0087] S290 , forming a drain on a side of the first barrier layer away from the channel.

[0088] like Figure 4 As shown, a drain 208 is formed on a side of the first barrier layer 202 away from the channel layer.

[0089] It should be noted that the process of forming the gate 206 includes two methods: Method 1: Before patterning the doped III-V semiconductor layer, a gate is formed on a side of the doped III-V semiconductor layer away from the third barrier layer.

[0090] like Figure 8 and Fig. 9 As shown, before patterning the doped III-V semiconductor layer 205 , a gate 206 is formed on a side of the doped III-V semiconductor layer 205 away from the third barrier layer 204 .

[0091] Alternatively, in method 2: S290 , after forming a drain on a side of the first barrier layer away from the channel, a gate is formed on a side of the doped III-V group semiconductor layer away from the third barrier layer.

[0092] like Fig.10 , Fig.11 and Figure 4 As shown, after the drain 208 is formed on the side of the first barrier layer 202 away from the channel layer 201 , the gate 206 is formed on the side of the doped III-V semiconductor layer 205 away from the third barrier layer 204 .

[0093] The first barrier layer 202 and the third barrier layer 204 may be one or more of an AlGaN layer, an AlN layer and an InGaN layer. The doped III-V semiconductor layer 205 is pGaN. The gallium nitride device in the embodiment of the present invention is an enhancement mode GaN high electron mobility transistor (HEMT).

[0094] According to the technical solution provided by the embodiment of the present invention, a second barrier layer 203 is arranged between the first barrier layer 202 and the third barrier layer 204 in the composite barrier layer 001. In the process of patterning the doped III-V semiconductor layer 205 by an etching process, even if the third barrier layer 204 is over-etched, since the second barrier layer 203 is used as an etching stop layer, which can also be called an in-situ passivation layer for protecting the first barrier layer 202, the first barrier layer 202 on the channel layer 201 will not be over-etched, which can effectively reduce the interface defects of the first barrier layer 202, thereby avoiding etching damage to the first barrier layer 202, and further avoiding affecting the dynamic characteristics and off-state leakage characteristics of the device, optimizing the dynamic characteristics of the enhanced gallium nitride device, reducing the off-state leakage current, reducing the gate leakage current, and improving the gate withstand voltage and reliability. Furthermore, since the first barrier layer 202 on the channel layer 201 will not be over-etched, the thickness of the first barrier layer 202 on the channel layer 201 will not be lost, thereby avoiding affecting the 2DEG concentration of the device, and further avoiding affecting the device resistance and saturation current, thereby improving the electrical performance of the device.

[0095] Optionally, based on the above technical solution, S240 forming a second barrier layer on a side of the first barrier layer away from the channel layer includes:

[0096] A second barrier layer including aluminum nitride is formed on a side of the first barrier layer away from the channel layer. The etching gas for etching the doped III-V semiconductor layer includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

[0097] As shown in FIG. 7 , a second barrier layer 203 including aluminum nitride is formed on a side of the first barrier layer 202 away from the channel layer 201, and the second barrier layer 203 is used as an etching stop layer to protect the first barrier layer 202. The etching gas for etching the doped III-V semiconductor layer 205 includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

[0098] Specifically, the second barrier layer 203 includes aluminum nitride, and the etching gas for etching the doped III-V semiconductor layer 205 includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F). The aluminum in the second barrier layer 203 and the oxygen (O) in the etching gas generate dense and difficult-to-volatile Al2O3, and the aluminum in the second barrier layer 203 and the fluorine (F) in the etching gas generate dense and difficult-to-volatile AlF3, so that the etching rate of the etching gas for the doped III-V semiconductor layer 205 and the third barrier layer 204 is greater than the etching rate for the second barrier layer 203, so that the second barrier layer 203 is used as an etching stop layer for protecting the first barrier layer 202.

[0099] Optionally, based on the above technical solution, S240 forming a second barrier layer on a side of the first barrier layer away from the channel layer includes:

[0100] A second barrier layer including AlGaN is formed on a side of the first barrier layer away from the channel layer, wherein the content of Al atoms in the second barrier layer is greater than the content of Al atoms in the first barrier layer. The etching gas for etching the doped III-V semiconductor layer includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

[0101] As shown in FIG. 7 , a second barrier layer 203 including AlGaN is formed on a side of the first barrier layer 202 away from the channel layer 201, and the second barrier layer 203 is used as an etching stop layer to protect the first barrier layer 202. The etching gas for etching the doped III-V semiconductor layer 205 includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

[0102] Specifically, the content of Al atoms in the second barrier layer 203 is greater than the content of Al atoms in the first barrier layer 202, and the etching gas for etching the doped III-V semiconductor layer 205 includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F). The aluminum in the second barrier layer 203 and the oxygen (O) in the etching gas generate dense and difficult-to-volatile Al2O3, and the aluminum in the second barrier layer 203 and the fluorine (F) in the etching gas generate dense and difficult-to-volatile AlF3, so that the etching rate of the etching gas for the doped III-V semiconductor layer 205 and the third barrier layer 204 is greater than the etching rate for the second barrier layer 203, so that the second barrier layer 203 is used as an etching stop layer for protecting the first barrier layer 202.

[0103] Optionally, based on the above technical solution, Fig.12 As shown, Fig.12 yes Figure 6 A schematic diagram of a process included in S250, wherein S250 forms a third barrier layer on a side of the second barrier layer away from the first barrier layer, including:

[0104] S2501 , forming a third barrier layer on a side of the second barrier layer away from the first barrier layer, wherein a vertical projection area of ​​the third barrier layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate.

[0105] like Figure 4 As shown, a third barrier layer 204 is formed on a side of the second barrier layer 203 away from the first barrier layer 202 , and a vertical projection area of ​​the third barrier layer 204 on the substrate 200 is equal to a vertical projection area of ​​the second barrier layer 203 on the substrate 200 .

[0106] S2502, forming a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer, wherein a vertical projection area of ​​the doped III-V semiconductor layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate.

[0107] like Figure 4 As shown, a doped III-V semiconductor layer 205 is formed on a side of the third barrier layer 204 away from the second barrier layer 203 , and a vertical projection area of ​​the doped III-V semiconductor layer 205 on the substrate 200 is equal to a vertical projection area of ​​the second barrier layer 203 on the substrate 200 .

[0108] S2503. Etch the doped III-V semiconductor layer using an etching gas including a chlorine-based etching gas doped with oxygen (O) or fluorine (F) to form a third barrier layer whose vertical projection area on the substrate is smaller than the vertical projection area of ​​the second barrier layer on the substrate, and whose vertical projection area on the substrate is greater than or equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate.

[0109] like Figure 4 As shown, the doped III-V semiconductor layer 205 is etched using an etching gas including a chlorine-based etching gas doped with oxygen (O) or fluorine (F) to form a third barrier layer 204 whose vertical projection area on the substrate 200 is smaller than the vertical projection area of ​​the second barrier layer 203 on the substrate 200 and whose vertical projection area on the substrate 200 is greater than or equal to the vertical projection area of ​​the doped III-V semiconductor layer 205 on the substrate 200.

[0110] Specifically, in the above technical solution, in the process of patterning the doped III-V semiconductor layer 205 by etching, the third barrier layer 204 is overetched, and the third barrier layer 204 covering the area between the gate structure and the source 207 and the third barrier layer 204 covering the area between the gate structure and the drain 208 are removed. However, since the second barrier layer 203 is used as an etching stop layer, which can also be called an in-situ passivation layer, and is used to protect the first barrier layer 202, the first barrier layer 202 above the channel layer 201 will not be overetched, thereby improving the electrical performance of the device.

[0111] Optionally, based on the above technical solution, Fig.13 As shown, Fig.13 yes Figure 6 Another schematic diagram of a process included in S250, wherein forming a third barrier layer on a side of the second barrier layer away from the first barrier layer includes:

[0112] S2054, forming a third barrier layer on a side of the second barrier layer away from the first barrier layer, wherein a vertical projection area of ​​the third barrier layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate.

[0113] like Figure 5 As shown, a third barrier layer 204 is formed on a side of the second barrier layer 203 away from the first barrier layer 202 , and a vertical projection area of ​​the third barrier layer 204 on the substrate 200 is equal to a vertical projection area of ​​the second barrier layer 203 on the substrate 200 .

[0114] S2505. Form a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer, wherein a vertical projection area of ​​the doped III-V semiconductor layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate.

[0115] like Figure 5 As shown, a doped III-V semiconductor layer 205 is formed on a side of the third barrier layer 204 away from the second barrier layer 203 , and a vertical projection area of ​​the doped III-V semiconductor layer 205 on the substrate 200 is equal to a vertical projection area of ​​the second barrier layer 203 on the substrate 200 .

[0116] S2506. Etch the doped III-V semiconductor layer using an etching gas including a chlorine-based etching gas doped with oxygen (O) or fluorine (F) to form a third barrier layer whose vertical projection area on the substrate is equal to the vertical projection area of ​​the second barrier layer on the substrate; and the third barrier layer includes a first part, a second part and a third part, the first part covers the area between the gate structure and the source, the second part covers the area between the gate structure and the drain, the third part is located between the doped III-V semiconductor layer and the second barrier layer, the thickness of the first part is less than the thickness of the third part, and the thickness of the second part is less than the thickness of the third part.

[0117] like Figure 5 As shown, the doped III-V semiconductor layer 205 is etched using an etching gas including a chlorine-based etching gas doped with oxygen (O) or fluorine (F) to form a third barrier layer 204 whose vertical projection area on the substrate 200 is equal to the vertical projection area of ​​the second barrier layer 203 on the substrate 200; and the third barrier layer 204 includes a first part 2041, a second part 2042 and a third part 2043, the first part 2041 covers the area between the gate structure and the source 207, the second part 2042 covers the area between the gate structure and the drain 208, the third part 2043 is located between the doped III-V semiconductor layer 205 and the second barrier layer 203, the thickness of the first part 2041 is less than the thickness of the third part 2043, and the thickness of the second part 2042 is less than the thickness of the third part 2043.

[0118] Specifically, in the above technical solution, in the process of patterning the doped III-V semiconductor layer 205 by etching, the third barrier layer 204 is overetched, and the third barrier layer 204 covering the area between the gate structure and the source 207 and the third barrier layer 204 covering the area between the gate structure and the drain 208 are not completely removed. The third barrier layer 204 and the second barrier layer 203 in the area that are not completely removed play a role in protecting the first barrier layer 202, thereby further improving the electrical performance of the device.

[0119] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0120] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A gallium nitride device, characterized in that: include: substrate; A channel layer, located on one side of the substrate; A composite barrier layer, the composite barrier layer comprising a first barrier layer, a second barrier layer and a third barrier layer; the first barrier layer is located on a side of the channel layer away from the substrate; the second barrier layer is located on a side of the first barrier layer away from the channel layer; the second barrier layer is used as an etching stop layer for protecting the first barrier layer; the third barrier layer is located on a side of the second barrier layer away from the first barrier layer; a doped III-V group semiconductor layer, located on a side of the third barrier layer away from the second barrier layer; A gate, located on a side of the doped III-V semiconductor layer away from the third barrier layer; A source electrode, located at a side of the first barrier layer away from the channel layer; The drain is located on a side of the first barrier layer away from the channel layer.

2. The gallium nitride device according to claim 1, characterized in that: The second barrier layer includes aluminum nitride, and the etching gas for etching the doped III-V group semiconductor layer includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

3. The gallium nitride device according to claim 1, characterized in that: The second barrier layer includes AlGaN, and the content of Al atoms in the second barrier layer is greater than the content of Al atoms in the first barrier layer; the etching gas for etching the doped III-V semiconductor layer includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

4. The gallium nitride device according to claim 1, characterized in that: The vertical projection area of ​​the third barrier layer on the substrate is smaller than the vertical projection area of ​​the second barrier layer on the substrate; The vertical projection area of ​​the third barrier layer on the substrate is greater than or equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate.

5. The gallium nitride device according to claim 1, characterized in that: The vertical projection area of ​​the third barrier layer on the substrate is equal to the vertical projection area of ​​the second barrier layer on the substrate; The third barrier layer includes a first part, a second part and a third part, the first part covers the area between the gate structure and the source, the second part covers the area between the gate structure and the drain, the third part is located between the doped III-V semiconductor layer and the second barrier layer, the thickness of the first part is less than the thickness of the third part, and the thickness of the second part is less than the thickness of the third part.

6. A method for preparing a gallium nitride device, characterized in that: include: providing a substrate; forming a channel layer on one side of the substrate; forming a first barrier layer on a side of the channel layer away from the substrate; forming a second barrier layer on a side of the first barrier layer away from the channel layer, wherein the second barrier layer is used as an etching stop layer to protect the first barrier layer; forming a third barrier layer on a side of the second barrier layer away from the first barrier layer; the first barrier layer, the second barrier layer and the third barrier layer serve as a composite barrier layer; forming a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer; Patterning the doped III-V semiconductor layer; forming a source electrode on a side of the first barrier layer away from the channel layer; forming a drain on a side of the first barrier layer away from the channel; Before patterning the doped III-V semiconductor layer, a gate is formed on a side of the doped III-V semiconductor layer away from the third barrier layer; or, after forming a drain on a side of the first barrier layer away from the channel layer, a gate is formed on a side of the doped III-V semiconductor layer away from the third barrier layer.

7. The method for preparing a gallium nitride device according to claim 6, characterized in that: Forming a second barrier layer on a side of the first barrier layer away from the channel layer comprises: A second barrier layer including aluminum nitride is formed on a side of the first barrier layer away from the channel layer, and an etching gas for etching the doped III-V semiconductor layer includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

8. The method for preparing a gallium nitride device according to claim 6, characterized in that: Forming a second barrier layer on a side of the first barrier layer away from the channel layer comprises: A second barrier layer including AlGaN is formed on a side of the first barrier layer away from the channel layer, and a content of Al atoms in the second barrier layer is greater than a content of Al atoms in the first barrier layer; and an etching gas for etching the doped III-V semiconductor layer includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).

9. The method for preparing a gallium nitride device according to claim 6, characterized in that: Forming a third barrier layer on a side of the second barrier layer away from the first barrier layer comprises: forming a third barrier layer on a side of the second barrier layer away from the first barrier layer, wherein a vertical projection area of ​​the third barrier layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate; forming a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer, wherein a vertical projection area of ​​the doped III-V semiconductor layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate; The doped III-V semiconductor layer is etched using an etching gas including a chlorine-based etching gas doped with oxygen (O) or fluorine (F) to form a third barrier layer whose vertical projection area on the substrate is smaller than the vertical projection area of ​​the second barrier layer on the substrate, and whose vertical projection area on the substrate is greater than or equal to the vertical projection area of ​​the doped III-V semiconductor layer on the substrate.

10. The method for preparing a gallium nitride device according to claim 6, characterized in that: Forming a third barrier layer on a side of the second barrier layer away from the first barrier layer comprises: forming a third barrier layer on a side of the second barrier layer away from the first barrier layer, wherein a vertical projection area of ​​the third barrier layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate; forming a doped III-V semiconductor layer on a side of the third barrier layer away from the second barrier layer, wherein a vertical projection area of ​​the doped III-V semiconductor layer on the substrate is equal to a vertical projection area of ​​the second barrier layer on the substrate; The doped III-V semiconductor layer is etched using an etching gas including a chlorine-based etching gas doped with oxygen (O) or fluorine (F) to form a third barrier layer whose vertical projection area on the substrate is equal to the vertical projection area of ​​the second barrier layer on the substrate; and the third barrier layer includes a first part, a second part and a third part, the first part covers the area between the gate structure and the source, the second part covers the area between the gate structure and the drain, the third part is located between the doped III-V semiconductor layer and the second barrier layer, the thickness of the first part is less than the thickness of the third part, and the thickness of the second part is less than the thickness of the third part.

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