Fully-depleted strained silicon MOS device on insulator and preparation method thereof

Abstract

The invention discloses a strained silicon MOS device on a fully-depleted insulator and a preparation method thereof, the device comprises an SOI substrate, the upper surface of the SOI substrate is sequentially provided with a shallow groove channel isolation region, a first epitaxial groove, a second epitaxial groove and a second shallow groove channel isolation region along a first direction, the shallow groove channel isolation region comprises an isolation filling material, the epitaxial groove is internally provided with an epitaxial layer, and the first epitaxial groove and the second epitaxial groove are communicated with each other; a source electrode / drain electrode is arranged on the epitaxial layer; the substrate between the epitaxial grooves is a strained silicon layer, a gate oxide layer is arranged on the upper surface of the strained silicon layer, and a gate is arranged on the upper surface of the gate oxide layer; the thermal expansion coefficient of the isolation filling material is different from that of the strained silicon layer, and the lattice constant of the epitaxial layer material is different from that of the strained silicon layer. According to the invention, two uniaxial compressive stresses from different sources are introduced into the channel region of the MOS device, so that the carrier mobility can be improved, and the performance of the MOS device is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a strained silicon-on-insulator MOS device and a preparation method thereof. Background Art

[0002] The rapidly developing integrated circuit industry has increasingly higher requirements on the performance of MOS devices. Currently, there are two popular methods for improving the performance of MOS devices: one is stress introduction technology, and the other is metal silicide strain introduction technology.

[0003] Stress introduction technology is a local stress introduction technology used in NMOS, NFET, etc., which can effectively improve the electron transport performance and reduce the leakage current. This method mainly includes the following steps: amorphization of polysilicon, deposition of a liner with tensile stress, rapid annealing, and liner removal. Although the tensile layer is removed, the stress is memorized through the annealing process, so that the channel still retains the stress after the liner is removed. However, this technology is mainly suitable for N-type devices, and will cause the performance of the device to decrease when used to make P-type devices.

[0004] Similarly, in the metal silicide strain introduction technology, due to the difference in thermal expansion coefficients between silicide and silicon, the metal silicidation reaction causes lattice mismatch and generates internal tensile stress, which reduces the PMOS performance.

[0005] In addition, there is another method with a wide range of applications that can improve the performance of PMOS devices, which is strained silicon technology. Since the strained silicon process (not the above-mentioned metal silicide strain introduction technology) is compatible with the current silicon process, it can continuously adjust the energy band and improve the mobility of carriers in MOS devices, so it is widely used in CMOS processes to enhance the performance of devices. The stress introduced into MOS devices can be divided into uniaxial stress and biaxial stress from the stress direction. The introduced stress can cause the energy level of the material to split, causing a change in the effective mass of carriers and thus affecting the carrier mobility. The basic principle of this stress introduction is lattice mismatch. The material in contact with silicon and silicon both grow along the lattice, but the different lattice coefficients will generate stress.

[0006] However, the current strained silicon process can only introduce a single stress in MOS devices, resulting in the performance of MOS devices being still relatively low. Summary of the invention

[0007] The embodiment of the present invention provides a fully depleted strained silicon-on-insulator MOS device and a preparation method thereof, which can solve the problem that the current strained silicon process can only introduce a single stress in the MOS device, resulting in low performance during the MOS process.

[0008] In a first aspect, an embodiment of the present invention provides a fully depleted strained silicon-on-insulator MOS device, comprising:

[0009] An SOI substrate, wherein a first shallow trench isolation region, a first epitaxial trench, a second epitaxial trench, and a second shallow trench isolation region are sequentially arranged on an upper surface of the SOI substrate along a first direction, a strained silicon layer is formed on the SOI substrate between the first epitaxial trench and the second epitaxial trench, the trench depths of the first shallow trench isolation region and the second shallow trench isolation region are greater than the trench depths of the first epitaxial trench and the second epitaxial trench, and the first shallow trench isolation region and the second shallow trench isolation region both contain an isolation filling material;

[0010] A first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are respectively arranged in a first epitaxial trench and a second epitaxial trench, and the thickness of the first epitaxial layer and the second epitaxial layer is less than the trench depth of the first epitaxial trench and the second epitaxial trench;

[0011] The lattice coefficients of the materials of the first epitaxial layer and the second epitaxial layer are different from the lattice coefficients of the material of the strained silicon layer, and the thermal expansion coefficient of the isolation filling material is different from the thermal expansion coefficient of the material of the strained silicon layer;

[0012] A source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively arranged on the upper surfaces of the first epitaxial layer and the second epitaxial layer;

[0013] A gate oxide layer, the gate oxide layer is arranged on the upper surface of the strained silicon layer;

[0014] The gate is arranged on the upper surface of the gate oxide layer.

[0015] In a second aspect, an embodiment of the present invention provides a method for preparing a fully depleted strained silicon-on-insulator MOS device, comprising:

[0016] preparing an SOI substrate;

[0017] Etching a first shallow trench isolation region and a second shallow trench isolation region at two sides of the upper surface of the SOI substrate at a preset angle, and depositing an isolation filling material in the first shallow trench isolation region and the second shallow trench isolation region;

[0018] Depositing a gate oxide layer and a gate in sequence on the upper surface of a portion of the SOI substrate located between the first shallow trench isolation region and the second shallow trench isolation region;

[0019] Performing ion implantation on the SOI substrate located between the first shallow trench isolation region and the gate and the SOI substrate located between the second shallow trench isolation region and the gate, respectively, to form a source region and a drain region in the SOI substrate;

[0020] Etching the source region and the drain region respectively to form a first epitaxial groove and a second epitaxial groove, and forming a strained silicon layer in the SOI substrate between the first epitaxial groove and the second epitaxial groove, wherein the groove depths of the first epitaxial groove and the second epitaxial groove are less than the groove depths of the first shallow trench isolation region and the second shallow trench isolation region;

[0021] Depositing epitaxial metal in the first epitaxial trench, and performing ion implantation on the epitaxial metal having a relative height greater than a preset height value, so as to form a first epitaxial layer and a source electrode, wherein the preset height value is less than a trench depth of the first epitaxial trench, and the first epitaxial layer is formed by the epitaxial metal located in the first epitaxial trench and not subjected to ion implantation;

[0022] Epitaxial metal is deposited in the second epitaxial trench, and ion implantation is performed on the epitaxial metal having a relative height greater than a preset height value to form a second epitaxial layer and a drain, wherein the preset height value is less than the trench depth of the second epitaxial trench, and the second epitaxial layer is formed by the epitaxial metal located in the second epitaxial trench and not ion implanted.

[0023] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: according to the MOS device provided by the present invention, by arranging a strained silicon layer in the channel region between the source and the drain, and arranging epitaxial layers with lattice constants different from those of the strained silicon layer on both sides of the strained silicon layer, a uniaxial compressive stress can be introduced into the channel region based on the lattice mismatch principle; by arranging shallow trench isolation regions with thermal expansion coefficients different from those of the strained silicon layer on both sides of the strained silicon layer, another uniaxial compressive stress can be introduced into the channel region; thereby, a composite uniaxial stress is introduced into the channel region of the MOS device instead of a single stress generated by a single strain source, which can greatly increase the carrier mobility and thus improve the performance of the MOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic structural diagram of a fully depleted strained silicon-on-insulator MOS device provided in an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of the structure of an SOI substrate provided in an embodiment of the present invention;

[0026] Figure 3 A flowchart of a method for preparing a fully depleted strained silicon-on-insulator MOS device provided by an embodiment of the present invention;

[0027] Figure 4-Figure 7 A schematic diagram of a scenario for preparing a fully depleted strained silicon-on-insulator MOS device provided in an embodiment of the present invention;

[0028] Figure 8 A schematic diagram of a preset height value provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0030] Example 1

[0031] Figure 1 The structure diagram of a fully depleted strained silicon-on-insulator MOS device provided by an embodiment of the present invention is shown. As an example but not limitation, the MOS device 100 may include an SOI substrate 1, a first epitaxial layer 2, a second epitaxial layer 3, a source 4, a drain 5, a gate oxide layer 6, and a gate 7.

[0032] For details, see Figure 2 , on the upper surface of the SOI substrate 1, along the first direction (see Figure 2 In the direction indicated by the arrow 201 in the middle), a first shallow trench isolation region 81, a first epitaxial trench 21, a second epitaxial trench 31, and a second shallow trench isolation region 82 may be sequentially provided. A strained silicon layer 11 is formed on the SOI substrate between the first epitaxial trench 21 and the second epitaxial trench 31. Figure 1 The first epitaxial layer 2 and the second epitaxial layer 3 are arranged in the first epitaxial groove 21 and the second epitaxial groove 31, a source 4 is arranged on the upper surface of the first epitaxial layer 2, a drain 4 is arranged on the upper surface of the second epitaxial layer 3, a gate oxide layer 6 is arranged on the upper surface of the strained silicon layer 11, and a gate 7 is arranged on the upper surface of the gate oxide layer 6.

[0033] Exemplarily, the first shallow trench isolation region 81 and the second shallow trench isolation region 82 both include isolation filling materials.

[0034] For example, see Figure 1 and Figure 2 The thickness of the first epitaxial layer 2 and the second epitaxial layer 3 is less than the depth of the first epitaxial groove 21 and the second epitaxial groove 31 ; thus, the source 4 and the drain 5 located on the first epitaxial layer 2 and the second epitaxial layer 3 , respectively, can be embedded in the first epitaxial groove 21 and the second epitaxial groove 31 .

[0035] The source 4 and the drain 5 are respectively disposed in the first epitaxial groove 21 and the second epitaxial groove 31 in an embedded manner, so that the MOS device can maintain a high level of carrier mobility under a large electric field and reduce the channel resistance and the extension resistance of the MOS device 100 .

[0036] In some embodiments, see Figure 1 and Figure 2 The SOI substrate may include at least a silicon substrate layer 13, a buried oxide layer 12 and a strained silicon layer 11 stacked in sequence from the bottom.

[0037] For a substrate of the SOI structure of silicon layer-buried oxide layer-silicon layer, due to the existence of the buried oxide layer 12, there is no conductive path between the source 4 and drain 5 for collecting charges and the silicon substrate layer 13, and the channel region is small in volume and can only generate limited excited charges; therefore, this structure is less likely to generate large drift currents and diffusion currents, and can eliminate the single-particle latch-up effect caused by integrated transistors that cannot be avoided in traditional bulk silicon processes from the level of the device's physical structure.

[0038] In a possible implementation, the materials of the silicon substrate layer 13 and the strained silicon layer 11 may both include Si, and the material of the buried oxide layer 12 may include SiO 2 .

[0039] In one example, the thermal expansion coefficient of the isolation filling material may be different from the thermal expansion coefficient of the material of the strained silicon layer 11 .

[0040] Exemplarily, when the thermal expansion coefficient of the isolation filling material is different from that of the material of the strained silicon layer, the isolation filling material of the shallow trench isolation (STI) region located on both sides of the strained silicon layer 11 generates compressive stress to squeeze the active region (i.e., the source 4 and the drain 5), thereby introducing a uniaxial compressive stress in the channel region of the MOS device 100, thereby improving the carrier mobility and thus improving the performance of the MOS device 100.

[0041] Optionally, the isolation filling material may be SiO2.

[0042] In a possible implementation, the thickness of the silicon substrate layer 13 may be 3-5 μm, the thickness of the strained silicon layer 11 may be 100-200 nm, and the thickness of the buried oxide layer 12 may be 400-500 nm.

[0043] In one example, see Figure 2 The depths of the first epitaxial trench 21 and the second epitaxial trench 31 are smaller than the depths of the first shallow trench isolation region 81 and the second shallow trench isolation region 82 .

[0044] Exemplarily, the first epitaxial trench 21 and the second epitaxial trench 31 may extend to the upper surface of the buried oxide layer 12 , and the first shallow trench isolation region 81 and the second shallow trench isolation region 82 may extend to the silicon substrate layer 13 .

[0045] Optionally, the trench depths of the first shallow trench isolation region 81 and the second shallow trench isolation region 82 may be 500-600 nm.

[0046] Optionally, the trench depth of the first epitaxial trench 21 and the second epitaxial trench 31 may be about 60 nm.

[0047] In some embodiments, the lattice constant of the material of the first epitaxial layer 2 and the second epitaxial layer 3 may be different from the lattice constant of the material of the strained silicon layer 11 .

[0048] For example, since the lattice constant of the material of the epitaxial layer is different from the lattice constant of the material of the strained silicon layer 11, and the strained silicon layer 11 is located in the channel region between the source 4 and the drain 5, another uniaxial compressive stress caused by the epitaxial layer can be introduced in the channel region, thereby further increasing the carrier mobility and improving the performance of the MOS device 100.

[0049] In a possible implementation, the material of the first epitaxial layer 2 and the second epitaxial layer 3 may include SiGe.

[0050] Exemplarily, since the lattice constant of SiGe is greater than that of Si, the strained silicon layer 11 may be compressed by the first epitaxial layer 2 and the second epitaxial layer 3 .

[0051] In a possible implementation, the thickness of the first epitaxial layer 2 and the second epitaxial layer 3 may range from 20 to 70 nm.

[0052] In some embodiments, the shape of the upper surface of the source 4 and the drain 5 can be convex, which can increase the thickness and surface area of ​​the active region of the MOS device 100, form a thicker self-aligned silicide, reduce the contact resistance of the source 4 and the drain 5, and reduce the increase in relative contact resistance due to the increase in size.

[0053] In a possible implementation, the MOS device 100 may be a P-type device or an N-type device.

[0054] In one example, if the MOS device 100 is a P-type device, the source 4 and the drain 5 may be P-type doped junctions, which are doped with elements such as boron.

[0055] Exemplarily, doping the epitaxially grown portions protruding from the upper surfaces of the source and drain with boron elements can also increase the activation degree of boron ions in the source and drain regions of the MOS device and reduce the spreading resistance.

[0056] In another example, if the MOS device 100 is an N-type device, the source 4 and the drain 5 may be N-type doped junctions, and may be doped with elements such as phosphorus.

[0057] In a possible implementation, the thickness of the source electrode 4 and the drain electrode 5 may range from 50 to 70 nm.

[0058] In some embodiments, the gate oxide layer 6 may be made of SiO 2 and may have a thickness ranging from 100 to 200 nm.

[0059] In some embodiments, the material of the gate 7 may include polysilicon.

[0060] According to the MOS device provided by the present invention, a strained silicon layer is arranged in the channel region between the source and the drain, and epitaxial layers with lattice constants different from those of the strained silicon layer are arranged on both sides of the strained silicon layer, so that a uniaxial compressive stress can be introduced in the channel region based on the lattice mismatch principle; and another uniaxial compressive stress can be introduced in the channel region by arranging shallow trench channel isolation regions with thermal expansion coefficients different from those of the strained silicon layer on both sides of the strained silicon layer; thereby, composite uniaxial stress is introduced in the channel region of the MOS device instead of a single stress generated by a single strain source, so that carrier mobility can be greatly increased, thereby improving the performance of the MOS device.

[0061] Example 2

[0062] Figure 3 The flowchart shown is a method for preparing a fully depleted strained silicon-on-insulator MOS device provided by an embodiment of the present invention. As an example but not a limitation, the preparation method can be used to prepare the MOS device 100 in Example 1. The preparation method can include steps S301-S307, and each step is described below.

[0063] S301, preparing an SOI substrate.

[0064] In one example, a silicon wafer (eg, a silicon wafer substrate bare chip) may be selected and oxygen ion implanted therein, and then high-temperature annealing may be performed to obtain an SOI substrate 1 .

[0065] For example, 0.3e18cm -2 -1.8e18cm -2 The oxygen ions injected into the silicon wafer are distributed below the upper surface of the silicon wafer. After 3-6 hours of high temperature annealing at 1350°C, the oxygen ions in the silicon wafer react chemically with silicon to form a silicon dioxide insulating layer (i.e., buried oxide layer 12) with a thickness of about 400nm below the upper surface of the silicon wafer, thereby forming an SOI substrate 1 (see Figure 4 ).

[0066] S302, etching a first shallow trench isolation region and a second shallow trench isolation region at both sides of the upper surface of the SOI substrate at a preset angle, and depositing an isolation filling material in the first shallow trench isolation region and the second shallow trench isolation region.

[0067] In one example, before etching the shallow trench isolation region, an oxide protection layer (SiO2) can be deposited on the upper surface of the SOI substrate to protect the active area of ​​the device from chemical contamination during the subsequent removal of the nitride protection layer; and a nitride protection layer (SiN) is deposited on the oxide protection layer to protect the active area during the deposition of the isolation filling material, so as to obtain the following: Figure 5 The structure shown in (a) in FIG. The two protective layers are etched away while subsequently etching the shallow trench isolation region.

[0068] In one example, a first shallow trench isolation region 81 and a second shallow trench isolation region 82 can be etched at a preset angle (e.g., 87°) on both sides of the upper surface of the SOI substrate, and then an isolation filling material (e.g., SiO2) is deposited in the first shallow trench isolation region 81 and the second shallow trench isolation region 82 by a chemical vapor deposition process to obtain a Figure 5 The structure shown in (b).

[0069] For example, the thermal expansion coefficient of the isolation filling material is different from the thermal expansion coefficient of the material of the stress silicon layer 11, resulting in the first shallow trench isolation region 81 and the second shallow trench isolation region 82 generating compressive stress to squeeze the active region, thereby introducing uniaxial compressive stress in the channel region, improving carrier mobility, and improving device performance. The application of shallow trench isolation technology can also isolate components in the circuit, effectively reduce the circuit latch effect, protect the normal operation of the circuit and the device, and not affect the normal operation of the source and drain regions inside the device.

[0070] S303, depositing a gate oxide layer and a gate in sequence on the upper surface of a portion of the SOI substrate located between the first shallow trench isolation region and the second shallow trench isolation region.

[0071] In one example, a thermal oxidation technique may be used to grow a gate oxide layer 6, and then a chemical vapor deposition process may be used to deposit a gate 7 on the gate oxide layer 6, to obtain: Figure 6 The structure shown.

[0072] For example, at a temperature of about 900° C., a wet oxygen oxidation method may be used to introduce a mixed gas of H2 and O2; then a dry oxygen oxidation method may be used to introduce high-purity O2 to oxidize silicon to form a gate oxide layer 6. Afterwards, annealing is performed in N2 at a temperature of 900° C. for 10 minutes, and then polysilicon is deposited at a temperature of 700° C. to form a gate 7.

[0073] S304, ion implantation is performed on the SOI substrate located between the first shallow trench isolation region and the gate and the SOI substrate located between the second shallow trench isolation region and the gate, respectively, to form a source region and a drain region in the SOI substrate.

[0074] In one example, see Figure 6 , can be Figure 6 Ion implantation is performed at a preset position 601 of the source region and a preset position 602 of the drain region to form a source region and a drain region of the MOS device 100, respectively. Figure 7 The structure shown in (a) in .

[0075] For example, if the MOS device 100 is a P-type device, boron ions may be doped under the conditions of an energy of 0.18 keV and a dosage of 1.5×10 15 cm −2 .

[0076] S305 , etching the source region and the drain region respectively to form a first epitaxial trench and a second epitaxial trench, and forming a strained silicon layer in the SOI substrate between the first epitaxial trench and the second epitaxial trench.

[0077] In one example, the source region and the drain region can be etched back by selective etching technology to form the first epitaxial groove 21 and the second epitaxial groove 31. Figure 7 The structure shown in (b).

[0078] S306, depositing an epitaxial metal in the first epitaxial trench, and performing ion implantation on the epitaxial metal having a relative height greater than a preset height value, so as to form a first epitaxial layer and a source electrode.

[0079] For example, see Figure 8 The relative height may be the height of the epitaxial metal relative to the upper surface of the SOI substrate in the epitaxial trench.

[0080] Exemplarily, the preset height value may be smaller than the depth of the first epitaxial trench 21 , so that the source 4 may be embedded in the first epitaxial trench 21 .

[0081] For example, the first epitaxial trench has a depth of 60 nm and a preset height of 20 nm. Figure 8 The portion with a height less than 20 nm is an epitaxial layer, and ion implantation is performed on the epitaxial metal with a height greater than 20 nm to obtain a source electrode embedded in the first epitaxial groove 21 .

[0082] For example, see Figure 7 In (c), the first epitaxial layer 2 is formed by the epitaxial metal located in the first epitaxial trench 21 without ion implantation, and the remaining epitaxial metal with ion implantation forms the source 4.

[0083] In one example, an epitaxial growth process may be used to grow an epitaxial metal (eg SiGe) in the first epitaxial trench 21 , and then an in-situ doping technique may be used to perform ion implantation to form the first epitaxial layer 2 and the source 4 .

[0084] For example, a SiGe material with a Ge molar composition of 17% can be epitaxially grown at 550° C. and a doping concentration of 1.5×1020 cm -2 Ion implantation is performed under the conditions of .

[0085] S307, depositing an epitaxial metal in the second epitaxial trench, and performing ion implantation on the epitaxial metal having a relative height greater than a preset height value, so as to form a second epitaxial layer and a drain.

[0086] Similarly, the preset height value is smaller than the depth of the second epitaxial trench 31. Figure 7 The second epitaxial layer 3 in (c) is formed by the epitaxial metal located in the second epitaxial trench but not ion-implanted, and the rest of the epitaxial metal that has been ion-implanted forms the drain 5 .

[0087] In one example, an epitaxial growth process may be used to grow an epitaxial metal (eg SiGe) in the second epitaxial trench 31 , and then an in-situ doping technique may be used to perform ion implantation to form the second epitaxial layer 3 and the drain 5 .

[0088] For example, a SiGe material with a Ge molar composition of 17% can be epitaxially grown at 550° C. and a doping concentration of 1.5×10 20 cm -2 Ion implantation is performed under the conditions of .

[0089] Optionally, the upper surfaces of the source electrode 4 and the drain electrode 5 may be convex.

[0090] Since the active area of ​​silicon on fully depleted insulator is very thin, the epitaxial growth technology can make the active area protrude, increase the thickness and surface area of ​​the active area, thereby forming a thicker self-aligned silicide, reducing the contact resistance of the source and drain, and the increase in relative contact resistance caused by the increase in size.

[0091] At the same time, since the lattice constants of the epitaxial metal and the strained silicon layer are different, the epitaxially grown source and drain and the epitaxial layer will generate compressive strain on the channel region, thereby increasing carrier mobility and thus improving the performance of the MOS device 100 .

[0092] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0093] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0094] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0095] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, any modifications made without departing from the concept of the present invention should be deemed to belong to the protection scope of the present invention.

Claims

1. A fully depleted strained silicon-on-insulator MOS device, characterized in that: include: An SOI substrate, wherein a first shallow trench isolation region, a first epitaxial trench, a second epitaxial trench, and a second shallow trench isolation region are sequentially arranged on an upper surface of the SOI substrate along a first direction, a strained silicon layer is formed on the SOI substrate between the first epitaxial trench and the second epitaxial trench, the trench depths of the first shallow trench isolation region and the second shallow trench isolation region are greater than the trench depths of the first epitaxial trench and the second epitaxial trench, and the first shallow trench isolation region and the second shallow trench isolation region both contain an isolation filling material; A first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are respectively arranged in the first epitaxial trench and the second epitaxial trench, and the thickness of the first epitaxial layer and the second epitaxial layer is less than the trench depth of the first epitaxial trench and the second epitaxial trench; The lattice coefficients of the materials of the first epitaxial layer and the second epitaxial layer are different from the lattice coefficients of the material of the strained silicon layer, and the thermal expansion coefficient of the isolation filling material is different from the thermal expansion coefficient of the material of the strained silicon layer; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively arranged on the upper surfaces of the first epitaxial layer and the second epitaxial layer; A gate oxide layer, wherein the gate oxide layer is disposed on an upper surface of the strained silicon layer; A gate is disposed on an upper surface of the gate oxide layer.

2. The MOS device according to claim 1, characterized in that: The SOI substrate comprises a silicon substrate layer, a buried oxide layer and the strained silicon layer stacked in sequence from bottom to top.

3. The MOS device according to claim 2, characterized in that: The first epitaxial trench and the second epitaxial trench extend to the upper surface of the buried oxide layer, and the first shallow trench isolation region and the second shallow trench isolation region extend into the silicon substrate layer.

4. The MOS device according to claim 1, characterized in that: The upper surfaces of the source electrode and the drain electrode are convex.

5. The MOS device according to claim 1, characterized in that: The material of the first epitaxial layer and the second epitaxial layer includes SiGe, and the material of the strained silicon layer includes Si.

6. The MOS device according to claim 5, characterized in that: The thickness of the first epitaxial layer and the second epitaxial layer ranges from 50 to 70 nm.

7. The MOS device according to claim 1, characterized in that: The isolation filling material includes SiO2, and the material of the strained silicon layer includes Si.

8. The MOS device according to claim 7, characterized in that: The trench depths of the first shallow trench isolation region and the second shallow trench isolation region range from 500 nm to 600 nm.

9. A method for preparing a fully depleted strained silicon-on-insulator MOS device, characterized in that: include: preparing an SOI substrate; Etching a first shallow trench isolation region and a second shallow trench isolation region at a preset angle on both sides of the upper surface of the SOI substrate, and depositing an isolation filling material in the first shallow trench isolation region and the second shallow trench isolation region; Depositing a gate oxide layer and a gate in sequence on the upper surface of a portion of the SOI substrate located between the first shallow trench isolation region and the second shallow trench isolation region; Performing ion implantation on the SOI substrate located between the first shallow trench isolation region and the gate and the SOI substrate located between the second shallow trench isolation region and the gate, respectively, to form a source region and a drain region in the SOI substrate; Etching the source region and the drain region respectively to form a first epitaxial trench and a second epitaxial trench, and forming a strained silicon layer in the SOI substrate between the first epitaxial trench and the second epitaxial trench, wherein the trench depths of the first epitaxial trench and the second epitaxial trench are less than the trench depths of the first shallow trench trench isolation region and the second shallow trench trench isolation region; Depositing epitaxial metal in the first epitaxial trench, and performing ion implantation on the epitaxial metal having a relative height greater than a preset height value, so as to form a first epitaxial layer and a source electrode, wherein the preset height value is less than a trench depth of the first epitaxial trench, and the first epitaxial layer is formed by the epitaxial metal located in the first epitaxial trench and not subjected to ion implantation; Epitaxial metal is deposited in the second epitaxial trench, and ion implantation is performed on the epitaxial metal having a relative height greater than a preset height value to form a second epitaxial layer and a drain, wherein the preset height value is less than a trench depth of the second epitaxial trench, and the second epitaxial layer is formed by the epitaxial metal located in the second epitaxial trench and not subjected to ion implantation.

10. The preparation method according to claim 9, characterized in that: Before etching the first shallow trench isolation region and the second shallow trench isolation region at both sides of the upper surface of the SOI substrate at a preset angle, the method further includes: An oxidation protection layer and a nitride protection layer are sequentially deposited on the upper surface of the SOI substrate to protect the active area of ​​the MOS device, and the oxidation protection layer and the nitride protection layer are etched away while etching the first shallow trench isolation area and the second shallow trench isolation area.

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