Thin film transistor and preparation method thereof, array substrate and display panel

Abstract

The invention relates to a thin film transistor and a preparation method thereof, an array substrate and a display panel. The thin film transistor includes: a substrate; the active layer is located on one side of the substrate, the active layer comprises at least two first sub-active layers and at least one second sub-active layer, and the first sub-active layers and the second sub-active layers are alternately stacked; the forbidden bandwidth of the first sub-active layer is larger than that of the second sub-active layer, and the carrier mobility of the second sub-active layer is larger than that of the first sub-active layer. By applying the thin film transistor provided by the invention, the carrier mobility and the stability of a device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a thin film transistor and a preparation method thereof, an array substrate, and a display panel. Background Art

[0002] The development of virtual reality (VR) and augmented reality (AR) technologies has put forward higher requirements for display devices. Compared with single crystal silicon (a-Si) and low temperature polycrystalline silicon (LTPS), metal oxide thin film transistors (TFTs) represented by indium gallium zinc oxide (IGZO) have the advantages of low off-state current (Ioff), good device uniformity and large-area preparation, which have attracted widespread attention in the field of modern reality. However, the poor stability and low carrier mobility of traditional metal oxide thin film transistors limit their application in the next generation of displays. Summary of the invention

[0003] Based on this, it is necessary to provide a thin film transistor and a preparation method thereof, an array substrate, and a display panel to address the problem of how to significantly improve the stability of the device while improving the carrier mobility of the device.

[0004] A thin film transistor, comprising:

[0005] substrate; and

[0006] An active layer, located on one side of the substrate, the active layer comprising at least two first sub-active layers and at least one second sub-active layer, and the first sub-active layers and the second sub-active layers are alternately stacked;

[0007] The bandgap width of the first sub-active layer is greater than the bandgap width of the second sub-active layer, and the carrier mobility of the second sub-active layer is greater than the carrier mobility of the first sub-active layer.

[0008] In the thin film transistor using the technical solution of the present invention, on the one hand, the carrier mobility of the second sub-active layer is greater than that of the first sub-active layer, which can improve the carrier mobility of the device; on the other hand, since the first sub-active layer and the second sub-active layer are alternately stacked and the band gap width of the first sub-active layer is greater than that of the second sub-active layer, the carriers can be subjected to conduction band shifting during their movement, which greatly reduces the capture of carriers in the deep hydrazine state at the interface of the gate insulating layer, thereby improving the stability of the device.

[0009] In a feasible implementation, a difference between a bandgap width of the first sub-active layer and a bandgap width of the second sub-active layer is greater than or equal to 1.0 eV;

[0010] Preferably, the difference between the bandgap width of the first sub-active layer and the bandgap width of the second sub-active layer is 1.5 eV to 2 eV;

[0011] Preferably, the bandgap width of the first sub-active layer is greater than or equal to 3.0 eV, and the bandgap width of the second sub-active layer is less than or equal to 2.5 eV;

[0012] Preferably, the bandgap width of the second sub-active layer is 1.0 eV to 2.5 eV.

[0013] In a feasible implementation, the carrier mobility of the second sub-active layer is greater than or equal to twice the carrier mobility of the first sub-active layer;

[0014] Preferably, the carrier mobility of the second sub-active layer is greater than or equal to 20 cm 2 / V·s.

[0015] In a feasible implementation, the first sub-active layer includes a metal oxide semiconductor material, and the material of the second sub-active layer includes at least one of ZnON, TiO2 and MoS2;

[0016] Preferably, the metal oxide semiconductor material is selected from at least one of ZnO, SnO, TZO, ATZO and lanthanide oxides.

[0017] In a feasible implementation, the sum of the number of layers of the first sub-active layer and the second sub-active layer is three to seven, and the number of layers of the first sub-active layer is greater than or equal to the number of layers of the second sub-active layer;

[0018] Preferably, the active layer comprises a first sub-active layer, a second sub-active layer and a first sub-active layer which are alternately stacked;

[0019] Preferably, the active layer comprises a first sub-active layer, a second sub-active layer, a first sub-active layer, a second sub-active layer and a first sub-active layer which are alternately stacked;

[0020] Preferably, the active layer includes a first sub-active layer, a second sub-active layer, a first sub-active layer, a second sub-active layer, a first sub-active layer, a second sub-active layer and a first sub-active layer which are alternately stacked.

[0021] In a feasible implementation, the thin film transistor further includes:

[0022] A first gate, located on a side of the substrate close to the active layer;

[0023] A buffer layer, located between the first gate and the active layer;

[0024] A gate insulating layer, located on a side of the active layer away from the substrate;

[0025] A second gate is located at a side of the gate insulating layer away from the substrate;

[0026] an interlayer insulating layer, located on a side of the second gate away from the substrate;

[0027] a source electrode electrically connected to the active layer; and

[0028] The drain electrode is electrically connected to the active layer.

[0029] A method for preparing a thin film transistor comprises the following steps:

[0030] providing a substrate; and

[0031] An active layer is formed on the substrate, wherein the active layer includes at least two first sub-active layers and at least one second sub-active layer, and the first sub-active layers and the second sub-active layers are alternately stacked; the bandgap width of the first sub-active layer is greater than the bandgap width of the second sub-active layer, and the carrier mobility of the second sub-active layer is greater than the carrier mobility of the first sub-active layer.

[0032] The method for preparing the thin film transistor of the technical solution of the present invention has a simple process. In the prepared thin film transistor, on the one hand, the carrier mobility of the second sub-active layer is greater than that of the first sub-active layer, which can improve the carrier mobility of the device; on the other hand, since the first sub-active layer and the second sub-active layer are alternately stacked and the band gap width of the first sub-active layer is greater than that of the second sub-active layer, the carriers can be subjected to conduction band deviation during the movement process, which greatly reduces the carriers being captured in the deep hydrazine state at the interface of the gate insulating layer, thereby improving the stability of the device.

[0033] In a feasible implementation, the following steps are included:

[0034] providing a substrate;

[0035] forming a first gate on the substrate;

[0036] forming a buffer layer on the first gate;

[0037] forming an active layer on the buffer layer;

[0038] forming a gate insulating layer on the active layer, and forming a second gate on the gate insulating layer; doping the active layer to form a source electrode and a drain electrode, wherein the source electrode and the drain electrode are both electrically connected to the active layer; and

[0039] An interlayer insulating layer is formed on the second gate.

[0040] An array substrate comprises any of the above-mentioned thin film transistors or a thin film transistor prepared by any of the above-mentioned preparation methods.

[0041] In the array substrate using the technical solution of the present invention, on the one hand, the carrier mobility of the second sub-active layer is greater than that of the first sub-active layer, which can improve the carrier mobility of the device; on the other hand, since the first sub-active layer and the second sub-active layer are alternately stacked and the band gap width of the first sub-active layer is greater than that of the second sub-active layer, the carriers can be subjected to conduction band shift during their movement, which greatly reduces the capture of carriers in the deep hydrazine state at the interface of the gate insulating layer, thereby improving the stability of the device.

[0042] A display panel comprises the above array substrate.

[0043] In the display panel using the technical solution of the present invention, on the one hand, the carrier mobility of the second sub-active layer is greater than that of the first sub-active layer, which can improve the carrier mobility of the device; on the other hand, since the first sub-active layer and the second sub-active layer are alternately stacked and the band gap width of the first sub-active layer is greater than that of the second sub-active layer, the carriers can undergo conduction band shifting during their movement, which greatly reduces the capture of carriers in the deep hydrazine state at the interface of the gate insulating layer, thereby improving the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a schematic diagram of a thin film transistor according to an embodiment of the present invention;

[0045] Figure 2 is a schematic diagram of an active layer according to an embodiment of the present invention;

[0046] Figure 3 It is a schematic diagram of the principle of the active layer of one embodiment of the present invention;

[0047] Figure 4 is a schematic diagram of an active layer according to another embodiment of the present invention;

[0048] Figure 5 is a schematic diagram of the principle of an active layer according to another embodiment of the present invention;

[0049] Figure 6 is a schematic diagram of an active layer according to another embodiment of the present invention;

[0050] Figure 7 is a schematic diagram of the principle of an active layer according to another embodiment of the present invention;

[0051] Figure 8 A flow chart of a method for preparing a thin film transistor according to an embodiment of the present invention;

[0052] Fig. 9 is a flow chart of a method for preparing a thin film transistor according to another embodiment of the present invention;

[0053] Fig.10 It is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of the present invention after forming a first gate on a substrate;

[0054] Fig.11 It is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of the present invention after a buffer layer is formed on a first gate electrode;

[0055] Fig.12 It is a schematic diagram of a method for preparing a thin film transistor according to an embodiment of the present invention after an active layer material is formed on a buffer layer;

[0056] Fig.13 It is a schematic diagram of a method for preparing a thin film transistor according to an embodiment of the present invention after an active layer is formed;

[0057] Fig.14 It is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of the present invention after a gate insulating layer and a second gate are formed on an active layer;

[0058] Fig.15 The schematic diagram is a method for manufacturing a thin film transistor according to an embodiment of the present invention after forming a source electrode and a drain electrode. DETAILED DESCRIPTION

[0059] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0060] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0062] See also Figure 1 to Figure 3 , a thin film transistor 100 according to an embodiment of the present invention includes a substrate 110 and an active layer 120 .

[0063] The active layer 120 is located on one side of the substrate 110 , and includes at least two first sub-active layers 121 and at least one second sub-active layer 122 , and the first sub-active layers 121 and the second sub-active layers 122 are alternately stacked.

[0064] The bandgap width of the first sub-active layer 121 is greater than the bandgap width of the second sub-active layer 122 , and the carrier mobility of the second sub-active layer 122 is greater than the carrier mobility of the first sub-active layer 121 .

[0065] In the thin film transistor 100 of the above embodiment, on the one hand, the carrier mobility of the second sub-active layer 122 is greater than the carrier mobility of the first sub-active layer 121, which can improve the carrier mobility of the device; on the other hand, since the first sub-active layer 121 and the second sub-active layer 122 are alternately stacked and the band gap width of the first sub-active layer 121 is greater than the band gap width of the second sub-active layer 122, the carriers can undergo conduction band shift during their movement, which greatly reduces the capture of carriers in the deep hydrazine state at the gate insulating layer interface, thereby improving the stability of the device.

[0066] Based on the above embodiments, the thin film transistor 100 further includes a first gate (Gate1) 130, a buffer layer (buffer) 140, a gate insulating layer (GI) 150, a second gate (Gate2) 160, an interlayer insulating layer (ILD) 170, a source (source) 180 and a drain (drain) 190.

[0067] The first gate 130 is located on a side of the substrate 110 close to the active layer 120. The first gate 130 can be made of a gate material commonly used in the art, such as Mo, Al, Cu, Ti, and the like.

[0068] The buffer layer 140 is located between the first gate 130 and the active layer 120. The buffer layer 140 can be made of a commonly used buffer material in the art, such as SiO2, SiN x 、SiON, etc.

[0069] The gate insulating layer 150 is located on the side of the active layer 120 away from the substrate 110. The gate insulating layer 150 can be made of a commonly used gate insulating material in the art, such as SiO2, SiN x , SiON, etc.

[0070] The second gate 160 is located on the side of the gate insulating layer 150 away from the substrate 110. The second gate 160 can be made of a gate material commonly used in the art, such as Mo, Al, Cu, Ti, etc. The thin film transistor 100 of the technical solution of the present invention introduces a double-gate structure on the basis of the active layer 120 being a stacked layer, which is conducive to forming a dual-carrier main channel when the device is working, wherein the bottom gate can also serve as a light shielding layer, further improving the stability of the device.

[0071] The interlayer insulating layer 170 is located on the side of the second gate 160 away from the substrate 110. The interlayer insulating layer 170 can be made of interlayer insulating materials commonly used in the art, such as SiN, HfO x 、TaO x wait.

[0072] The source electrode 180 is electrically connected to the active layer 120, and the drain electrode 190 is electrically connected to the active layer 120. The source electrode 180 and the drain electrode 190 are the inlet and outlet of the current, and the current magnitude of the channel between the source electrode 180 and the drain electrode 190 can be adjusted by controlling the gate voltage. The material of the source electrode 180 and the drain electrode 190 can be a stacked combination of one or more of molybdenum, titanium, aluminum and copper, and the source electrode 180 and the drain electrode 190 can also be formed by conductorization of a partial area of ​​the active layer 120.

[0073] In addition, the thin film transistor 100 further includes a first conductive layer 181 electrically connected to the source 180, a second conductive layer 191 electrically connected to the drain 190, a third conductive layer 131 electrically connected to the first gate 130, and a fourth conductive layer 161 electrically connected to the second gate 160. It should be noted that in the thin film transistor 100 of this embodiment, Figure 1 The thickness of the first gate 130 at one end close to the third conductive layer 131 is less than the thickness at one end away from the third conductive layer 131, but this does not mean that the end of the first gate 130 close to the third conductive layer 131 must be thinned. Figure 1 It is only used to indicate that the first gate 130 is electrically connected to the third conductive layer 131 . Of course, the first gate 130 and the third conductive layer 131 may also be connected by wires other than at the current cross-sectional position.

[0074] On the basis of the above-mentioned embodiment, the difference between the bandgap width of the first sub-active layer 121 and the bandgap width of the second sub-active layer 122 is greater than or equal to 1.0 eV. In this embodiment, the first sub-active layer 121 is made of a wide bandgap material, and the second sub-active layer 122 is made of a narrow bandgap material. This is conducive to causing the conduction band to shift during the movement of carriers, reducing the capture of carriers by the deep hydrazine state at the gate insulating layer interface, thereby improving the stability of the device.

[0075] Preferably, the difference between the bandgap width of the first sub-active layer 121 and the bandgap width of the second sub-active layer 122 is 1.5 eV to 2 eV. Further, the difference between the bandgap width of the first sub-active layer 121 and the bandgap width of the second sub-active layer 122 may be, but is not limited to, 1.5 eV, 1.6 eV, 1.7 eV, 1.8 eV, 1.9 eV or 2 eV.

[0076] Preferably, the bandgap of the first sub-active layer 121 is greater than or equal to 3.0 eV, and the bandgap of the second sub-active layer 122 is less than or equal to 2.5 eV. Preferably, the bandgap of the second sub-active layer 122 is 1.0 eV to 2.5 eV. Further, the bandgap of the second sub-active layer 122 may be, but is not limited to, 1.0 eV, 1.1 eV, 1.2 eV, 1.3 eV, 1.4 eV, 1.5 eV, 1.6 eV, 1.7 eV, 1.8 eV, 1.9 eV, 2.0 eV, 2.1 eV, 2.2 eV, 2.3 eV, 2.4 eV or 2.5 eV.

[0077] Based on the above embodiment, the carrier mobility of the second sub-active layer 122 is greater than or equal to twice the carrier mobility of the first sub-active layer 121. Preferably, the carrier mobility of the second sub-active layer 122 is greater than or equal to 20 cm 2 / V·s.

[0078] On the basis of the above-mentioned embodiment, the first sub-active layer 121 includes a metal oxide semiconductor material, and the material of the second sub-active layer 122 includes at least one of ZnON, TiO2, and MoS2. Preferably, the metal oxide semiconductor material is selected from at least one of IGZO, ZnO, SnO, TZO, ATZO, IZO, and lanthanide oxides. These types of first sub-active layer 121 materials are wide bandgap materials, and these types of second sub-active layer 122 materials are narrow bandgap high carrier mobility materials. The stacked arrangement of the first sub-active layer 121 and the second sub-active layer 122 using these materials can improve the mobility of carriers and improve the stability of the device.

[0079] On the basis of the above-mentioned embodiment, the sum of the number of layers of the first sub-active layer 121 and the second sub-active layer 122 is three to seven, and the number of layers of the first sub-active layer 121 is greater than or equal to the number of layers of the second sub-active layer 122. Specifically, in this embodiment, the number of layers of the active layer 120 is five, and specifically, the active layer 120 includes the first sub-active layer 121, the second sub-active layer 122, the first sub-active layer 121, the second sub-active layer 122 and the first sub-active layer 121 which are alternately stacked. This five-layer structure enables carriers to pass through two conduction band deviations during movement, greatly reducing the capture of carriers by the deep hydrazine state at the gate insulating layer interface, thereby improving the stability of the device.

[0080] It should be noted that in the thin film transistor of the present invention, the structure of the active layer is not limited thereto. The sum of the number of layers of the first sub-active layer 121 and the second sub-active layer 122 is three to seven, for example, three, four, five, six or seven. It is preferred that the number of layers of the first sub-active layer 121 is greater than or equal to the number of layers of the second sub-active layer 122. In order to form more carrier transmission channels, the carrier mobility and stability of the device are further improved.

[0081] See also Figure 4 and Figure 5 The active layer 220 of another embodiment of the present invention includes a first sub-active layer 221, a second sub-active layer 222 and a first sub-active layer 221 which are alternately stacked. In this way, a multi-carrier transmission channel can be formed through a three-layer structure, thereby improving the carrier mobility and stability of the device.

[0082] See also Figure 6 and Figure 7 The active layer 320 of another embodiment of the present invention includes a first sub-active layer 321, a second sub-active layer 322, a first sub-active layer 321, a second sub-active layer 322, a first sub-active layer 321, a second sub-active layer 322 and a first sub-active layer 321 which are alternately stacked. In this way, the formation of multiple carrier transmission channels can be realized through a multi-layer structure, thereby improving the carrier mobility and stability of the device.

[0083] In the thin film transistor using the technical solution of the present invention, on the one hand, the carrier mobility of the second sub-active layer is greater than that of the first sub-active layer, which can improve the carrier mobility of the device; on the other hand, since the first sub-active layer and the second sub-active layer are alternately stacked and the band gap width of the first sub-active layer is greater than that of the second sub-active layer, the carriers can be subjected to conduction band shifting during their movement, which greatly reduces the capture of carriers in the deep hydrazine state at the interface of the gate insulating layer, thereby improving the stability of the device.

[0084] See also Figure 8 A method for preparing a thin film transistor according to an embodiment of the present invention comprises the following steps:

[0085] S10. Provide a substrate.

[0086] S20. Form an active layer on the substrate of step S10, wherein the active layer includes at least two first sub-active layers and at least one second sub-active layer, and the first sub-active layers and the second sub-active layers are alternately stacked; the bandgap width of the first sub-active layer is greater than the bandgap width of the second sub-active layer, and the carrier mobility of the second sub-active layer is greater than the carrier mobility of the first sub-active layer.

[0087] The preparation method of the thin film transistor of this embodiment is simple in process. In the prepared thin film transistor, on the one hand, the carrier mobility of the second sub-active layer is greater than that of the first sub-active layer, which can improve the carrier mobility of the device; on the other hand, since the first sub-active layer and the second sub-active layer are alternately stacked and the band gap width of the first sub-active layer is greater than that of the second sub-active layer, the carriers can be subjected to conduction band shift during their movement, which greatly reduces the capture of carriers in the deep hydrazine state at the interface of the gate insulating layer, thereby improving the stability of the device.

[0088] Based on the above implementation, please refer to Figure 1 , Figures 9 to 15 A method for preparing a thin film transistor according to an embodiment of the present invention comprises the following steps:

[0089] S10. Provide a substrate.

[0090] The substrate 110 may be a commonly used substrate in the art, such as a glass substrate.

[0091] S20 , forming a first gate on the substrate of step S10 .

[0092] The first gate 130 can be formed on the substrate 110 by using common technical means in the art. For example, Mo with a thickness of 100 nm to 500 nm is deposited on the glass substrate 110 as the first gate material, and then patterned by yellow light etching and stripping process to obtain the first gate 130, such as Fig.10 Further, the thickness of Mo can be, but is not limited to, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.

[0093] S30 , forming a buffer layer on the first gate of step S20 .

[0094] The buffer layer 140 may be formed on the first gate 130 by using common technical means in the art. For example, after cleaning the substrate 110 with the first gate 130, 100nm to 300nm of SiO2 is deposited as the buffer layer 140, and serves as the gate dielectric layer of the bottom gate, such as Fig.11Further, the thickness of SiO2 can be, but is not limited to, 100nm, 200nm or 300nm.

[0095] S40 , forming an active layer on the buffer layer of step S30 .

[0096] The step of forming the active layer 120 on the buffer layer 140 is: forming the first active layer material and the second active layer material alternately arranged on the buffer layer 140 in sequence, and patterning the first active layer material and the second active layer material to obtain the active layer 120, such as Fig.12 and Fig.13 shown.

[0097] In one feasible implementation, the substrate 110 is treated with O3 water for 30s to 60s before depositing the active layer material, and the concentration of O3 water is 30ppm to 50ppm; then the substrate 110 is cleaned, and IGZO / ZnONIGZO / ZnON / IGZO are deposited in sequence as the active layer material of the device using a magnetron sputtering device, wherein the atomic ratio of the IGZO target material is In:Ga:Zn=1:1:1; ZnON is deposited using a Zn metal target material, and the mixed gas is Ar:O2:N2=3:1:40; the thickness of each IGZO layer is 5nm to 10nm, the thickness of each ZnON layer is 5nm to 10nm, and the total thickness is 25nm to 50nm, such as Fig.12 As shown; after the active layer material is deposited, it is annealed at high temperature in a vacuum environment, treated with O3 water for 30s to 60s, and the O3 water concentration is 30ppm to 50ppm; then patterned by yellow light, etching, and stripping processes to obtain an active layer 120, as shown Fig.13 Further, the time of O3 water treatment may be, but not limited to, 30s, 40s, 50s or 60s; the concentration of O3 water may be, but not limited to, 30ppm, 40ppm or 50ppm; the thickness of each IGZO layer may be, but not limited to, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, the thickness of each ZnON layer may be, but not limited to, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, and the total thickness may be, but not limited to, 25nm, 30nm, 35nm, 40nm, 45nm or 50nm.

[0098] In this embodiment, O3 water treatment is introduced before and after the active layer 120 is formed, and the interface between the active layer 120 and the gate insulating layer 150 is modified by two-step oxidation, which can reduce deep energy level trap states and improve device stability.

[0099] S50, forming a gate insulating layer on the active layer of step S40, and forming a second gate on the gate insulating layer; doping the active layer to form a source and a drain, and the source and the drain are electrically connected to the active layer.

[0100] The gate insulating layer 150 may be formed on the active layer 120 by using common technical means in the art. For example, the substrate 110 is cleaned, and then 100nm to 160nm SiO2 is deposited as the gate insulating layer 150 of the top gate. Fig.14 Further, the thickness of SiO2 can be, but is not limited to, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm or 160 nm.

[0101] The second gate 160 can be formed on the gate insulating layer 150 by using common technical means in the art. For example, the substrate 110 is cleaned, and then 100nm to 500nm of Mo is deposited as the second gate material using a magnetron sputtering device; and the second gate 160 is obtained by patterning through yellow light, etching, and stripping processes. Fig.14 Further, the thickness of Mo can be, but is not limited to, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.

[0102] The active layer 120 may be doped using common technical means in the art to form a source 180 and a drain 190. For example, an ion implantation process may be used to dope both ends of the active layer 120 to form a source 180 and a drain 190. Fig.15 shown.

[0103] In addition, it should be noted that in step S50, the active layer may be doped first to form a source and a drain, both of which are electrically connected to the active layer; then a gate insulating layer is formed on the active layer, and a second gate is formed on the gate insulating layer.

[0104] S60 , forming an interlayer insulating layer on the second gate of step S50 .

[0105] The interlayer insulating layer 170 may be formed on the second gate 160 by using common technical means in the art. For example, the substrate 110 is cleaned, and then 250nm to 500nm of SiO2 and 250nm to 500nm of SiN are deposited as the interlayer insulating layer 170; holes are then punched by yellow light, etching, and stripping processes, and 100 to 500nm of Mo is deposited by magnetron sputtering, and the Mo layer is patterned by yellow light, etching, and stripping processes to form a first conductive layer 181 electrically connected to the source 180, a second conductive layer 191 electrically connected to the drain 190, a third conductive layer 131 electrically connected to the first gate 130, and a fourth conductive layer 161 electrically connected to the second gate 160, as shown in FIG. Figure 1The thickness of SiO2 may be, but is not limited to, 250nm, 300nm, 350nm, 400nm, 450nm, or 500nm, the thickness of SiN may be, but is not limited to, 250nm, 300nm, 350nm, 400nm, 450nm, or 500nm, and the thickness of Mo may be, but is not limited to, 100nm, 200nm, 300nm, 400nm, or 500nm.

[0106] The method for preparing the thin film transistor of the technical solution of the present invention has a simple process. In the prepared thin film transistor, on the one hand, the carrier mobility of the second sub-active layer is greater than that of the first sub-active layer, which can improve the carrier mobility of the device; on the other hand, since the first sub-active layer and the second sub-active layer are alternately stacked and the band gap width of the first sub-active layer is greater than that of the second sub-active layer, the carriers can be subjected to conduction band deviation during the movement process, which greatly reduces the carriers being captured in the deep hydrazine state at the interface of the gate insulating layer, thereby improving the stability of the device.

[0107] An array substrate according to one embodiment includes any of the above-mentioned thin film transistors or a thin film transistor prepared by any of the above-mentioned preparation methods.

[0108] In the array substrate using the technical solution of the present invention, on the one hand, the carrier mobility of the second sub-active layer is greater than that of the first sub-active layer, which can improve the carrier mobility of the device; on the other hand, since the first sub-active layer and the second sub-active layer are alternately stacked and the band gap width of the first sub-active layer is greater than that of the second sub-active layer, the carriers can be subjected to conduction band shift during their movement, which greatly reduces the capture of carriers in the deep hydrazine state at the interface of the gate insulating layer, thereby improving the stability of the device.

[0109] A display panel according to one embodiment includes the above array substrate.

[0110] In the display panel using the technical solution of the present invention, on the one hand, the carrier mobility of the second sub-active layer is greater than that of the first sub-active layer, which can improve the carrier mobility of the device; on the other hand, since the first sub-active layer and the second sub-active layer are alternately stacked and the band gap width of the first sub-active layer is greater than that of the second sub-active layer, the carriers can undergo conduction band shifting during their movement, which greatly reduces the capture of carriers in the deep hydrazine state at the interface of the gate insulating layer, thereby improving the stability of the device.

[0111] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A thin film transistor, characterized in that: The thin film transistor comprises: substrate; and An active layer, located on one side of the substrate, the active layer comprising at least two first sub-active layers and at least one second sub-active layer, and the first sub-active layers and the second sub-active layers are alternately stacked; The bandgap width of the first sub-active layer is greater than the bandgap width of the second sub-active layer, and the carrier mobility of the second sub-active layer is greater than the carrier mobility of the first sub-active layer.

2. The thin film transistor according to claim 1, characterized in that: A difference between a bandgap width of the first sub-active layer and a bandgap width of the second sub-active layer is greater than or equal to 1.0 eV; Preferably, the difference between the bandgap width of the first sub-active layer and the bandgap width of the second sub-active layer is 1.5 eV to 2 eV; Preferably, the bandgap width of the first sub-active layer is greater than or equal to 3.0 eV, and the bandgap width of the second sub-active layer is less than or equal to 2.5 eV; Preferably, the bandgap width of the second sub-active layer is 1.0 eV to 2.5 eV.

3. The thin film transistor according to claim 1, characterized in that: The carrier mobility of the second sub-active layer is greater than or equal to twice the carrier mobility of the first sub-active layer; Preferably, the carrier mobility of the second sub-active layer is greater than or equal to 20 cm 2 / V·s.

4. The thin film transistor according to claim 1, characterized in that: The first sub-active layer includes a metal oxide semiconductor material, and the material of the second sub-active layer includes at least one of ZnON, TiO2 and MoS2; Preferably, the metal oxide semiconductor material is selected from at least one of ZnO, SnO, TZO, ATZO, IGZO, IZO and lanthanide oxides.

5. The thin film transistor according to claim 1, characterized in that: The sum of the number of layers of the first sub-active layer and the second sub-active layer is three to seven, and the number of layers of the first sub-active layer is greater than or equal to the number of layers of the second sub-active layer; Preferably, the active layer comprises a first sub-active layer, a second sub-active layer and a first sub-active layer which are alternately stacked; Preferably, the active layer comprises a first sub-active layer, a second sub-active layer, a first sub-active layer, a second sub-active layer and a first sub-active layer which are alternately stacked; Preferably, the active layer includes a first sub-active layer, a second sub-active layer, a first sub-active layer, a second sub-active layer, a first sub-active layer, a second sub-active layer and a first sub-active layer which are alternately stacked.

6. The thin film transistor according to claim 1, characterized in that: The thin film transistor further comprises: A first gate, located on a side of the substrate close to the active layer; A buffer layer, located between the first gate and the active layer; A gate insulating layer, located on a side of the active layer away from the substrate; A second gate is located at a side of the gate insulating layer away from the substrate; an interlayer insulating layer, located on a side of the second gate away from the substrate; a source electrode electrically connected to the active layer; and The drain electrode is electrically connected to the active layer.

7. A method for preparing a thin film transistor, characterized in that: The steps include: providing a substrate; as well as An active layer is formed on the substrate, wherein the active layer includes at least two first sub-active layers and at least one second sub-active layer, and the first sub-active layers and the second sub-active layers are alternately stacked; the bandgap width of the first sub-active layer is greater than the bandgap width of the second sub-active layer, and the carrier mobility of the second sub-active layer is greater than the carrier mobility of the first sub-active layer.

8. The method for preparing a thin film transistor according to claim 7, characterized in that: The steps include: providing a substrate; forming a first gate on the substrate; forming a buffer layer on the first gate; forming an active layer on the buffer layer; forming a gate insulating layer on the active layer, and forming a second gate on the gate insulating layer; doping the active layer to form a source electrode and a drain electrode, wherein the source electrode and the drain electrode are both electrically connected to the active layer; and An interlayer insulating layer is formed on the second gate.

9. An array substrate, characterized in that: A thin film transistor comprising any one of claims 1 to 6 or a thin film transistor prepared by the preparation method according to any one of claims 7 to 8.

10. A display panel, characterized in that: Comprising the array substrate as claimed in claim 9.

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