Junction-free fin type field effect transistor and manufacturing method thereof
By designing the crystal pipeless of the finite field field, the doped ions of the polygonal fin structure and the same form are used to solve the problem of the traditional MOS semiconductor element in small size and low voltage saturation current. Effect.
Patent Information
- Application Number
- CN202411544982.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-01-28
AI Technical Summary
As the gate channel size decreases, the saturation current cannot reach the expected value when the applied voltage of the conventional MOS semiconductor components decreases, and the space used decreases rapidly.
Design a kind of -free fins effect, the top of the fin is polygon, the octagonal structure is left and right symmetrical funnel -shaped. Effective use of external plus operation voltage.
In the case of lowering the voltage, it can reach the required saturation current and suitable for making smaller and density semiconductor elements.
Smart Images
Figure CN119384014A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a junctionless fin field effect transistor and a manufacturing method thereof. Background Art
[0002] In traditional metal oxide semiconductor, i.e. MOS semiconductor components, basically N-type MOS, i.e. NMOS, is placed in P well, and P-type, i.e. PMOS, is placed in N well. The source / drain and gate channel layers use different types of conductive particles. Due to the reverse PN junction between the source / drain and the gate channel layer, in the state without external longitudinal voltage, the source / drain does not conduct current under the action of the external transverse voltage. Under the influence of the longitudinal external voltage, the gate channel layer is converted into the characteristics of reverse conductive ions to form a current channel. Due to the characteristics of the PN junction, an ion depletion region is formed in the interface layer of the reverse conductive ions, and the ion depletion region affects the number of reverse ions generated by the external longitudinal voltage. The above-mentioned MOS semiconductor component structure has become the mainstream driving force for the development of semiconductor technology. MOS semiconductor technology is developing in the direction of smaller and smaller gate channel size and lower and lower external voltage. The traditional MOS semiconductor structure uses a thinner and higher dielectric dielectric layer to enhance the effect of the longitudinal electric field. Due to engineering design considerations and semiconductor process trends, more complex three-dimensional spatial structures are usually used to control the on or off current, and the saturation current and leakage current are controlled by increasing the doping ion concentration of the gate channel layer.
[0003] That is, in the prior art, as the gate channel size becomes smaller and smaller, the required doping source / drain depth becomes shallower and shallower, and the space available to control the reverse PN junction ion depletion region becomes less and less. For traditional MOS semiconductor elements with three-sided ion depletion regions, the available space decreases rapidly. When the external voltage is reduced, the saturation current will not be able to reach the expected value.
[0004] Therefore, the prior art has defects and needs to be improved and developed. Summary of the invention
[0005] The embodiment of the present invention provides a junctionless fin field effect transistor and a method for manufacturing the same, which is used to solve the problem in the prior art that as the gate channel size becomes smaller and smaller, the required doping source / drain depth becomes shallower and shallower, the space available for controlling the reverse PN junction ion depletion region becomes less and less, the available space of the traditional MOS semiconductor element with a three-sided ion depletion region decreases rapidly, and when the external voltage is reduced, the saturation current will not be able to reach the expected value.
[0006] According to a first aspect of an embodiment of the present invention, a junctionless fin field effect transistor is provided, comprising a substrate, the substrate being covered with an oxide layer; a fin being formed on the substrate, the interface of the top of the fin in a direction perpendicular to the extension direction of the fin being a polygon, the polygon being an octagon and being bilaterally symmetrical in a funnel shape, the top of the octagon being defined as a first side, the second side of the octagon being perpendicular to the oxide layer in a clockwise direction, the angle between the third side of the octagon and the oxide layer being an acute angle, the fourth side of the octagon being perpendicular to the substrate and the highest point of the fourth side being flush with the upper surface of the oxide layer, the fifth side of the octagon being closely attached to the substrate; the distance between the first side and the fifth side being less than the sum of the lengths of the second side, the third side and the fourth side; a gate across the fin being fixed on the oxide layer, the gate being used to fit the lower surface of the fin to adapt to the outer contour of the fin; the bottom of the gate is also covered with a dielectric layer; when the gate crosses the gate, the gate is separated into a source and a drain.
[0007] Further, the first side of the octagon is defined as W, the height of the octagon above the oxide layer is defined as H, H:W=A, wherein W and H are positive numbers, and the value range of A is [1, 100].
[0008] Furthermore, the angle between the second side of the octagon and the third side of the octagon is defined as θ, and the value range of θ is [120, 150].
[0009] Furthermore, the acute angle between the third side of the octagon and the oxide layer is defined as β, and the value range of β is [30, 60].
[0010] Furthermore, the substrate is one of a silicon substrate, a silicon-on-insulator substrate, and a silicon element mixture substrate.
[0011] According to a second aspect of an embodiment of the present invention, a method for manufacturing a junctionless fin field effect transistor is provided, comprising:
[0012] Providing a substrate; forming an oxide layer with a channel on the upper surface of the substrate; patterning the substrate and forming a fin on the channel; forming a gate across the fin on the oxide layer, defining the gate across the fin and located at the top of the fin as a gate channel layer; covering the lower surface of the gate with a dielectric layer; doping the fin with charged ions so that the fin spanned by the gate forms a source and a drain; doping the gate channel layer with charged ions of the same form as the source and the drain, wherein the concentration of the charged ions doped in the gate channel layer is lower than the concentration of the charged ions doped in the source and the drain.
[0013] Furthermore, when the junctionless fin field effect transistor is an NMOS tube, the gate channel layer, the source and the drain contain pentavalent ion dopants, and the pentavalent ion dopants are at least one of phosphorus ions, arsenic ions, antimony ions, bismuth ions, and nitrogen ions; the dielectric layer is a metal silicide dielectric layer, and the metal component in the metal silicide dielectric layer is at least one of cobalt, nickel, molybdenum, titanium, tungsten, copper, and niobium.
[0014] Furthermore, when the junctionless fin field effect transistor is a PMOS tube, the gate channel layer, the source and the drain contain trivalent ion dopants, and the trivalent ion dopants are at least one of boron ions, boron fluoride ions, gallium ions, indium ions, thallium ions, and aluminum ions; the dielectric layer is a metal silicide dielectric layer, and the metal component in the metal silicide dielectric layer is at least one of cobalt, nickel, molybdenum, titanium, tungsten, copper, and niobium.
[0015] Furthermore, the concentration of pentavalent ion dopants in the gate channel layer is between 2E15 / cm 3 ~3E18 / cm 3 The concentration of pentavalent ion dopants in the source and drain is between 2E20 / cm 3 ~3E22 / cm 3 .
[0016] Furthermore, the gate channel layer is doped with n-type dopants, and the concentration of the n-type dopants is between 3E12 / cm 3 ~2E16 / cm 3 , wherein the n-type dopant includes at least one of phosphorus, arsenic, nitrogen, antimony, and bismuth; the gate channel layer is doped with a p-type dopant, and the concentration of the p-type dopant is between 3E12 / cm 3 ~2E16 / cm 3 , wherein the p-type dopant includes at least one or more of the group consisting of boron, boron fluoride, gallium, indium, thallium and aluminum.
[0017] Beneficial effects:
[0018] It can be seen from the above technical scheme that the present invention provides a junctionless fin field effect transistor and a method for manufacturing the same. In the structure, the gate channel layer is doped with charged ions of the same form as the source and drain. The isolation between the gate channel layer and the source and drain on both sides does not need to rely on the PN junction, and the electric field effect of the applied operating voltage can be more effectively utilized, and a wider range of doping ion concentrations and dielectric layer thicknesses can be used; while reducing the voltage, the required saturation current can be achieved, so it is suitable for making smaller and higher density semiconductor components.
[0019] It should be appreciated that all combinations of the foregoing concepts, as well as additional concepts described in greater detail below, may be considered to be part of the inventive subject matter of the present disclosure, provided such concepts are not mutually inconsistent.
[0020] The foregoing and other aspects, embodiments and features of the present invention can be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the present invention, such as the features and / or beneficial effects of the exemplary embodiments, will be apparent from the following description or learned from the practice of the specific embodiments according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The accompanying drawings are not intended to be drawn to scale. In the accompanying drawings, each identical or nearly identical component shown in various figures may be represented by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the present invention will now be described by way of example and with reference to the accompanying drawings, in which:
[0022] Figure 1 Schematic diagram of the structure of a junctionless fin field effect transistor in an embodiment of the present application.
[0023] Figure 2 It is a cross-sectional view of the structure of a junctionless fin field effect transistor in an embodiment of the present application.
[0024] Figure 3 It is a structural cross-sectional view of a fin field effect transistor in the prior art.
[0025] Figure 4 Schematic diagram of a gate channel layer of a junctionless fin field effect transistor in an embodiment of the present application.
[0026] Figure 5 This is a schematic diagram of a switching effect achieved when a junctionless fin field effect transistor is an NMOS tube in an embodiment of the present application.
[0027] Figure 6 This is a schematic diagram of a switching effect achieved when a junctionless fin field effect transistor is a PMOS tube in an embodiment of the present application.
[0028] Description of Figure Numbers:
[0029] Substrate 1; source 2; drain 3; oxide layer 4; dielectric layer 5; gate 6; gate channel layer 7. DETAILED DESCRIPTION
[0030] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meaning understood by people with general skills in the field to which the present invention belongs.
[0031] The words "first", "second" and similar terms used in the patent specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, unless the context clearly indicates otherwise, the singular form "a" or "an" shall not be construed as "a" or "an";
[0032] The words “-” or “the” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.
[0033] The words "include" or "comprises" and the like mean that the elements or objects appearing before "includes" or "comprises" include the features, wholes, steps, operations, elements and / or components listed after "includes" or "comprises", and do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0034] In the prior art, as the gate channel size becomes smaller and smaller, the required doping source / drain depth becomes shallower and shallower, and the space available to control the reverse PN junction ion depletion region becomes less and less. The available space of the traditional MOS semiconductor element with three-sided ion depletion region decreases rapidly. When the external voltage is reduced, the saturation current will not be able to reach the expected value.
[0035] In view of this, an embodiment of the present invention provides a junctionless fin field effect transistor, referring to Figure 1-2, including a substrate 1, on which an oxide layer 4 is covered; a fin is formed on the substrate 1. The interface of the top of the fin in the direction perpendicular to the extension of the fin is a polygon, and the sum of the lengths of the sides of any side of the polygon is greater than the height of the polygon; the polygon is an octagon and is a bilaterally symmetrical funnel shape, and the top of the octagon is defined as the first side, and the second side of the octagon is perpendicular to the oxide layer 4 in a clockwise direction, and the angle between the third side of the octagon and the oxide layer 4 is an acute angle, the fourth side of the octagon is perpendicular to the substrate 1 and the highest point of the fourth side is flush with the upper surface of the oxide layer 4, and the fifth side of the octagon is close to the substrate 1. A gate 6 that spans the fin is fixed on the oxide layer 4, and the gate 6 is used to fit the lower surface of the fin to adapt to the outer contour of the fin; when the gate 6 spans the gate 6, the gate 6 is separated into a source 2 and a drain 3.
[0036] By designing the top of the fin to be a polygon, and the sum of the side lengths is greater than the height, the conductive area can be effectively increased and the resistance can be reduced. The octagonal funnel-shaped structure makes the electric field more concentrated at the top of the fin, thereby improving the mobility of the carriers and speeding up the turn-on and turn-off speeds. In addition, the left-right symmetrical design contributes to the overall stability of the device and further improves the reliability of the device. In some other embodiments, the oxide layer 4 is a silicon dioxide layer, or it can be a high dielectric constant material, such as titanium oxide, zirconium oxide, etc., to increase the capacitance of the gate 6 while reducing the gate leakage current.
[0037] Reference Figure 2 , the arrows in the figure indicate the direction of the electric field, refer to Figure 3 , the arrow in the figure indicates the direction of the electric field. Compared with the fin structure in the prior art, the octagonal structure makes the electric field to which the P-type or N-type minority carriers of the transistor are subjected to become larger after the gate 6 voltage is applied, and the speed at which the carriers drift toward the source 2 or the drain 3 and the substrate 1 is faster, thereby accelerating the speed at which the transistor is turned on or off.
[0038] In some embodiments, the first side of the octagon is defined as W, the height of the octagon above the oxide layer 4 is H, H:W=A, where W and H are positive numbers, and the value range of A is [1, 100]. A small H value results in a large resistance. If W is too large, it is easy to merge with adjacent fins and short-circuit. If W is too small, the contact window between the fin and the gate 6 becomes narrower, which will destroy the circuit effect. If A is too large, the epitaxial height in the transistor will become shorter and affect the resistance value. If A is too small, the epitaxial volume in the transistor will become smaller and reduce the tension of the device. Both of these situations will affect the mobility of the device. Therefore, the value of A is set to [1, 100] to balance the resistance value and device tension, thereby improving the quality of the transistor and improving the mobility and reliability of the device.
[0039] In some embodiments, the angle between the second side of the octagon and the third side of the octagon is defined as θ, and the value range of e is [120, 150]. The optimized range of the angle θ can adjust the electric field distribution between the fin and the substrate 1, ensure the electric field concentration, reduce the leakage current, and improve the switching speed.
[0040] In some embodiments, the acute angle between the third side of the octagon and the oxide layer 4 is defined as β, and the value range of β is [30, 60]. The value range of the angle β optimizes the connection between the fin and the oxide layer 4, further concentrates the electric field, improves the carrier migration path, and thus improves the switching efficiency.
[0041] In some embodiments, the substrate 1 is one of a silicon substrate 1, a silicon-on-insulator substrate 1, and a silicon element mixture substrate 1. The selection of the substrate 1 material enables the device to operate stably in harsh environments such as high temperature and high pressure, while optimizing the electric field coupling between the fin and the substrate 1 and improving the overall performance.
[0042] In some other embodiments, the bottom of the gate 6 is also covered with a dielectric layer 5, the thickness range of the dielectric layer 5 is [15, 120], and the thickness unit of the dielectric layer 5 is angstrom. The thickness optimization of the dielectric layer 5 effectively protects the gate 6 while ensuring the concentration of the electric field and improving the response speed of the transistor. The fine control of the thickness at the angstrom level helps to reduce leakage and improve the switching efficiency of the device. The dielectric layer 5 includes an aluminum oxide dielectric layer, a hafnium oxide dielectric layer, a hafnium silicon oxide dielectric layer, a hafnium silicon nitride dielectric layer, a hafnium titanium oxide dielectric layer, a hafnium zirconium oxide dielectric layer, etc. In some other embodiments, the length of the gate channel layer is between 1nm and 1.8μm.
[0043] According to a second aspect of an embodiment of the present invention, a method for manufacturing a junctionless fin field effect transistor is provided, comprising:
[0044] Step 1: providing a substrate 1;
[0045] Step 2: forming an oxide layer 4 with a channel on the upper surface of the substrate 1;
[0046] Step 3: patterning the substrate 1 and forming fins on the channels;
[0047] Step 4: forming a gate 6 across the fin on the oxide layer 4, and defining the gate 6 across the fin and located at the top of the fin as a gate channel layer 7;
[0048] Step 5: Covering the lower surface of the gate 6 with a dielectric layer 5;
[0049] Step 6: doping the fin with charged ions so that the fin crossed by the gate 6 forms a source 2 and a drain 3;
[0050] Step seven: doping the gate channel layer 7 with charged ions of the same form as the source 2 and the drain 3 , wherein the concentration of the charged ions doped in the gate channel layer 7 is lower than the concentration of the charged ions doped in the source 2 and the drain 3 .
[0051] Reference Figure 4 , Figure 4 The middle cyan part is the gate channel layer 7. The reason for the existence of the gate channel layer 7 is the skin effect, which means that when the alternating current passes through the conductor, the current is mainly concentrated on the surface of the fin, rather than being evenly distributed over the entire cross section. This phenomenon is caused by the electromagnetic field generated by the alternating current inside the conductor. Usually, the current density is higher on the surface of the fin and lower in the center. The skin effect reduces the effective cross-sectional area of the fin, thereby affecting its resistance and current conduction performance. Therefore, ion doping is required in the gate channel layer 7. The source 2, drain 3 and gate channel layer 7 of the semiconductor element are doped with the same type of ions. By controlling the ion doping concentration of the gate channel layer 7 and the source 2 and drain 3, the ion doping concentration of the source 2 and drain 3 is greater than the ion doping concentration of the gate channel layer 7, and a potential barrier is generated between the gate 6 and the source 2 and drain 3, so that the charged particles in the gate channel layer 7 are bound to a non-conductive state. Under the influence of the external electric field, they are converted into a free moving state, producing a switching effect.
[0052] The region where the source 2 and drain 3 are doped with ions is a doping region, and the ion doping concentration of the doping region is always greater than the ion doping concentration of the gate channel layer 7, thereby generating a potential barrier between the gate channel layer 7 and the source 2 and drain 3, forming isolation between the source 2 and the drain 3 via the gate 6. In addition, since the gate channel layer 7 and the source 2 and drain 3 doping regions have the same doping ions, there is no PN junction in the semiconductor element. The conventional gate channel layer 7 containing a PN junction generates a potential barrier of 0.7V between the source 2 and drain 3, while the potential barrier generated between the gate channel layer 7 and the source 2 and drain 3 of the present invention is about 0.5V, and the external operating voltage of the semiconductor element can be reduced to 0.2V to 0.45V, which is very helpful for power saving of the GPU currently used for A1 calculations.
[0053] In some embodiments, when the junctionless fin field effect transistor is an NMOS tube, the gate channel layer 7, the source 2 and the drain 3 contain pentavalent ion dopants, and the pentavalent ion dopants are at least one of phosphorus ions, arsenic ions, antimony ions, bismuth ions, and nitrogen ions; the dielectric layer 5 is a metal silicide dielectric layer 5, and the metal component in the metal silicide dielectric layer 5 is at least one of cobalt, nickel, molybdenum, titanium, tungsten, copper, and niobium.
[0054] When the junctionless fin field effect transistor is an NMOS tube, and the gate channel layer 7, the source 2 and the drain 3 contain pentavalent ion dopants, the semiconductor has different changes under the action of voltage, referring to Figure 5, indicating the electromotive force conduction mode of the electric field, ①~④ in the figure are schematic diagrams of energy level barriers under different voltage application states, in which the gate 6 represents the gate channel layer 7, and the dotted line without arrows represents the barrier. Figure 5 In ①, in the thermal equilibrium state without external voltage, a potential barrier is formed between the gate channel layer 7 and the source 2 and drain 3 doping regions. The potential difference of the barrier is less than 0.5V. Under this condition, electrons are bound to a high potential and cannot flow from the source 2 to the drain 3. Figure 5 In ②, when an external positive voltage is applied to the drain 3, the conductive energy band of the drain 3 changes position, as indicated by the dotted line with an arrow, and the conductive bands of the gate channel layer 7 and the source 2 do not change, and the semiconductor element is in a non-conductive state. Figure 5 In ③, when a voltage is applied to the gate, if the applied voltage is a negative voltage, the electrons are repelled away from the gate channel layer 7, and the energy band difference between the gate channel layer 7 and the source 2 and drain 3 conductive regions increases along the direction indicated by the arrow, and the semiconductor element is still in a non-conductive state. Figure 5 In ④, if the applied voltage is a positive voltage, electrons are attracted to the gate channel layer 7, and the energy band of the conductive region corresponding to the gate channel layer 7 changes in the direction indicated by the arrow, so that the potential barrier is lowered. When the voltage reaches the threshold voltage, the semiconductor element is in a conductive state, and electrons flow from the source 2 to the drain 3, and the current direction flows from the drain 3 to the source 2.
[0055] In some embodiments, when the junctionless fin field effect transistor is a PMOS tube, the gate channel layer 7, the source 2 and the drain 3 contain trivalent ion dopants, and the trivalent ion dopants are at least one of boron ions, boron fluoride ions, gallium ions, indium ions, thallium ions, and aluminum ions; the dielectric layer 5 is a metal silicide dielectric layer 5, and the metal component in the metal silicide dielectric layer 5 is at least one of cobalt, nickel, molybdenum, titanium, tungsten, copper, and niobium.
[0056] When the junctionless fin field effect transistor is a PMOS tube, the gate channel layer 7, the source 2 and the drain 3 contain trivalent ion dopants, and the doping concentration of the source 2 and the drain 3 doping regions is much greater than the doping concentration of the gate channel layer 7, refer to Figure 6 , indicating the electromotive force conduction mode of the electric field, ①~④ in the figure are schematic diagrams of energy level barriers under different voltage application states, in which the gate 6 represents the gate channel layer 7, and the dotted line without arrows represents the barrier. Figure 6 In ①, in the thermal equilibrium state without external voltage, a potential barrier is formed between the gate channel layer 7 and the source 2 and drain 3 doping regions, and the potential difference of the barrier is less than 0.5V. Under this condition, holes are bound at a low potential and cannot flow from the source 2 to the drain 3. Figure 6In ②, when a positive voltage is applied to the source 2, the valence energy band of the source 2 is displaced as shown by the arrow in the figure, and the valence energy band of the gate channel layer 7 and the valence energy band of the drain 3 remain unchanged, and the semiconductor element remains in a non-conductive state. Figure 6 In ③, when a voltage is applied to the gate, if the applied voltage is a positive voltage, holes are repelled away from the gate channel layer 7, and the valence band of the gate channel layer 7 increases along the arrow direction, and the valence band difference between the gate channel layer 7 and the source 2 and drain 3 increases, and the semiconductor element is in a non-conductive state. Figure 6 In ④, if the applied voltage is negative, the holes are attracted to the gate channel layer 7, and the energy band of the valence region of the gate channel layer 7 changes in the direction indicated by the arrow, and the potential barrier is lowered. When the voltage reaches the threshold voltage, the semiconductor element is in a conductive state, and the holes flow from the source 2 to the drain 3, and the current direction also flows from the source 2 to the drain 3.
[0057] In some embodiments, the concentration of pentavalent ion dopants in the gate channel layer 7 is between 2E15 / cm 3 ~3E18 / cm 3 ; The concentration of pentavalent ion dopants in the source 2 and drain 3 is between 2E20 / cm 3 ~3E22 / cm 3 .
[0058] In some embodiments, the gate channel layer 7 is doped with n-type dopants, and the concentration of the n-type dopants is between 3E12 / cm 3 ~2E16 / cm 3 , wherein the n-type dopant includes at least one of phosphorus, arsenic, nitrogen, antimony, and bismuth; the gate channel layer 7 is doped with a p-type dopant, and the concentration of the p-type dopant is between 3E12 / cm 3 ~2E16 / cm 3 , wherein the p-type dopant includes holes, and the p-type dopant also includes at least one or more of the group consisting of boron, boron fluoride, gallium, indium, thallium and aluminum.
[0059] In summary, the present invention provides a junctionless fin field effect transistor and a manufacturing method thereof. By doping the gate channel layer 7 with charged ions of the same form as the source 2 and the drain 3, the isolation between the gate channel layer 7 and the source 2 and the drain 3 on both sides does not need to rely on the PN junction, and can more effectively utilize the electric field effect of the applied operating voltage and use a wider range of doping ion concentrations and dielectric layer thicknesses. While reducing the voltage, the required saturation current can be achieved, and therefore it is suitable for making smaller and higher density semiconductor components.
[0060] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.
Claims
1. A junctionless fin field effect transistor, comprising a substrate, characterized in that: The substrate is covered with an oxide layer; a fin is formed on the substrate, and the interface of the top of the fin in the direction perpendicular to the extension of the fin is a polygon, the polygon is an octagon and is a bilaterally symmetrical funnel, the top of the octagon is defined as the first side, the second side of the octagon is perpendicular to the oxide layer in a clockwise direction, the angle between the third side of the octagon and the oxide layer is an acute angle, the fourth side of the octagon is perpendicular to the substrate and the highest point of the fourth side is flush with the upper surface of the oxide layer, and the fifth side of the octagon is close to the substrate; the distance between the first side and the fifth side is less than the sum of the lengths of the second side, the third side and the fourth side; a gate across the fin is fixed on the oxide layer, and the gate is used to fit the lower surface of the fin to adapt to the outer contour of the fin; the bottom of the gate is also covered with a dielectric layer; when the gate crosses the gate, the gate is separated into a source and a drain.
2. The junctionless fin field effect transistor according to claim 1, characterized in that: Define the first side of the octagon to be W, the height of the octagon above the oxide layer to be H, H:W=A, wherein W and H are positive numbers, and the value range of A is [1, 100].
3. The junctionless fin field effect transistor according to claim 2, characterized in that: Define the included angle between the second side of the octagon and the third side of the octagon as θ, where the value range of θ is [120, 150].
4. The junctionless fin field effect transistor according to claim 3, characterized in that: The acute angle between the third side of the octagon and the oxide layer is defined as β, and the value range of β is [30, 60].
5. The junctionless fin field effect transistor according to claim 4, characterized in that: The substrate is one of a silicon substrate, a silicon-on-insulator substrate, and a silicon element mixture substrate.
6. A method for manufacturing a junctionless fin field effect transistor, characterized in that: include: providing a substrate; forming an oxide layer with a channel on the upper surface of the substrate; patterning the substrate and forming fins on the channels; Forming a gate across the fin on the oxide layer, defining the gate across the fin and located at the uppermost layer of the fin as a gate channel layer; Covering the lower surface of the gate with a dielectric layer; Doping the fin with charged ions so that the fin spanned by the gate forms a source and a drain; The gate channel layer is doped with charged ions of the same form as those of the source and the drain, wherein the concentration of the charged ions doped in the gate channel layer is lower than the concentration of the charged ions doped in the source and the drain.
7. The method for manufacturing a junctionless fin field effect transistor according to claim 6, characterized in that: When the junctionless fin field effect transistor is an NMOS tube, the gate channel layer, the source and the drain contain pentavalent ion dopants, and the pentavalent ion dopants are at least one of phosphorus ions, arsenic ions, antimony ions, bismuth ions, and nitrogen ions; the dielectric layer is a metal silicide dielectric layer, and the metal component in the metal silicide dielectric layer is at least one of cobalt, nickel, molybdenum, titanium, tungsten, copper, and niobium.
8. The method for manufacturing a junctionless fin field effect transistor according to claim 6, characterized in that: When the junctionless fin field effect transistor is a PMOS tube, the gate channel layer, the source and the drain contain trivalent ion dopants, and the trivalent ion dopants are at least one of boron ions, boron fluoride ions, gallium ions, indium ions, thallium ions, and aluminum ions; the dielectric layer is a metal silicide dielectric layer, and the metal component in the metal silicide dielectric layer is at least one of cobalt, nickel, molybdenum, titanium, tungsten, copper, and niobium.
9. The method for manufacturing a junctionless fin field effect transistor according to claim 7 or 8, characterized in that: The concentration of the pentavalent ion dopant in the gate channel layer is between 2E15 / cm 3 ~3E18 / cm 3 The concentration of pentavalent ion dopants in the source and drain is between 2E20 / cm 3 ~3E22 / cm 3 .
10. The method for manufacturing a junctionless fin field effect transistor according to claim 7 or 8, characterized in that: The gate channel layer is doped with n-type dopants, the concentration of which is between 3E12 / cm 3 ~2E16 / cm 3 , wherein the n-type dopant includes at least one of phosphorus, arsenic, nitrogen, antimony, and bismuth; the gate channel layer is doped with a p-type dopant, and the concentration of the p-type dopant is between 3E12 / cm 3 ~2E16 / cm 3 , wherein the p-type dopant includes at least one or more of the group consisting of boron, boron fluoride, gallium, indium, thallium and aluminum.