Electronic device

Abstract

The present invention provides an electronic device having more excellent operational reliability. An electronic device according to an embodiment of the present invention includes a first device board, a second device board, and a hollow portion. The second device board is stacked on and electrically connected to the first device board, and an area of the second device board is larger than an area of the first device board. The hollow portion surrounds at least a portion of a periphery of the first device board along a plane orthogonal to a stacking direction of the first device board and the second device board.

Description

Technical Field

[0001] The present invention relates to an electronic device having a stacked structure in which more than two boards are stacked on each other. Background Art

[0002] In order to achieve size reduction of imaging devices, a wafer-on-wafer (WoW) stacking technology has been proposed, which combines a wafer including an imaging element that generates a pixel signal with a wafer including a signal processing circuit that performs signal processing on the pixel signal generated by the imaging element, a memory circuit, etc. (for example, patent document 1).

[0003] Citation List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2014-099582. Summary of the invention

[0006] In view of this, it is desirable to improve the operational reliability of electronic devices having such a stacked structure.

[0007] Therefore, it is desirable to provide an electronic device having more excellent operational reliability.

[0008] An electronic device according to an embodiment of the present invention includes a first device board, a second device board and a cavity portion. The second device board is stacked on the first device board and electrically connected to the first device board, and the area of ​​the second device board is larger than the area of ​​the first device board. The cavity portion surrounds at least a portion of the periphery of the first device board along a plane orthogonal to the stacking direction of the first device board and the second device board.

[0009] An electronic device according to an embodiment of the present invention includes a hollow portion surrounding at least a portion of a periphery of a first device board, thereby effectively releasing heat of the first device board. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a cross-sectional view showing a configuration example of a solid-state imaging device according to a first embodiment of the present invention.

[0011] Figure 1B It is shown Figure 1A A plan view of a configuration example of a solid-state imaging device shown in FIG.

[0012] Figure 2A It is shown Figure 1A A cross-sectional view showing a step of a method for manufacturing a solid-state imaging device.

[0013] Figure 2B It is shown Figure 2AA cross-sectional view of a step after the step in FIG.

[0014] Figure 2C It is shown Figure 2B A cross-sectional view of a step after the step in FIG.

[0015] Figure 2D It is shown Figure 2C A cross-sectional view of a step after the step in FIG.

[0016] Figure 2E It is shown Figure 2D A cross-sectional view of a step after the step in FIG.

[0017] Figure 2F It is shown Figure 2E A cross-sectional view of a step after the step in FIG.

[0018] Figure 2G It is shown Figure 2F A plan view of a step following the step in FIG.

[0019] Figure 3A : is a cross-sectional view showing a configuration example of a solid-state imaging device according to a first modification example of the first embodiment of the present invention.

[0020] Figure 3B It is shown Figure 3A A plan view of a configuration example of a solid-state imaging device shown in FIG.

[0021] Figure 4A : is a cross-sectional view showing a configuration example of a solid-state imaging device according to a second modification example of the first embodiment of the present invention.

[0022] Figure 4B It is shown Figure 4A A plan view of a configuration example of a solid-state imaging device shown in FIG.

[0023] Figure 5A It is shown Figure 4A A cross-sectional view showing a step of a method for manufacturing a solid-state imaging device.

[0024] Figure 5B It is shown Figure 5A A cross-sectional view of a step after the step in FIG.

[0025] Figure 5C It is shown Figure 5B A cross-sectional view of a step after the step in FIG.

[0026] Figure 5D It is shown Figure 5C A cross-sectional view of a step after the step in FIG.

[0027] Fig. 6A : is a cross-sectional view showing a configuration example of a solid-state imaging device according to a third modification example of the first embodiment of the present invention.

[0028] Figure 6B It is shown Fig. 6A A plan view of a configuration example of a solid-state imaging device shown in FIG.

[0029] Fig. 7A It is shown Fig. 6A A cross-sectional view showing a step of a method for manufacturing a solid-state imaging device.

[0030] Figure 7B It is shown Fig. 7A A cross-sectional view of a step after the step in FIG.

[0031] Figure 7C It is shown Figure 7B A cross-sectional view of a step after the step in FIG.

[0032] Fig.7D It is shown Figure 7C A cross-sectional view of a step after the step in FIG.

[0033] Figure 8 : is a plan view showing a configuration example of a solid-state imaging device according to a fourth modification example of the first embodiment of the present invention.

[0034] Fig. 9A is a cross-sectional view showing a configuration example of a solid-state imaging device according to a second embodiment of the present invention.

[0035] Fig. 9B It is shown Fig. 9A A plan view of a configuration example of a solid-state imaging device shown in FIG.

[0036] Fig.10 : is a cross-sectional view showing a configuration example of a solid-state imaging device according to a first modification example of the second embodiment of the present invention.

[0037] Fig.11 : is a cross-sectional view showing a configuration example of a solid-state imaging device according to a second modification of the second embodiment of the present invention.

[0038] Fig.12 : is a cross-sectional view showing a configuration example of a solid-state imaging device according to a third modification example of the second embodiment of the present invention.

[0039] Fig.13A is a cross-sectional view showing a configuration example of a solid-state imaging device according to a third embodiment of the present invention.

[0040] Fig. 13B It is shown Fig.13AA plan view of a configuration example of a solid-state imaging device shown in FIG.

[0041] Fig.14 It is shown in an enlarged manner Fig.13A An enlarged cross-sectional view of a configuration example of a logic board of a solid-state imaging device shown in FIG.

[0042] Fig.15A is a cross-sectional view showing a configuration example of a solid-state imaging device according to a first modification of the third embodiment of the present invention.

[0043] Fig. 15B : is a cross-sectional view showing a configuration example of a solid-state imaging device according to a second modification example of the third embodiment of the present invention.

[0044] Fig. 15C : is a cross-sectional view showing a configuration example of a solid-state imaging device according to a third modification example of the third embodiment of the present invention.

[0045] Fig.15D : is a cross-sectional view showing a configuration example of a solid-state imaging device according to a fourth modification example of the third embodiment of the present invention.

[0046] Fig.16 : is a plan view showing a configuration example of a logic board of a solid-state imaging device according to a fifth modification example of the third embodiment of the present invention.

[0047] Fig.17 : is a plan view showing a configuration example of a logic board of a solid-state imaging device according to a sixth modification example of the third embodiment of the present invention.

[0048] Fig.18 : is a cross-sectional view showing a configuration example of a logic board of a solid-state imaging device according to a seventh modification example of the third embodiment of the present invention.

[0049] Fig.19 is a cross-sectional view showing a configuration example of a solid-state imaging device according to a fourth embodiment of the present invention.

[0050] Fig. 20 is a cross-sectional view showing a configuration example of a solid-state imaging device according to a fifth embodiment of the present invention.

[0051] Fig.21 : is a schematic diagram showing an overall configuration example of an electronic device according to a second embodiment of the present invention.

[0052] Fig. 22 is a block diagram showing a schematic configuration example of a vehicle control system.

[0053] Fig.23 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0054] Hereinafter, some embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the description is given in the following order.

[0055] 1. First Embodiment (Example of First Solid-State Imaging Device)

[0056] 2. Modification of the First Embodiment (Modification of the First Solid-State Imaging Device)

[0057] 3. Second Embodiment (Example of Second Solid-State Imaging Device)

[0058] 4. Modification of the Second Embodiment (Modification of the Second Solid-State Imaging Device)

[0059] 5. Third Embodiment (Example of Third Solid-State Imaging Device)

[0060] 6. Modification of the Third Embodiment (Modification of the Fourth Generation Solid-State Imaging Device)

[0061] 7. Fourth Embodiment (Example of Fourth Solid-State Imaging Device)

[0062] 8. Fifth Embodiment (Embodiment of a Fifth Solid-State Imaging Device)

[0063] 9. Sixth Embodiment (Application Example to Electronic Equipment)

[0064] 10. Examples of practical applications on mobile objects

[0065] 11. Other Modifications

[0066] [1. First embodiment]

[0067] [Configuration of Solid-State Imaging Device 1]

[0068] Figure 1A and 1B Each of the configuration examples of the solid-state imaging device 1 according to the first embodiment of the present invention is schematically shown. Figure 1A shows a cross-sectional configuration example of the solid-state imaging device 1, and Figure 1B A planar configuration example of the solid-state imaging device 1 is shown. Figure 1A Corresponding to the stack along Figure 1B The cross-sectional view of the cutting line IA-IA in the direction of the arrow is shown. In addition, Figure 1A Corresponding to Figure 1A A horizontal cross-sectional view at the height position indicated by the dotted line IB.

[0069] like Figure 1A As shown, the solid-state imaging device 1 has a stacked structure in which a logic layer 40 , an intermediate layer 30 , and a sensor board 20 are sequentially stacked on a support layer 10 .

[0070] [Support layer 10]

[0071] The support layer 10 includes, for example, a support plate 11 and a metal film 52. The support plate 11 is, for example, a Si (silicon) plate, and has a front surface 11FS and a back surface 11BS. The metal film 52 is provided to cover the back surface 11BS.

[0072] [Logical layer 40]

[0073] The logic layer 40 includes one or more logic boards 41 . Figure 1A and 1B The case where two logic boards 41 are provided for one sensor board 20 is shown respectively. However, the solid-state imaging device 1 may include only one logic board 41, or include more than three logic boards 41. That is, the number of logic boards 41 may be set for one sensor board 20 as needed. The logic board 41 is electrically connected to the sensor board 20 through the intermediate layer 30. The logic board 41 is a specific example corresponding to the “first device board” of the present invention. The sensor board 20 is a specific example corresponding to the “second device board” of the present invention.

[0074] like Figure 1A and 1B As shown, two logic boards 41 are spaced apart from each other along the XY plane. The XY plane is orthogonal to the Z-axis direction. The Z-axis direction is the stacking direction of the logic board 41, the intermediate layer 30, and the sensor board 20. A cavity portion V is provided at the periphery of each logic board 41. The cavity portion V is provided to surround the periphery of the logic board 41 along the XY plane. The cavity portion V is, for example, a heat sink, which is used to release the heat generated in the logic board 41 to the periphery of the logic board 41. In the solid-state imaging device 1, the cavity portion V is provided at the same level as the logic board 41. Note that in the solid-state imaging device 1, there is a cavity portion V surrounding the outer edge 41K of the logic board 41 over the entire circumference along the XY plane. However, in the present invention, the cavity portion V may surround at least a portion of the logic board 41. The cavity portion V also exists in the space between a pair of adjacent logic boards 41. Note that the cavity portion V may be provided in at least a portion of the space between a plurality of logic boards 41. That is, the present invention is not limited to the case where the cavity V exists entirely in the space between the plurality of logic boards 41 .

[0075] The cavity portion V may communicate with the outside of the solid-state imaging device 1. That is, the outside air may be introduced into and exhausted from the cavity portion V. In this case, the cavity portion V may function as a ventilation passage.

[0076] At least a portion of the cavity V is defined by a metal film 51 covering the logic board 41. That is, the cavity V is separated from the periphery of the logic board by the metal film 51. In the solid-state imaging device 1, the cavity V is defined by the metal film 51 and the metal film 52, and is separated from the logic board 41 and the support board 11. The metal film 51 continuously covers the end surface 41T of the logic board 41 along the outer edge 41K of the logic board 41 and the front surface 41FS of the logic board 41 on the opposite side of the sensor board 20. Note that the metal films 51 covering a plurality of adjacent logic boards 41 may be connected to each other. In addition, an insulating layer 44 including, for example, SiN (silicon nitride) may be provided between the metal film 51 and the end surface 41T and the front surface 41FS of the logic board 41. Figure 1A An example of the following case is shown: the insulating layer 44 and the metal film 51 are formed to cover the front surface 30FS of the intermediate layer 30 also at the periphery of the logic board 41. Here, the metal film 51 and the metal film 52 are integrated with each other and constitute a metal frame 50. Therefore, it can be said that the cavity portion V is contained inside the metal frame 50. The metal film 51 and the metal film 52 may respectively include at least one of Al (aluminum), W (tungsten), and Cu (copper). The material contained in the metal film 51 and the material contained in the metal film 52 may be the same as or different from each other. In addition, the metal film 51 and the metal film 52 may be formed by, for example, an atomic layer deposition (ALD) method, respectively; however, their manufacturing methods are not limited thereto.

[0077] The logic board 41 is provided with a logic circuit. The logic circuit includes, for example, a wiring layer 42 and a semiconductor element 43 such as a transistor. A surface of a portion of the wiring layer 42 is exposed to the back side 41BS of the logic board 41. The back side 41BS of the logic board 41 is bonded to the front side 30FS of the intermediate layer 30. The wiring layer 42 includes, for example, Cu (copper).

[0078] [Middle layer 30]

[0079] The intermediate layer 30 includes an insulating layer 31 and wiring layers 32 to 38 embedded in the insulating layer 31. The insulating layer 31 may include an inorganic oxide, such as silicon oxide (SiOx) or silicon nitride (SiNx). The wiring layers 32 to 38 are stacked in sequence from the front surface 30FS to the back surface 30BS of the intermediate layer 30 along the Z-axis direction. The wiring layer 32 is exposed to the front surface 30FS and is bonded to the wiring layer 42 of the logic board 41. The wiring layers 32 to 38 each include, for example, Cu (copper). Note that Figure 1A The wiring layers 32 to 38 are examples, and the number of wiring layers present in the intermediate layer 30, the size and position of the wiring layers present in the intermediate layer 30, etc. are not limited to Figure 1A In the example shown, the back surface 30BS of the intermediate layer 30 is bonded to the front surface FS of the sensor plate 20 .

[0080] [Sensor board 20]

[0081] In the sensor board 20, a solid-state imaging element 22 and wiring layers 23 to 26 are provided in a base 21. The occupied area of ​​the sensor board 20 in the XY plane is larger than the occupied area of ​​the logic board 41 in the XY plane. The solid-state imaging element 22 includes a plurality of pixels (these pixels include, for example, a photodiode 22A), and is configured to generate pixel signals by receiving external light in units of pixels. The solid-state imaging element 22 also includes, for example, a protective film 22B, a color filter 22C, and a microlens 22D. The wiring layers 23 to 26 are stacked in sequence from the front side 20FS to the photodiode 22A along the Z-axis direction. The wiring layer 23 is exposed to the front side 23FS and is bonded to the wiring layer 38 of the intermediate layer 30. The wiring layers 23 to 26 each include, for example, Cu (copper). Note that, Figure 1A The wiring layers 23 to 26 in the sensor board 20 are examples, and the number of wiring layers present in the sensor board 20, the size and position of the wiring layers present in the sensor board 20, etc. are not limited to Figure 1A The logic circuit of the logic board 41 and the solid-state imaging element 22 of the sensor board 20 are electrically connected to each other through the wiring layers 32 to 38 and the wiring layers 23 to 26 .

[0082] [Method of Manufacturing Solid-State Imaging Device 1]

[0083] Next, we will refer to Figures 2A to 2G A method of manufacturing the solid-state imaging device 1 will be described. Figures 2A to 2G Each of them is a cross-sectional view showing one step of the method for manufacturing the solid-state imaging device 1, and corresponds to Figure 1A .Notice, Figures 2A to 2F The process of manufacturing a solid-state imaging device 1 is exemplified, but in reality, Figure 2G As shown, a plurality of solid-state imaging devices 1 are collectively formed on a single wafer (support plate 11 ), and then dicing is performed for each solid-state imaging device 1 .

[0084] First, if Figure 2A As shown, the back side 20BS of the sensor board 20Z is fixed to the support board 61. The configuration of the sensor board 20Z is basically the same as that of the sensor board 20, except that the sensor board 20Z includes the photodiode 22A in the solid-state imaging element 22, but does not include the protective film 22B, the color filter 22C, and the microlens 22D. Subsequently, the back side 30BS of the intermediate layer 30 is bonded to the front side 20FS of the sensor board 20Z by the WoW stacking technology. In this case, the wiring layer 23 and the wiring layer 38 are directly bonded to each other.

[0085] Afterwards, if Figure 2BAs shown, a separately prepared logic board 41 is bonded to the front side 30FS of the intermediate layer 30 by a chip on wafer (CoW) stacking technology. Thus, a stacked body SS is obtained. Thereafter, the logic board 41 is ground as needed to adjust the thickness of the logic board 41. In the case of arranging a plurality of logic boards 41, the height positions of the front sides 41FS of the plurality of logic boards 41 are adjusted so that they are aligned with each other.

[0086] Afterwards, if Figure 2C As shown, the insulating layer 44 is formed to cover at least the front surface 30FS of the intermediate layer 30 and the end surface 41T and the front surface 41FS of the logic board 41 .

[0087] Then, if Figure 2D As shown, trimming is performed along the outline of the stacked body of the sensor board 20Z, the intermediate layer 30, and the logic layer 40, and the peripheral portion of the support plate 61 along the outline of the stacked body SS is hollowed out in the thickness direction to reduce its thickness. This is done to prevent defects such as the support plate 61 being cut into an unexpected shape when cutting into individual solid-state imaging devices 1.

[0088] Then, if Figure 2E As shown, a metal film 51 is further formed on a portion of the insulating layer 44 covering the front surface 30FS of the intermediate layer 30 and the end surface 41T and the front surface 41FS of the logic board 41. In this case, by forming the metal film 51 using the ALD method, the metal film 51 having a more uniform thickness can be obtained.

[0089] Then, if Figure 2F As shown, a metal film 52 is formed on the flat back surface 11BS of the support plate 11, and then the metal film 51 and the metal film 52 are brought into contact with each other and bonded to each other by compression bonding at room temperature. Alternatively, the metal film 51 and the metal film 52 may be heated and bonded to each other by thermocompression bonding. After that, the support plate 61 is ground to reduce its thickness, and then a protective film 22B, a color filter 22C, and a photodiode 22D are sequentially formed on the photodiode 22A to form the solid-state imaging element 22.

[0090] As mentioned above, Figure 2G As shown in FIG. 1 , a plurality of solid-state imaging devices 1 are formed on a support plate 11. Then, the surface 11FS of the support plate 11 is ground as needed to process the thickness of the support plate 11 to have a predetermined thickness. Finally, a cutting knife or the like is used to cut the surface 11FS of the support plate 11 to form a plurality of solid-state imaging devices 1 on the support plate 11. Figure 2G The positions shown by the dotted lines in FIG. 1 are cut to cut out a plurality of solid-state imaging devices 1. Thus, the manufacture of the solid-state imaging device 1 is completed.

[0091] [Function and Effect of Solid-State Imaging Device 1]

[0092] As described above, in the solid-state imaging device 1 of the present embodiment, the cavity portion V is provided to surround at least a portion of the periphery of the logic board 41 along the XY plane orthogonal to the stacking direction of the logic board 41 and the sensor board 20. Therefore, the cavity portion V serves as a heat sink, and the heat of the logic board 41 is effectively released. Thus, the influence on the operating performance of the solid-state imaging device 1, which is attributed to the dark current caused by the temperature rise of the logic board 41, can be reduced. Therefore, high operational reliability of the solid-state imaging device 1 can be ensured. In addition, the solid-state imaging device 1 of the present embodiment has high heat dissipation, which is also conducive to further high integration.

[0093] Furthermore, in the solid-state imaging device 1 , the cavity portion V is also provided in the space between two adjacent logic boards 41 , whereby the heat of each logic board 41 can be released to the outside more effectively through the cavity portion V.

[0094] In addition, in the solid-state imaging device 1 , the cavity portion V communicates with the outside, whereby the outside air can be introduced into and exhausted from the cavity portion V, thereby further improving the heat dissipation performance.

[0095] In addition, in the solid-state imaging device 1, the end surface 41T and the front surface 41FS of the logic board 41 are continuously covered with the metal film 51, thereby the heat of the logic board 41 can also be effectively released through the metal film 51. In addition, a metal film 52 is also provided on the back surface 11BS of the support plate 11, so that the metal film 51 and the metal film 52 are bonded to each other, thereby achieving higher heat dissipation performance. In addition, even if there is a cavity V in the solid-state imaging device 1, the solid-state imaging device 1 also includes a metal frame 50 including the metal film 51 and the metal film 52 bonded to each other. Thus, light passing through the front surface 11FS can be prevented from entering the sensor board 20. This also enables the support layer 10 to firmly support the logic board 41, the intermediate layer 30, and the sensor board 20.

[0096] [2. Modification of the first embodiment]

[0097] [Configuration of Solid-State Imaging Device 1A]

[0098] Figure 3A is a cross-sectional view showing an example of a cross-sectional configuration of a solid-state imaging device 1A according to a first modification example (hereinafter referred to as modification example 1-1) of the present embodiment, and corresponds to the cross-sectional view showing an example of a cross-sectional configuration of the solid-state imaging device 1 according to the first embodiment described above. Figure 1A .also, Figure 3B 1 is a plan view showing a planar configuration example of the solid-state imaging device 1A, and corresponds to FIG. 1 showing a planar configuration example of the solid-state imaging device 1 according to the first embodiment described above. Figure 1B . Figure 3A Corresponding to the stack along Figure 3BThe cross-sectional view of the cutting line IIIA-IIIA in the direction of the arrow is shown. In addition, Figure 3B Corresponding to Figure 3A A horizontal cross-sectional view at the height indicated by the dashed line IIIB in FIG. Figure 3B In FIG. 1 , a two-dot chain line indicates a boundary between a plurality of solid-state imaging devices 1A adjacent to each other in a state before being divided into individual solid-state imaging devices 1A.

[0099] [Function and Effect of Solid-State Imaging Device 1A]

[0100] like Figure 3A As shown, in the solid-state imaging device 1A of the modification 1-1, the dummy board D is arranged adjacent to the logic board 41 in the logic layer 40. The dummy board D is arranged to straddle the boundary with another adjacent solid-state imaging device 1A. Therefore, in the solid-state imaging device 1A, the support layer 10 supports the logic board 41, the intermediate layer 30, and the sensor board 20 more firmly than the solid-state imaging device 1. Therefore, when a plurality of solid-state imaging devices 1A formed on one support board 11 are to be cut into individual solid-state imaging devices 1A by a cutting knife or the like, it is possible to cut more accurately and smoothly than when the dummy board D is not provided.

[0101] Furthermore, in the solid-state imaging device 1A, a cavity V is provided around at least a portion of the periphery of the logic board 41, thereby effectively releasing heat from the logic board 41. Therefore, effects similar to those of the solid-state imaging device 1 can be achieved.

[0102] [Configuration of Solid-State Imaging Device 1B]

[0103] Figure 4A is a cross-sectional diagram showing an example of a cross-sectional configuration of a solid-state imaging device 1B according to a second modification example (hereinafter referred to as modification example 1-2) of the present embodiment, and corresponds to the cross-sectional diagram showing an example of a cross-sectional configuration of the solid-state imaging device 1 according to the first embodiment described above. Figure 1A .also, Figure 4B is a plan view showing a planar configuration example of the solid-state imaging device 1B, and corresponds to FIG. 1 showing a planar configuration example of the solid-state imaging device 1 according to the above-described first embodiment. Figure 1B . Figure 4A Corresponding to the stack along Figure 4B The cross-sectional view of the cutting line IVA-IVA in the direction of the arrow is shown. In addition, Figure 4B Corresponding to Figure 4A A horizontal cross-sectional view at the height position indicated by the dotted line IVB.

[0104] In the solid-state imaging device 1 according to the first embodiment described above, the logic layer 40 is stacked on the support layer 10, in which a flat metal film 52 is provided on the support plate 11 having a flat plate shape. In contrast, the solid-state imaging device 1B according to the modification 1-2 adopts the support layer 10B instead of the support layer 10. Specifically, a recess 11U1 and a recess 11U2 are provided on the support plate 11, and the logic board 41 is accommodated in each of the recesses 11U1 and 11U2. In the solid-state imaging device 1B, it is sufficient as long as at least a portion of the logic board 41 in the thickness direction is accommodated in the recesses 11U1 and 11U2. That is, in a state where the solid-state imaging device 1B is observed along the XY plane, the support layer 10B and at least a portion of the logic layer 40 overlap each other. The inner surface of each of the recesses 11U1 and 11U2 is covered with a metal film 52. Here, the portion of the metal film 52 covering the bottom surface 11US and the side surface 11WS of each of the recesses 11U1 and 11U2 is spaced apart from the portion of the metal film 51 covering the front surface 41FS and the end surface 41T of the logic board 41, thereby forming the hollow portions V1 and V2. That is, the hollow portions V1 and V2 also exist between the logic board 41 and the support board 11. Note that the hollow portion V1 and the hollow portion V2 exist in the periphery of a corresponding one of the different logic boards 41, respectively, and are separated from each other.

[0105] [Method of Manufacturing Solid-State Imaging Device 1B]

[0106] Next, refer to Figures 5A to 5D Description of the Manufacturing Method of the Solid-State Imaging Device 1B Here, the manufacturing method of the supporting layer 10B of the solid-state imaging device 1B will be described in detail. Figures 5A to 5D Each of them is a cross-sectional view showing one step of the method for manufacturing the support layer 10B. Note that Figures 5A to 5D A manufacturing process of the support layer 10B including two recessed portions 11U1 and 11U2 is shown; however, the number of recessed portions is not limited thereto.

[0107] First, if Figure 5A As shown, for example, a silicon plate 11Z is prepared, and then an inorganic film IF including SiO2 or the like is formed to completely cover the back surface 11BS. Thereafter, a resist film is formed to completely cover the inorganic film IF, and then the resist film is selectively removed by photolithography or the like to obtain a resist pattern RP.

[0108] Then, if Figure 5B As shown, the inorganic film IF is patterned by a selective etching process using the resist pattern RP as a mask to obtain an inorganic film pattern IFP. Thus, a portion of the back surface 11BS is exposed.

[0109] Then, if Figure 5CAs shown, the exposed portion of the silicon plate 11Z is removed by a selective etching process using the inorganic film pattern IFP as a mask, thereby obtaining the support plate 11 including the recessed portions 11U1 and 11U2.

[0110] Finally, if Figure 5D As shown, the inorganic film pattern IFP is removed, and then the metal film 52 is formed to cover the entire support plate 11 including the bottom surface 11US and the side surface 11WS of each of the recesses 11U1 and 11U2 .

[0111] Thereby, the production of the supporting layer 10B is completed. Thereafter, the solid-state imaging device 1B can be produced similarly to the solid-state imaging device 1 explained in the first embodiment.

[0112] [Function and Effect of Solid-State Imaging Device 1B]

[0113] In the solid-state imaging device 1B according to the modification 1-2, the recess 11U1 and the recess 11U2 are provided in the support plate 11, and the logic board 41 is accommodated in each of the recesses 11U1 and 11U2. Therefore, compared with the solid-state imaging device 1, high heat dissipation can be achieved while improving the mechanical strength. In addition, in the solid-state imaging device 1B, there are also hollow portions V1 and V2 between the logic board 41 and the support plate 11. This increases the surface area of ​​the logic board 41 exposed to the hollow portions V1 and V2, and the heat dissipation can be further improved.

[0114] [Configuration of Solid-State Imaging Device 1C]

[0115] Fig. 6A is a cross-sectional view showing an example of a cross-sectional configuration of a solid-state imaging device 1C according to a third modification example (hereinafter referred to as modification example 1-3) of the present embodiment, and corresponds to the cross-sectional view showing an example of a cross-sectional configuration of the solid-state imaging device 1 according to the first embodiment described above. Figure 1A .also, Figure 6B 1 is a plan view showing a planar configuration example of the solid-state imaging device 1C, and corresponds to FIG. 1 showing a planar configuration example of the solid-state imaging device 1 according to the above-described first embodiment. Figure 1B . Fig. 6A Corresponding to the stack along Figure 6B The cross-sectional view of the cutting line VIA-VIA in the direction of the arrow is shown. In addition, Figure 6B Corresponding to Fig. 6A A horizontal cross-sectional view at the height position indicated by the dotted line VIB.

[0116] The solid-state imaging device 1C according to the modification 1-3 adopts a support layer 10C instead of the support layer 10. Specifically, a recess 11U1 and a recess 11U2 are provided in the support plate 11, and the logic board 41 is accommodated in each of the recesses 11U1 and 11U2. Note that in the solid-state imaging device 1C, a portion of the metal film 52 covering the bottom surface 11US of each recess 11U1 and 11U2 abuts against a portion of the metal film 51 covering the front surface 41FS of the logic board 41. On the contrary, a portion of the metal film 52 covering the side surface 11WS of each recess 11U1 and 11U2 is spaced apart from a portion of the metal film 51 covering the end surface 41T of the logic board 41, thereby forming cavity portions V1 and V2. Except for this, the structure of the solid-state imaging device 1C is substantially the same as that of the solid-state imaging device 1B.

[0117] [Method of Manufacturing Solid-State Imaging Device 1C]

[0118] Next, we will refer to Figures 7A to 7D Description of the Manufacturing Method of the Solid-State Imaging Device 1C Here, the manufacturing method of the supporting layer 10C of the solid-state imaging device 1C will be described in detail. Figures 7A to 7D Each of them shows a cross-sectional view of a step of the method for manufacturing the support layer 10C. Note that Figures 7A to 7D A manufacturing process of the support layer 10C including two recesses 11U1 and 11U2 is shown; however, the number of recesses is not limited thereto.

[0119] First, if Fig. 7A As shown, for example, a silicon plate 11Z is prepared, and then an inorganic film IF including SiO2 or the like is formed to completely cover the back side 11BS. However, the silicon plate 11Z includes a high-concentration impurity layer BB including boron (B) or the like in a portion in its thickness direction. Thereafter, a resist film is formed to completely cover the inorganic film IF, and then the resist film is selectively removed by photolithography or the like to obtain a resist pattern RP.

[0120] Then, if Figure 7B As shown, the inorganic film IF is patterned by a selective etching process using the resist pattern RP as a mask to obtain an inorganic film pattern IFP. Thus, a portion of the back surface 11BS is exposed.

[0121] Then, if Figure 7C As shown, the exposed portion of the silicon plate 11Z is removed by a selective etching process using the inorganic film pattern IFP as a mask, thereby obtaining the support plate 11 including the recesses 11U1 and 11U2. At this time, the high-concentration impurity layer BB is used as an etching stopper, and the depth of each recess 11U1 and 11U2 is controlled with high precision.

[0122] Finally, if Fig.7DAs shown, the inorganic film pattern IFP is removed, and then the metal film 52 is formed to cover the entire support plate 11 including the bottom surface 11US and the side surface 11WS of each of the recesses 11U1 and 11U2 .

[0123] Thereby, the manufacturing of the supporting layer 10C is completed. Thereafter, the solid-state imaging device 1C can be manufactured in the same manner as the solid-state imaging device 1 described in the first embodiment.

[0124] [Function and Effect of Solid-State Imaging Device 1C]

[0125] In the solid-state imaging device 1C according to the modification 1-3, the recess 11U1 and the recess 11U2 are provided in the support plate 11, and the logic board 41 is accommodated in each of the recesses 11U1 and 11U2. Therefore, compared with the solid-state imaging device 1, high heat dissipation can be achieved while improving the mechanical strength. In addition, in the solid-state imaging device 1B, the portion of the metal film 52 covering the bottom surface 11US of each recess 11U1 and 11U2 abuts against the portion of the metal film 51 covering the front surface 41FS of the logic board 41. Therefore, compared with the support layer 10 or the support layer 10B, a reduction in the thickness of the support layer 10C can be achieved. In addition, the heat of the logic board 41 is effectively released through the metal film 51 and the metal film 52.

[0126] [Configuration of Solid-State Imaging Device 1D]

[0127] Figure 8 is a plan view showing a planar configuration example of a solid-state imaging device 1D according to a fourth modification example (hereinafter referred to as modification example 1-4) of the present embodiment, and corresponds to the plan view showing a planar configuration example of the solid-state imaging device 1 according to the first embodiment described above. Figure 1B In the solid-state imaging device 1D according to the fourth modification, the cavity portions V1 and V2 are connected to each other and are respectively connected to the outside. Thus, the heat dissipation performance can be further improved.

[0128] [3. Second embodiment]

[0129] [Configuration of Solid-State Imaging Device 2]

[0130] Fig. 9A and 9B Each of the configuration examples of the solid-state imaging device 2 according to the second embodiment of the present invention is schematically shown. Fig. 9A shows a cross-sectional configuration example of the solid-state imaging device 2, and Fig. 9B A planar configuration example of the solid-state imaging device 2 is shown. Fig. 9A Corresponding to the stack along Fig. 9B The cross-sectional view of the cutting line IXA-IXA in the direction of the arrow is shown. In addition, Fig. 9B Corresponding to Fig. 9AA horizontal cross-sectional view at the height position indicated by the dotted line IXB.

[0131] In the solid-state imaging device 1 according to the first embodiment, the logic layer 40 includes more than one logic board 41. In contrast, in the solid-state imaging device 2 according to the present embodiment, in addition to the logic board 41, the logic layer 40 also includes a heat sink 71. The heat sink 71 is provided at a position adjacent to the logic board 41 along the XY plane, and its area in the XY plane is smaller than that of the sensor board 20. A cavity V is also provided around the periphery of the heat sink 71. The cavity V is provided to surround the periphery of the heat sink 71 along the XY plane. Therefore, there is also a cavity V between the heat sink 71 and the adjacent logic board 41. Note that the number of heat sinks 71 may be more than two.

[0132] The thermal conductivity of the heat sink 71 is, for example, higher than that of the logic board 41. In addition, the thermal conductivity of the heat sink 71 may be higher than that of the sensor board 20. The heat sink 71 includes, for example, a metal layer 72, an insulating layer 73 stacked on the metal layer 72, and a wiring 74 embedded in the insulating layer 73. The metal layer 72 extends along the XY plane. The metal layer 72 may, for example, extend throughout the heat sink 71. The metal layer 72 includes a single substance of a metal element having a relatively high thermal conductivity, such as Ag (silver), Al (aluminum), Cu (copper), Ti (titanium), or W (tungsten), or an alloy including these metal elements. The insulating layer 73 includes an insulating material such as aluminum oxide, etc. In addition, a portion of the wiring 74 is exposed to the back side 71BS of the heat sink 71. The wiring 74 does not constitute a circuit such as a logic circuit, and is a so-called dummy wiring. The wiring layer 74 includes, for example, Cu (copper). The back side 71BS of the heat sink 71 is bonded to the front side 30FS of the intermediate layer 30. Like the front surface 41FS and the end surface 41T of the logic board 41 , the front surface 71FS and the end surface 71T of the heat dissipation plate 71 may be covered with the metal film 52 .

[0133] [Method of Manufacturing Solid-State Imaging Device 2]

[0134] The manufacturing method of the solid-state imaging device 2 is basically the same as the manufacturing method of the solid-state imaging device 1 of the above-mentioned first embodiment, but the difference is that when some logic boards 41 need to be joined to the front side 30FS of the intermediate layer 30, more than one heat sink 71 (instead of more than one logic board 41) needs to be joined to the front side 30FS of the intermediate layer 30.

[0135] [Function and Effect of Solid-State Imaging Device 2]

[0136] As described above, in the solid-state imaging device 2 of this embodiment, the heat sink 71 having higher thermal conductivity than the logic board 41 is provided as the third device board above the sensor board 20, thereby being able to effectively release the heat of the logic board 41 to the outside.

[0137] [4. Modification of the Second Embodiment]

[0138] [Configuration of Solid-State Imaging Device 2A]

[0139] Fig.10 is a cross-sectional view showing an example of a cross-sectional configuration of a solid-state imaging device 2A according to a first modification example (hereinafter referred to as modification example 2-1) of the present embodiment, and corresponds to the cross-sectional view showing an example of a cross-sectional configuration of the solid-state imaging device 2 according to the second embodiment described above. Fig. 9A .

[0140] like Fig.10 As shown, in the solid-state imaging device 2A of Modification 2-1, the heat sink 71 includes only the metal layer 72. Except for this, the configuration of the solid-state imaging device 2A is basically the same as that of the solid-state imaging device 2 of the second embodiment described above.

[0141] [Function and Effect of Solid-State Imaging Device 2A]

[0142] In the solid-state imaging device 2A of the modification 2-1, the heat sink 71 includes only the metal layer 72, thereby increasing the volume of the metal layer 72 compared with the solid-state imaging device 2 of the second embodiment. As a result, the heat dissipation performance of the heat sink 71 can be further improved. Therefore, the heat of the logic board 41 or the sensor board 20 can be released to the outside more effectively.

[0143] [Configuration of Solid-State Imaging Device 2B]

[0144] Fig.11 is a cross-sectional view showing an example of a cross-sectional configuration of a solid-state imaging device 2B according to a second modification example (hereinafter referred to as modification example 2-2) of the present embodiment, and corresponds to the cross-sectional view showing an example of a cross-sectional configuration of the solid-state imaging device 2 according to the second embodiment described above. Fig. 9A .

[0145] like Fig.11 As shown, in the solid-state imaging device 2B of the modification 2-2, the heat sink 71 includes one or more fins 75 vertically arranged on the metal layer 72. Except for this, the configuration of the solid-state imaging device 2B is basically the same as the configuration of the solid-state imaging device 2 of the second embodiment described above. Note that the fin 75 can be provided integrally with the metal layer 72. That is, the metal layer 72 can include the fin structure 75,

[0146] [Function and Effect of Solid-State Imaging Device 2B]

[0147] In the solid-state imaging device 2B of the modification 2-2, the heat sink 71 includes the fins 75, thereby further improving the heat dissipation performance of the heat sink 71 compared with the solid-state imaging device 2 of the second embodiment. Therefore, the heat of the logic board 41 or the sensor board 20 can be released to the outside more effectively.

[0148] [Configuration of Solid-State Imaging Device 2C]

[0149] Fig.12 is a cross-sectional view showing an example of a cross-sectional configuration of a solid-state imaging device 2C according to a third modification example (hereinafter referred to as modification example 2-3) of the present embodiment, and corresponds to the cross-sectional view showing an example of a cross-sectional configuration of the solid-state imaging device 2 according to the second embodiment described above. Fig. 9A .

[0150] like Fig.12 As shown, in the solid-state imaging device 2C of the modification 2-3, the heat sink 71 includes a cooling element 76 instead of the insulating layer 73 and the wiring 74. Except for this, the configuration of the solid-state imaging device 2C is basically the same as the configuration of the solid-state imaging device 2B of the above-mentioned modification 2-2. As the cooling element 76, for example, a Peltier element can be used. In the case where the cooling element 76 is, for example, a Peltier element, a path for supplying power required for its operation can be provided.

[0151] [Function and Effect of Solid-State Imaging Device 2C]

[0152] In the solid-state imaging device 2C of the modification 2-3, the heat sink 71 further includes a cooling element 76, thereby further improving the heat dissipation performance of the heat sink 71 compared to the solid-state imaging device 2B of the above modification 2-2. Therefore, the heat of the logic board 41 or the sensor board 20 can be released to the outside more effectively.

[0153] Note that in the solid-state imaging device 2 of the second embodiment, a cooling element 76 may be provided instead of the insulating layer 73 and the wiring 74. Also, in the solid-state imaging device 2A of the modification 2-1, a cooling element 76 may be provided instead of the insulating layer 73 and the wiring 74.

[0154] [5. Third embodiment]

[0155] [Configuration of Solid-State Imaging Device 3]

[0156] Fig.13A and 13B Each of the configuration examples of the solid-state imaging device 3 according to the third embodiment of the present invention is schematically shown. Fig.13A shows a cross-sectional configuration example of the solid-state imaging device 3, and Fig. 13B A planar configuration example of the solid-state imaging device 3 is shown. Fig.13A Corresponding to the stack along Fig. 13B The cross-sectional view of the cutting line XIIIA-XIIIA in the direction of the arrow is shown. In addition, Fig. 13B Corresponding to Fig.13A A horizontal cross-sectional view at the height position indicated by the dotted line XIIIB.

[0157] In the solid-state imaging device 3 according to the present embodiment, the logic layer 40 includes a logic board 41A instead of the logic board 41. Except for this, the configuration of the solid-state imaging device 3 is substantially the same as that of the solid-state imaging device 1. Therefore, in the following description, the logic board 41A of the solid-state imaging device 3 will be mainly described, and the components in the solid-state imaging device 3 that are the same as those of the solid-state imaging device 1 are denoted by the same reference numerals, and the description thereof will be appropriately omitted.

[0158] like Fig.13A and 13B As shown, the logic board 41A includes a semiconductor substrate 411 and an insulating layer 412 stacked on the semiconductor substrate 411. The semiconductor element 43 is provided in the semiconductor substrate 411. The wiring layer 42 is provided in the insulating layer 412. In addition, in the logic board 41A, at least a portion of the surface of the semiconductor substrate 411 other than the back surface 41BS has a concavo-convex structure 45. Fig.13A and 13B The example of the case where the front surface 41AFS is a surface having a concavo-convex structure 45 is shown. The concavo-convex structure 45 includes concave portions 45U and convex portions 45T. The back surface 41BS is an opposing surface opposite to the front surface 20FS of the sensor board 20, and is also a bonding surface to be bonded to the front surface 30FS of the intermediate layer 30. Fig.13A and 13B In the illustrated configuration example, for example, a plurality of recesses 45U extending in the X-axis direction and a plurality of recesses 45U extending in the Y-axis direction are arranged in a mutually intersecting manner. That is, in the front surface 41AFS of the semiconductor substrate 411, the recesses 45U are arranged in a lattice pattern in the XY plane. Fig.13A As shown, the cross-sectional shape of the recess 45U is, for example, a substantially V-shaped shape. However, the cross-sectional shape of the recess 45U is not limited thereto, and various cross-sectional shapes other than the substantially V-shaped shape may also be adopted, examples of which include a rectangle, an inverted trapezoid, a semicircle, a semi-ellipse, and a U-shape.

[0159] In addition, for example, the front surface roughness of the concavo-convex structure 45 mentioned in the present embodiment is greater than the front surface roughness of the front surface flattened by chemical mechanical polishing (CMP). The front surface 41AFS is a surface of the logic board 41A having the concavo-convex structure 45, and its arithmetic mean roughness Ra value is greater than 0.2nm or its root mean square roughness Rms value is greater than 0.25nm. In addition, a cavity portion V is provided around the logic board 41A. At least a portion of the cavity portion V is defined by a metal film 51 covering the logic board 41A. The metal film 51 continuously covers the end surface 41AT of the logic board 41A and the front surface 41AFS of the logic board 41A.

[0160] Fig.14 It is shown in an enlarged manner Fig.13A FIG. 4 is an enlarged cross-sectional view of the logic board 41A shown in FIG. Fig.14 As shown, in the solid-state imaging device 3 of the present embodiment, a gap AG is provided between the front surface 41FS of the logic board 41A and the metal film 51. Specifically, a plurality of gaps AG exist in the respective plurality of recessed portions 45U.

[0161] [Method of Manufacturing Solid-State Imaging Device 3]

[0162] The manufacturing method of the solid-state imaging device 3 is substantially the same as the manufacturing method of the solid-state imaging device 1 of the first embodiment described above, but the difference lies in that the logic board 41 is bonded to the front surface 30FS of the intermediate layer 30, and the logic board 41 is ground as needed to adjust the thickness of the logic board 41 (see Figure 2B ), and then a concavo-convex structure 45 is formed by at least one of dry etching and wet etching.

[0163] [Function and Effect of Solid-State Imaging Device 3]

[0164] As described above, in the solid-state imaging device 3 of the present embodiment, the logic board 41A has the concavo-convex structure 45 in at least a portion of the surface other than the back surface 41BS of the semiconductor substrate 411, thereby increasing the surface area of ​​the logic board 41A compared with, for example, the logic board 41 of the solid-state imaging device 1 according to the first embodiment. Therefore, according to the solid-state imaging device 3, the logic board 41A has high heat dissipation, and the heat of the logic board 41A or the sensor board 20 can be effectively released to the outside. Specifically, the gap AG is provided between the front surface 41AFS of the logic board 41A and the metal film 51, thereby enabling the heat of the logic board 41A or the sensor board 20 to be more effectively released to the outside.

[0165] [6. Modification of the third embodiment]

[0166] [First Modification]

[0167] [Configuration of Solid-State Imaging Device 3A]

[0168] Fig.15A is an enlarged cross-sectional view showing an example of a cross-sectional configuration of a portion of a solid-state imaging device 3A according to a first modification example (hereinafter referred to as modification example 3-1) of the present embodiment in an enlarged manner, and corresponds to a cross-sectional view showing a cross-sectional configuration example of a portion of a solid-state imaging device 3A according to the third embodiment described above. Fig.14 .

[0169] like Fig.15A As shown, in the solid-state imaging device 3A of Modification 3-1, the metal film 51 is provided to also fill the inside of the recess 45U provided in the semiconductor substrate 411. Except for this, the configuration of the solid-state imaging device 3A is basically the same as that of the solid-state imaging device 3 of the third embodiment described above.

[0170] [Function and Effect of Solid-State Imaging Device 3A]

[0171] In the solid-state imaging device 3A of Modification 3-1, the metal film 51 is provided to also fill the concave portion 45U of the concavo-convex structure 45 , whereby the bonding strength between the metal film 51 and the logic board 41A can be increased.

[0172] [Second Modification]

[0173] [Configuration of Solid-State Imaging Device 3B]

[0174] Fig. 15B is an enlarged cross-sectional view showing an example of a cross-sectional configuration of a part of a solid-state imaging device 3B according to a second modification example (hereinafter referred to as modification example 3-2) of the present embodiment in an enlarged manner, and corresponds to a cross-sectional view showing an example of a cross-sectional configuration of a part of the solid-state imaging device 3B according to the third embodiment described above. Fig.14 .

[0175] like Fig. 15B As shown, in the solid-state imaging device 3B of the modification 3-2, the metal film 46 is provided to fill the inside of the recess 45U provided in the semiconductor substrate 411. Except for this, the configuration of the solid-state imaging device 3B is basically the same as the configuration of the solid-state imaging device 3 of the third embodiment described above. The material contained in the metal film 46 is different from the material contained in the metal film 51. Specifically, a metal material having a higher light-shielding property than the material contained in the metal film 51 (for example, copper), such as W (tungsten), can be used as the material contained in the metal film 46.

[0176] [Function and Effect of Solid-State Imaging Device 3B]

[0177] In the solid-state imaging device 3B of Modification 3-2, the concave portion 45U of the concavo-convex structure 45 is filled with the metal film 46, thereby reducing the amount of unnecessary light entering the sensor board 20. Therefore, the operational reliability of the solid-state imaging device 3B can be improved.

[0178] [Third Modification]

[0179] [Configuration of Solid-State Imaging Device 3C]

[0180] Fig. 15C is an enlarged cross-sectional view showing an example of a cross-sectional configuration of a portion of a solid-state imaging device 3C according to a third modification example (hereinafter referred to as modification example 3-3) of the present embodiment in an enlarged manner, and corresponds to a cross-sectional view showing a cross-sectional configuration example of a portion of a solid-state imaging device 3C according to the third modification example (hereinafter referred to as modification example 3-3) of the present embodiment. Fig.14 .

[0181] like Fig. 15C As shown, in the solid-state imaging device 3C of the modification 3-3, the metal film 46 is provided to fill the inside of the concave portion 45U provided in the semiconductor substrate 411 and to cover the convex portion 45T. Except for this, the configuration of the solid-state imaging device 3C is basically the same as the configuration of the solid-state imaging device 3 of the third embodiment described above.

[0182] [Function and Effect of Solid-State Imaging Device 3C]

[0183] In the solid-state imaging device 3C of Modification 3-3, the metal film 46 is provided to fill the inside of the concave portion 45U and cover the convex portion 45T, thereby being able to further reduce the amount of unnecessary light entering the sensor board 20 compared to the solid-state imaging device 3B of Modification 3-2. Therefore, the operational reliability of the solid-state imaging device 3B can be further improved.

[0184] [Fourth Modification]

[0185] [Structure of solid-state imaging device 3D]

[0186] Fig.15D is an enlarged cross-sectional view showing an example of a cross-sectional configuration of a portion of a solid-state imaging device 3D according to a fourth modification example (hereinafter referred to as modification example 3-4) of the present embodiment in an enlarged manner, and corresponds to the diagram showing a cross-sectional configuration example of a portion of a solid-state imaging device 3D according to the third embodiment described above. Fig.14 .

[0187] like Fig.15D As shown, in the solid-state imaging device 3D of the modification 3-4, two or more recesses 45U having different depths are formed in the semiconductor substrate 411. Specifically, in the solid-state imaging device 3D, the depth of the recess 45U at the position overlapping with the semiconductor element 43 along the Z-axis direction becomes relatively shallow, and the depth of the recess 45U at the position not overlapping with the semiconductor element 43 along the Z-axis direction becomes relatively deep. Except for this, the configuration of the solid-state imaging device 3D is basically the same as the configuration of the solid-state imaging device 3 of the third embodiment described above.

[0188] [Functions and effects of solid-state imaging device 3D]

[0189] The solid-state imaging device 3D of the modification 3-4 has, for example, the above-described configuration, which is different from the solid-state imaging device 3 ( Fig.14 ) further increases the surface area of ​​the logic board 41A compared to the solid-state imaging device 3D. Therefore, according to the solid-state imaging device 3D, the logic board 41A has a higher heat dissipation property and can more effectively release the heat of the logic board 41A or the sensor board 20 to the outside. Note that although Fig.15D An example of the case where the concave portion 45U has the gap AG is shown, but the inside of the concave portion 45U may be filled with the metal film 46. Furthermore, the metal film 46 may also be provided to cover the convex portion 45T.

[0190] [Fifth Modification]

[0191] Fig.16 Parts (A) to (F) are respectively plan schematic diagrams showing construction examples of corresponding ones of semiconductor substrates 411 (411A to 411F) of a logic board to be used in a solid-state imaging device of a fifth variant (hereinafter referred to as variant 3-5) of the present embodiment.

[0192] In the solid-state imaging device 3 according to the third embodiment, the front surface 41AFS of the semiconductor substrate 411 has the concavo-convex structure 45. Fig.16 As shown in parts (A) to (F) of the embodiment, in each semiconductor substrate 411 (411A to 41F) of the modification example 3-5, the end surface 41AT has a concavo-convex structure 47. The concavo-convex structure 47 includes a plurality of concave portions 47U and a plurality of convex portions 47T. The front surface 41AFS of each semiconductor substrate 411 (411A to 41F) may be a flat surface that has been subjected to a planarization process (e.g., CMP), or may have a concavo-convex structure 45.

[0193] Specifically, in Fig.16 The semiconductor substrate 411A shown in the portion (A) and the Fig.16 In the semiconductor substrate 411B shown in the portion (B) of FIG. 1 , a plurality of recesses 47U having a substantially triangular shape are formed on the end surface 41AT in a plan view. Note that all the recesses 47U in the semiconductor substrate 411A have substantially the same size and shape as each other. In contrast, among the recesses 47U in the semiconductor substrate 411B, the size of some recesses 47U is different from the size of other recesses 47U.

[0194] In addition, Fig.16 The semiconductor substrate 411C shown in the portion (C) Fig.16 The semiconductor substrate 411C shown in the portion (D) and Fig.16 In the semiconductor substrate 411F shown in the portion (F) of FIG. 1 , a plurality of substantially rectangular recesses 47U are formed on the end surface 41AT in a plan view. Fig.16 In the semiconductor substrate 411E shown in part (E), a plurality of substantially U-shaped recesses 47U are formed on the end surface 41AT in a plan view. As described above, the number, shape, size (length and width), arrangement position, etc. of the plurality of recesses 47U can be set as needed.

[0195] In the solid-state imaging device including the logic board 41A including any one of the semiconductor substrates 411 (411A to 411F) of Modifications 3 to 5, the end surface 41AT has the concavo-convex structure 47, thereby increasing the surface area of ​​the logic board 41A compared with the logic board 41 of the solid-state imaging device 1 according to the first embodiment, for example. Therefore, the logic board 41A has high heat dissipation, and the heat of the logic board 41A or the sensor board 20 can be effectively released to the outside.

[0196] [Sixth Modification]

[0197] Fig.17 Parts (A) to (D) of FIG. 1 are plan views showing examples of the construction of a corresponding one of semiconductor substrates 411 (411G to 411J) of a logic board to be used in a solid-state imaging device according to a sixth modification example (hereinafter referred to as modification example 3-6) of the present embodiment. Fig.17 As shown in parts (A) to (D) of FIG. 4 , the layout of the concave portion 45U and the convex portion 45T of the concave-convex structure 45 can be selected as needed.

[0198] [Seventh Modification]

[0199] Fig.18 Parts (A) to (F) of FIG. 1 are plan views showing examples of the construction of corresponding ones of semiconductor substrates 411 (411K to 411P) of a logic board to be used in a solid-state imaging device according to a seventh modification example (hereinafter referred to as modification example 3-7) of the present embodiment. Fig.18 As shown in parts (A) to (F) of the concave-convex structure 45, the shapes and positions of the concave portion 45U and the convex portion 45T can be selected as needed.

[0200] [7. Fourth embodiment]

[0201] [Configuration of Solid-State Imaging Device 4]

[0202] Fig.19 A configuration example of a solid-state imaging device 4 according to a fourth embodiment of the present invention is schematically shown. Fig.19 4 shows a cross-sectional configuration example of a solid-state imaging device 4, and corresponds to the cross-sectional configuration example of the solid-state imaging device 2 according to the second embodiment described above. Fig. 9A .

[0203] In the solid-state imaging device 2 according to the second embodiment described above, the cavity portion V is provided in the periphery of the logic board 41 and in the periphery of the heat sink 71 in the logic layer 40. In contrast, in the solid-state imaging device 4 according to the present embodiment, the cavity portion V is not provided, and the periphery of the logic board 41 and in the periphery of the heat sink 71 in the logic layer 40 is filled with the insulating layer 40Z. Except for this, the configuration of the solid-state imaging device 4 is substantially the same as that of the solid-state imaging device 2.

[0204] The solid-state imaging device 4 of the present embodiment is also provided with the heat dissipation plate 71 , whereby the heat of the logic board 41 or the sensor board 20 can be effectively released to the outside.

[0205] [8. Fifth embodiment]

[0206] [Configuration of Solid-State Imaging Device 5]

[0207] Fig. 20 A configuration example of a solid-state imaging device 5 according to a fifth embodiment of the present invention is schematically shown. Fig. 20 1 shows a cross-sectional configuration example of a solid-state imaging device 5, and corresponds to the cross-sectional configuration example of the solid-state imaging device 3 according to the third embodiment described above. Fig.13A .

[0208] In the solid-state imaging device 3 according to the third embodiment described above, a cavity V is provided in the periphery of the logic board 41A in the logic layer 40. In contrast, in the solid-state imaging device 5 according to the present embodiment, the cavity V is not provided, and the periphery of the logic board 41A in the logic layer 40 is filled with the insulating layer 40Z. Except for this, the configuration of the solid-state imaging device 5 is substantially the same as that of the solid-state imaging device 3.

[0209] In the solid-state imaging device 5 of the present embodiment, the logic board 41A has the concavo-convex structure 45 , whereby the heat of the logic board 41A or the sensor board 20 can be effectively released to the outside.

[0210] [9. Sixth embodiment: Application example on electronic device]

[0211] Fig.21 is a block diagram showing a configuration example of a camera 2000 as an electronic device to which the present technology is applied.

[0212] The camera 2000 includes an optical unit 2001 including a lens group, etc., an imaging device 2002 to which the above-mentioned solid-state imaging device 1, 1A, etc. (hereinafter referred to as the solid-state imaging device 1, etc.) is applied, and a digital signal processor (DSP: Digital Signal Processor) circuit 2003 as a camera signal processing circuit. In addition, the camera 2000 also includes a frame memory 2004, a display 2005, a recorder 2006, an operation unit 2007, and a power supply unit 2008. The DSP circuit 2003, the frame memory 2004, the display 2005, the recorder 2006, the operation unit 2007, and the power supply unit 2008 are connected to each other via a bus 2009.

[0213] The optical unit 2001 receives incident light (image light) from a subject and forms an image on an imaging plane of the imaging device 2002. The imaging device 2002 converts the light amount of the incident light forming an image on the imaging plane by the optical unit 2001 into an electrical signal in units of pixels and outputs the electrical signal as a pixel signal.

[0214] The display 2005 includes, for example, a panel display device such as a liquid crystal panel or an organic EL panel. The display 2005 displays, for example, a moving image or a still image captured by the imaging device 2002. The recorder 2006 records the moving image or the still image captured by the imaging device 2002 in a recording medium such as a hard disk or a semiconductor memory.

[0215] The operation unit 2007 outputs operation commands regarding various functions of the camera 2000 under the operation of the user. The power supply unit 2008 appropriately supplies various power supplies to the DSP circuit 2003, frame memory 2004, display 2005, recorder 2006 and operation unit 2007 for use as operation power supplies of each of these power supply targets.

[0216] As described above, by using the above-described solid-state imaging device 1 or the like as the imaging device 2002 , it can be expected that a favorable image can be acquired.

[0217] [10. Examples of practical applications on mobile objects]

[0218] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be implemented as a device installed on any type of mobile body, such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, and a robot.

[0219] Fig. 22 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present invention can be applied.

[0220] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig. 22 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown as a functional configuration of the integrated control unit 12050.

[0221] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 acts as a control device for the following devices: a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a vehicle braking force, etc.

[0222] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a portable device as a key substitute or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0223] The vehicle exterior information detection unit 12030 detects external information about the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform processing for detecting objects such as people, vehicles, obstacles, signs, characters on the road surface, or processing for detecting their distances.

[0224] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may also output an electrical signal as an image, or may output an electrical signal as measured distance information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0225] The in-vehicle information detection unit 12040 detects interior information about the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting a driver state. The driver state detection unit 12041 includes, for example, a camera for capturing an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0226] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside and outside of the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control of functions aimed at realizing an advanced driver assistance system (ADAS), including collision avoidance or shock absorption of the vehicle, following driving based on vehicle spacing, speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0227] In addition, based on the environmental information about the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc., which enables the vehicle to drive automatically without relying on the driver's operation, etc.

[0228] In addition, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the external information about the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control for preventing glare by, for example, controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0229] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig. 22In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0230] Fig.23 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0231] exist Fig.23 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0232] The imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, arranged at the front nose, rearview mirror, rear bumper, rear door, and upper portion of the windshield of the vehicle 12100. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper portion of the windshield of the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the rearview mirror mainly acquire images on both sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 arranged at the upper portion of the windshield of the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0233] Notice, Fig.23 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0234] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0235] For example, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and extract the nearest three-dimensional object as the preceding vehicle, which is particularly present on the driving path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in the substantially same direction as the vehicle 12100. In addition, the microcomputer 12051 is capable of presetting the following distance to be maintained in front of the preceding vehicle, and performing automatic braking control (including following stop control), automatic acceleration control (including following start control), etc. Therefore, it is possible to perform coordinated control for automatic driving so that the vehicle can travel automatically without relying on the operation of the driver, etc.

[0236] For example, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult to be visually identified by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0237] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following process: a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras; and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a square contour line for emphasis superimposed on the identified pedestrian. In addition, the sound / image output unit 12052 may control the display unit 12062 so as to display an icon or the like for indicating a pedestrian at a desired position.

[0238] The following describes an example of a vehicle control system to which the technology according to the present invention can be applied. The technology according to the present invention can be applied to the imaging unit 12031 among the above components. Specifically, Figure 1A The solid-state imaging device 1 shown in FIG. 1200 and the like can be applied to the imaging section 12031. By applying the technology according to the present invention to the imaging section 12031, excellent operation of the vehicle control system can be expected.

[0239] [11. Other Modifications]

[0240] Although the present invention has been described above with reference to the embodiment and its modifications, the present invention is not limited to the above-described embodiment, etc., but can be modified in various ways. The positions, sizes, shapes, etc. of the components described in the above-described embodiment, etc. can be set as needed.

[0241] In addition, in the above-mentioned embodiments and the like, the logic circuit and the memory circuit are regarded as examples of the signal processing circuit; however, the present invention is not limited thereto. The signal processing circuit according to the present invention includes, for example, one or more of a logic circuit, a memory circuit, a power supply circuit, an image signal compression circuit, a clock circuit, and an optical communication conversion circuit.

[0242] Note that the effects described herein are merely examples, and the description thereof is not restrictive. In addition, any other effects may be provided. In addition, the present technology may have the following configurations.

[0243] (1) An electronic device comprising:

[0244] First equipment board;

[0245] a second device board, the second device board being stacked on the first device board and electrically connected to the first device board, and the area of ​​the second device board being larger than the area of ​​the first device board;

[0246] A cavity portion surrounds at least a portion of a periphery of the first device board along a plane orthogonal to a stacking direction of the first device board and the second device board.

[0247] (2) The electronic device according to (1), wherein:

[0248] The electronic device comprises a plurality of the first device boards spaced apart from each other along the plane, and

[0249] The cavity portion is provided in at least a portion of the space between the plurality of first device boards.

[0250] (3) The electronic device according to (1) and (2), wherein the cavity portion communicates with the outside.

[0251] (4) The electronic device according to any one of (1) to (3), wherein at least a portion of the cavity portion is defined by a first metal film covering the first device board.

[0252] (5) The electronic device according to (4), wherein the first metal film continuously covers an end surface of the first device board and a surface of the first device board on the opposite side to the second device board.

[0253] (6) The electronic device according to (4), wherein the first metal film includes at least one of Al (aluminum), W (tungsten), and Cu (copper).

[0254] (7) The electronic device according to any one of (1) to (6), further comprising:

[0255] a support plate, which is disposed on the opposite side of the second device plate when viewed from the first device plate, and supports the first device plate via a second metal film, wherein:

[0256] At least a portion of the cavity portion is defined by the second metal film and the first metal film covering the first device board.

[0257] (8) The electronic device according to (7), wherein the first metal film and the second metal film are integrated with each other and constitute a metal frame.

[0258] (9) The electronic device according to (7) or (8), wherein the support plate includes a recessed portion that accommodates at least a portion of the first device board in a thickness direction.

[0259] (10) The electronic device according to any one of (7) to (9), wherein an inner surface of the recess is covered with the second metal film.

[0260] (11) The electronic device according to (9) or (10), wherein the cavity also exists between the first device board and the support board.

[0261] (12) An electronic device according to any one of (9) to (11), wherein the front surface covering portion of the first metal film covering the front surface of the first device board and the bottom surface covering portion of the second metal film covering the bottom surface of the hollow portion of the support board are in contact with each other.

[0262] (13) The electronic device according to any one of (1) to (12), further comprising:

[0263] An additional board is arranged along the plane to be adjacent to the first device board, and the cavity is between the additional board and the first device board.

[0264] (14) The electronic device according to any one of (1) to (13), wherein:

[0265] The second device board is a sensor board provided with an imaging element, the imaging element including a plurality of pixels and capable of generating a pixel signal for each of the pixels by receiving external light, and

[0266] The first device board is a circuit board including a signal processing circuit, and the signal processing circuit performs signal processing on the pixel signal.

[0267] (15) The electronic device according to (13) or (14), wherein the signal processing circuit includes at least one of a logic circuit, a memory circuit, a power supply circuit, an image signal compression circuit, a clock circuit, and an optical communication conversion circuit.

[0268] (16) The electronic device according to (1), further comprising:

[0269] The third equipment board, wherein

[0270] The third device board is disposed adjacent to the first device board along the plane orthogonal to the stacking direction and has an area smaller than that of the second device board.

[0271] (17) The electronic device according to (16), wherein thermal conductivity of the third device board is higher than thermal conductivity of the first device board.

[0272] (18) The electronic device according to (16) or (17), wherein thermal conductivity of the third device board is higher than thermal conductivity of the second device board.

[0273] (19) The electronic device according to any one of (16) to (18), wherein the third device board includes a metal layer extending along the plane orthogonal to the stacking direction.

[0274] (20) An electronic device according to any one of (16) to (19), wherein the third device board includes a metal layer extending along the plane orthogonal to the stacking direction and one or more fins upright on the metal layer.

[0275] (21) The electronic device according to any one of (16) to (19), wherein the third device board includes a cooling element.

[0276] (22) The electronic device according to (1), wherein at least a portion of a surface of the first device board other than a surface opposing the second device board has a concavo-convex structure.

[0277] (23) An electronic device according to (22), wherein the surface of the first device board having the concave-convex structure is the front surface on the opposite side of the relative surface, the end surface connecting the relative surface and the front surface, or both the front surface and the end surface.

[0278] (24) An electronic device according to (22) or (23), wherein the surface of the first device board having the concave-convex structure has an arithmetic mean roughness Ra value greater than 0.2 nm, or has a root mean square roughness Rms value greater than 0.25 nm.

[0279] (25) The electronic device according to any one of (22) to (24), wherein:

[0280] At least a portion of the cavity is defined by a first metal film covering the first device board, and

[0281] The first metal film continuously covers an end surface of the first device board and a front surface of the first device board on an opposite side of the second device board.

[0282] (26) The electronic device according to (25), further comprising:

[0283] A second metal film covers at least a portion of the front surface of the first device board.

[0284] (27) The electronic device according to (25), wherein a gap exists between the front surface of the first device board and the first metal film.

[0285] (28) The electronic device according to (22), wherein two or more recesses having different depths are formed on the front surface of the first device board on the opposite side of the opposing surface.

[0286] This application claims the benefit of Japanese Priority Patent Application JP2022-119066 filed in the Japan Patent Office on Jul. 26, 2022, the entire contents of which are incorporated herein by reference.

[0287] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may be made depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. An electronic device, comprising: First equipment board; a second device board, the second device board being stacked on the first device board and electrically connected to the first device board, and the area of ​​the second device board being larger than the area of ​​the first device board; A cavity portion surrounds at least a portion of a periphery of the first device board along a plane orthogonal to a stacking direction of the first device board and the second device board.

2. The electronic device according to claim 1, wherein: The electronic device comprises a plurality of the first device boards spaced apart from each other along the plane, and The cavity portion is provided in at least a portion of the space between the plurality of first device boards.

3. The electronic device according to claim 1, wherein: The cavity portion is communicated with the outside.

4. The electronic device according to claim 1, wherein: At least a portion of the cavity portion is defined by a first metal film covering the first device board.

5. The electronic device according to claim 4, wherein: The first metal film continuously covers an end surface of the first device board and a surface of the first device board on the opposite side to the second device board.

6. The electronic device according to claim 4, wherein: The first metal film includes at least one of Al (aluminum), W (tungsten), and Cu (copper).

7. The electronic device according to claim 1, further comprising: a support plate, which is disposed on the opposite side of the second device plate when viewed from the first device plate, and supports the first device plate via a second metal film, wherein: At least a portion of the cavity portion is defined by the second metal film and the first metal film covering the first device board.

8. The electronic device according to claim 7, wherein: The first metal film and the second metal film are integrated with each other and constitute a metal frame.

9. The electronic device according to claim 7, wherein: The support plate includes a recessed portion that accommodates at least a portion of the first device plate in a thickness direction.

10. The electronic device according to claim 9, wherein: The inner surface of the recess is covered with the second metal film.

11. The electronic device according to claim 9, wherein: The cavity also exists between the first device plate and the support plate.

12. The electronic device according to claim 9, wherein: A front surface covering portion of the first metal film covering the front surface of the first device board and a bottom surface covering portion of the second metal film covering the bottom surface of the cavity portion of the support board are in contact with each other.

13. The electronic device according to claim 1, further comprising: An additional board is arranged along the plane to be adjacent to the first device board, and the cavity is between the additional board and the first device board.

14. The electronic device according to claim 1, wherein: The second device board is a sensor board provided with an imaging element, the imaging element including a plurality of pixels and capable of generating a pixel signal for each of the pixels by receiving external light, and The first device board is a circuit board including a signal processing circuit, and the signal processing circuit performs signal processing on the pixel signal.

15. The electronic device according to claim 14, wherein: The signal processing circuit includes at least one of a logic circuit, a memory circuit, a power supply circuit, an image signal compression circuit, a clock circuit, and an optical communication conversion circuit.

16. The electronic device according to claim 1, further comprising: The third equipment board, wherein The third device board is disposed adjacent to the first device board along the plane orthogonal to the stacking direction, and an area of ​​the third device board is smaller than an area of ​​the second device board.

17. The electronic device according to claim 16, wherein: The thermal conductivity of the third device plate is higher than the thermal conductivity of the first device plate.

18. The electronic device according to claim 16, wherein: The thermal conductivity of the third device plate is higher than the thermal conductivity of the second device plate.

19. The electronic device according to claim 16, wherein: The third device board includes a metal layer extending along the plane orthogonal to the stacking direction.

20. The electronic device according to claim 16, wherein: The third device board includes a metal layer extending along the plane orthogonal to the stacking direction and one or more fins uprightly disposed on the metal layer.

21. The electronic device according to claim 16, wherein: The third equipment plate includes a cooling element.

22. The electronic device according to claim 1, wherein: At least a portion of a surface of the first device board that is different from a surface opposite to the second device board has a concavo-convex structure.

23. The electronic device according to claim 22, wherein: The surface of the first device board having the concavo-convex structure is a front surface on the opposite side of the opposing surface, an end surface connecting the opposing surface and the front surface, or both the front surface and the end surface.

24. The electronic device according to claim 22, wherein: The surface of the first device plate having the concavo-convex structure has an arithmetic mean roughness Ra value greater than 0.2 nm, or has a root mean square roughness Rms value greater than 0.25 nm.

25. The electronic device according to claim 22, wherein: At least a portion of the cavity is defined by a first metal film covering the first device board, and The first metal film continuously covers an end surface of the first device board and a front surface of the first device board on an opposite side of the second device board.

26. The electronic device according to claim 25, further comprising: A second metal film covers at least a portion of the front surface of the first device board.

27. The electronic device according to claim 25, wherein: There is a gap between the front surface of the first device board and the first metal film.

28. The electronic device according to claim 22, wherein: Two or more recesses having different depths are formed on the front surface of the first device board on the opposite side to the opposing surface.

Images