Wafer structure and manufacturing method of semiconductor device

Abstract

The wafer structure includes: a wafer having a first surface on one side and a second surface on the other side; a first electrode covering the first surface; a second electrode covering an inner portion of the second surface such that a peripheral portion of the second surface is exposed; and a protective tape which has the characteristic that the adhesion force with respect to the peripheral edge of the second surface is higher than the adhesion force with respect to the second electrode, and which is affixed to the peripheral edge of the second surface and the second electrode.

Description

Technical Field

[0001] This application claims priority based on Patent Application No. 2022-095664 filed in the Japan Patent Office on June 14, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a wafer structure and a method for manufacturing a semiconductor device. Background Art

[0002] Patent document 1 discloses a method for manufacturing a semiconductor device, which includes a process of forming a first electrode on a first main surface of a semiconductor wafer, a process of forming a second electrode covering the entire second main surface of the semiconductor wafer, a process of attaching a first tape to the entire second main surface in a manner covering the entire second electrode, a process of attaching a second tape to the entire end of the semiconductor wafer in a manner overlapping with the first tape, and a process of forming a plating layer on the first electrode in a state where the first tape and the second tape are attached.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent Application Publication No. 2022-0020628 Summary of the invention

[0006] Problems to be solved by the invention

[0007] One embodiment provides a wafer structure that contributes to manufacturing a semiconductor device with high reliability and a method for manufacturing a semiconductor device.

[0008] Solutions to Solve Problems

[0009] One embodiment provides a wafer structure, including: a wafer having a first surface on one side and a second surface on the other side; a first electrode covering the first surface; a second electrode covering the inner portion of the second surface in a manner that exposes the peripheral portion of the second surface; and a protective tape having a characteristic that a sealing force relative to the peripheral portion of the second surface is higher than a sealing force relative to the second electrode, and being adhered to the peripheral portion of the second surface and the second electrode.

[0010] One embodiment provides a method for manufacturing a semiconductor device, comprising the following steps: a step of preparing a wafer structure, the wafer structure comprising a wafer having a first surface on one side and a second surface on the other side, and a first electrode covering the above-mentioned first surface; a step of forming a second electrode, the second electrode covering the inner square portion of the above-mentioned second surface in a manner that exposes the peripheral portion of the above-mentioned second surface; and a step of attaching a protective tape to the above-mentioned peripheral portion of the above-mentioned second surface and the above-mentioned second electrode, the protective tape having a characteristic that a sealing force relative to the above-mentioned peripheral portion of the above-mentioned second surface is higher than a sealing force relative to the above-mentioned second electrode.

[0011] The above and other objects, features and effects will become more apparent from the following description of the embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a plan view of the wafer structure according to the first embodiment as viewed from the first main surface side.

[0013] Figure 2 is along Figure 1 A cross-sectional view along line II-II is shown.

[0014] Figure 3 yes Figure 1 A schematic cross-sectional view of the wafer structure shown.

[0015] Figure 4 Viewed from the second main surface Figure 1 A top view of the wafer structure is shown.

[0016] Figure 5 Yes means Figure 3 A top view of an example layout of the second electrode is shown.

[0017] Figure 6 is shown together with the second electrode of the first embodiment. Figure 1 An enlarged cross-sectional view of the peripheral portion of the wafer structure shown.

[0018] Fig. 7A is shown together with the second electrode of the second embodiment Figure 1 An enlarged cross-sectional view of the peripheral portion of the wafer structure shown.

[0019] Figure 7B is shown together with the second electrode of the third embodiment. Figure 1 An enlarged cross-sectional view of the peripheral portion of the wafer structure shown.

[0020] Fig. 8A Yes means Figure 1 A cross-sectional view of a method for manufacturing a semiconductor device having a wafer structure shown.

[0021] Figure 8B Yes means Fig. 8A A cross-sectional view of the subsequent process.

[0022] Figure 8C Yes means Figure 8B A cross-sectional view of the subsequent process.

[0023] Fig.8D Yes means Figure 8C A cross-sectional view of the subsequent process.

[0024] Fig. 8E Yes means Fig.8D A cross-sectional view of the subsequent process.

[0025] Fig.8F Yes means Fig. 8E A cross-sectional view of the subsequent process.

[0026] Figure 8G Yes means Figure 8F A cross-sectional view of the subsequent process.

[0027] Fig. 9A It is a cross-sectional view showing a step of forming the second electrode.

[0028] Fig. 9B Yes means Fig. 9A A cross-sectional view of the subsequent process.

[0029] Fig. 9C Yes means Fig. 9B A cross-sectional view of the subsequent process.

[0030] Fig.10 This is a plan view of the wafer structure according to the second embodiment as viewed from the first main surface side.

[0031] Fig.11 is along Fig.10 A cross-sectional view taken along line XI-XI is shown.

[0032] Fig.12 Yes means Fig.11 An enlarged cross-sectional view of the main parts of the functional device shown.

[0033] Fig.13 yes Fig.10 A schematic cross-sectional view of the wafer structure shown.

[0034] Fig.14A Yes means Fig.10 A cross-sectional view of a method for manufacturing a semiconductor device having a wafer structure shown.

[0035] Fig. 14B Yes means Fig.14A A cross-sectional view of the subsequent process.

[0036] Fig. 14C Yes means Fig. 14BA cross-sectional view of the subsequent process.

[0037] Fig.14D Yes means Fig. 14C A cross-sectional view of the subsequent process.

[0038] Fig.14E Yes means Fig.14D A cross-sectional view of the subsequent process.

[0039] Fig.14F Yes means Fig.14E A cross-sectional view of the subsequent process.

[0040] Figure 14G Yes means Fig.14F A cross-sectional view of the subsequent process.

[0041] Fig.15 1 is a top view of a wafer showing a modified example.

[0042] Fig.16 It is a schematic cross-sectional view showing a step of forming the second electrode according to the first modification.

[0043] Fig.17 It is a schematic cross-sectional view showing a step of forming the second electrode according to the second modification.

[0044] Fig.18 It is a schematic cross-sectional view showing a step of forming the second electrode according to the third modification. DETAILED DESCRIPTION

[0045] Hereinafter, the implementation mode will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, not strictly illustrated, and the scales, etc. may not be consistent. In addition, the same reference symbols are marked on the corresponding structures between the drawings, and repeated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions before the omission or simplification shall apply. In the implementation mode, although the words "first", "second", "third" and the like are used, these are symbols for the names of the structures to clarify the order of description, and are not intended to limit the meaning of the names of the structures to be given.

[0046] Figure 1 This is a plan view of the wafer structure 1A according to the first embodiment as viewed from the first main surface 3 side. Figure 2 is along Figure 1 A cross-sectional view along line II-II is shown. Figure 3 yes Figure 1 The schematic cross-sectional view of the wafer structure 1A is shown. Figure 4 When viewed from the second main surface 4 Figure 1 A top view of wafer structure 1A is shown. Figure 5 Yes means Figure 3 FIG. 2 is a top view of an example of the layout of the second electrode 24 shown.

[0047] Figure 6 It is shown together with the second electrode 24 of the first embodiment. Figure 1 FIG. 1 is an enlarged cross-sectional view of the peripheral portion of the wafer structure 1A shown. Fig. 7A It is shown together with the second electrode 24 of the second embodiment. Figure 1 FIG. 1 is an enlarged cross-sectional view of the peripheral portion of the wafer structure 1A shown. Figure 7B It is shown together with the second electrode 24 of the third embodiment. Figure 1 FIG. 1 is an enlarged cross-sectional view of the peripheral portion of the wafer structure 1A shown.

[0048] Reference Figure 1 to Figure 6 , the wafer structure 1A includes a wafer 2. In this method, the wafer 2 is formed into a flat disc shape. Of course, the wafer 2 can also be formed into a flat rectangular parallelepiped shape. In this method, the wafer 2 is composed of a semiconductor single crystal having a plating reaction speed slower than the plating reaction speed of a Si (silicon) single crystal. That is, the wafer 2 is composed of a semiconductor single crystal whose redox reaction speed is slower than that of a Si single crystal. The wafer 2 is particularly preferably composed of a semiconductor single crystal having a Ni plating reaction speed slower than that of a Si single crystal.

[0049] The wafer 2 is most preferably composed of a high-hardness semiconductor single crystal having a hardness higher than that of a Si single crystal. The wafer 2 is preferably composed of a wide-gap semiconductor wafer including a wide-gap semiconductor single crystal. That is, the wafer structure 1A is preferably a wide-gap semiconductor wafer structure. A wide-gap semiconductor is a semiconductor having a higher band gap than Si.

[0050] In this method, wafer 2 is composed of a SiC wafer containing a hexagonal SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor. That is, wafer structure 1A is a SiC wafer structure. Hexagonal SiC single crystals have multiple polycrystalline types including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals, etc. In this method, an example in which wafer 2 contains a 4H-SiC single crystal is shown, but wafer 2 may also contain a SiC single crystal composed of other polycrystalline types.

[0051] The wafer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and a side surface 5 connecting the first main surface 3 and the second main surface 4. Hereinafter, a direction along the first main surface 3 is referred to as a first direction X, a direction orthogonal to the first direction X along the first main surface 3 is referred to as a second direction Y, and a direction orthogonal to the first main surface 3 is referred to as a vertical direction Z. The first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. The first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0052] The first principal surface 3 and the second principal surface 4 face the c-plane of the SiC single crystal. Preferably, the first principal surface 3 faces the silicon surface of the SiC single crystal, and the second principal surface 4 faces the carbon surface of the SiC single crystal. The first principal surface 3 is a device forming surface, and the second principal surface 4 is a non-device forming surface. The second principal surface 4 is composed of a flat surface extending horizontally from the inner part along the peripheral part, and there is no step difference in the peripheral part. In this embodiment, the second principal surface 4 is composed of a polished surface having a plurality of polishing marks recessed toward the first principal surface 3. The depth of the polishing marks is preferably less than 0.5μm. The depth of the polishing marks is particularly preferably less than 0.1μm.

[0053] The first principal surface 3 and the second principal surface 4 may also have an offset angle tilted at a predetermined angle relative to the c-plane in a predetermined offset direction. That is, the c-axis of the SiC single crystal may also be tilted relative to the vertical direction Z by an offset angle. The offset direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The offset angle may also be greater than 0° and less than 10°. The offset angle is preferably less than 5°. The offset angle is particularly preferably greater than 2° and less than 4.5°.

[0054] The wafer 2 has a mark 6 indicating the crystal orientation of the SiC single crystal on the side 5. In this embodiment, the mark 6 includes an orientation plane cut out in a straight line when viewed from above (hereinafter referred to as "viewed from above") from the vertical direction Z. In this embodiment, the orientation plane extends in the second direction Y.

[0055] The orientation plane does not necessarily need to extend in the second direction Y, but may also extend in the first direction X. Of course, the mark 6 may also include a first orientation plane extending in the first direction X, and a first orientation plane extending in the second direction Y.

[0056] The wafer 2 may have a diameter of 50 mm to 300 mm (ie, 2 inches to 12 inches) in a plan view. The diameter of the wafer 2 is defined outside the mark 6 by the length of a chord passing through the center of the wafer 2 .

[0057] The wafer 2 is preferably composed of a thin wafer having a thickness of 30 μm or more and less than 200 μm. The wafer 2 may also be 30 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, or 175 μm or more and 200 μm or less. The thickness of the wafer 2 is preferably 160 μm or less.

[0058] In this embodiment, the wafer structure 1A includes an n-type first region 7 (first semiconductor region) formed in a region (surface portion) on the first main surface 3 side in the wafer 2. The first region 7 is formed in a layer extending along the first main surface 3 and exposed from the first main surface 3 and the side surface 5. In this embodiment, the first region 7 is composed of an epitaxial layer (SiC epitaxial layer). The first region 7 may also have a thickness of 1 μm or more and 50 μm or less. The thickness of the first region 7 is preferably 5 μm or more and 30 μm or less. The thickness of the first region 7 is particularly preferably 25 μm or less.

[0059] In this embodiment, the wafer structure 1A includes an n-type second region 8 (second semiconductor region) formed in a region (surface portion) on the second main surface 4 side in the wafer 2. The second region 8 has a higher n-type impurity concentration than the first region 7 and is electrically connected to the first region 7 in the wafer 2. The second region 8 is formed in a layer extending along the second main surface 4 and exposed from the second main surface 4 and the side surface 5. In this embodiment, the second region 8 is composed of a semiconductor substrate (SiC substrate). That is, the wafer 2 has a stacked structure including a substrate and an epitaxial layer.

[0060] The second region 8 may also have a thickness of 1 μm or more and less than 200 μm. The thickness of the second region 8 is preferably less than 160 μm. The thickness of the second region 8 is preferably 10 μm or more. The thickness of the second region 8 may also exceed the thickness of the first region 7. The thickness of the second region 8 may also be less than the thickness of the first region 7.

[0061] The wafer structure 1A includes a plurality of device regions 10 provided on the first main surface 3. Each device region 10 is a region corresponding to a semiconductor device (wide bandgap semiconductor device / SiC semiconductor device). The plurality of device regions 10 are respectively set to be quadrilateral in a plan view. In this embodiment, the plurality of device regions 10 are arranged in rows and columns along the first direction X and the second direction Y in a plan view.

[0062] The plurality of device areas 10 are arranged at intervals from the peripheral portion of the first main surface 3 to the inside in a plan view, and a space 11 where the plurality of device areas 10 do not exist is divided in the peripheral portion of the first main surface 3. That is, the wafer 2 includes an inner portion having the plurality of device areas 10 and a peripheral portion having no device area 10. The space 11 is formed in a ring shape surrounding the plurality of device areas 10 in a plan view. The space 11 has a portion extending in an arc shape in the area outside the mark 6 in a plan view, and has a portion extending in a straight line shape in the area along the mark 6.

[0063] The length of one side of each device area 10 may also be greater than 0.5 mm and less than 20 mm. The length of one side of each device area 10 is preferably greater than 1 mm. The length of one side of each device area 10 is particularly preferably greater than 2 mm. In this embodiment, the length of one side of each device area 10 is set to a range of greater than 4 mm and less than 6 mm.

[0064] The wafer structure 1A includes a plurality of planned cutting lines 12 provided on the first main surface 3. The plurality of planned cutting lines 12 are provided in a grid pattern extending in the first direction X and the second direction Y so as to partition the plurality of device regions 10.

[0065] The wafer structure 1A further includes functional devices 13 formed in each device region 10 on the first main surface 3. Each functional device 13 is formed with a gap inward from the periphery of each device region 10. Each functional device 13 may include at least one of a switching device, a rectifying device, and a passive device.

[0066] The switching device may also include at least one of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor). The rectifying device may also include at least one of a pn junction diode, a pin junction diode, a Zener diode, a SBD (Schottky Barrier Diode), and a FRD (Fast Recovery Diode). The passive device may also include at least one of a resistor, a capacitor, and a coil.

[0067] Each functional device 13 may also include a circuit network (e.g., an integrated circuit such as an LSI) formed by combining at least two of a switching device, a rectifier device, and a passive device. In this embodiment, each functional device 13 includes an SBD. Since the structures of multiple device areas 10 (functional devices 13) are the same, the structure of one device area 10 (functional device 13) is described below.

[0068] Reference Figure 5The wafer structure 1A includes an n-type diode region 14 formed in the surface layer portion of the first main surface 3 in the device region 10. In this embodiment, the diode region 14 is formed using the first region 7. The diode region 14 is formed with a gap inward from the periphery of the device region 10. The diode region 14 is formed in a polygonal shape (a quadrilateral shape in this embodiment) when viewed from above.

[0069] The wafer structure 1A includes a p-type (second conductivity type) protection region 15, which is formed on the surface of the first main surface 3 in the device region 10. The protection region 15 is formed on the surface of the first region 7 with a gap inward from the periphery of the device region 10. The protection region 15 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) surrounding the diode region 14 when viewed from above. The protection region 15 has an inner edge portion on the inner side of the device region 10 and an outer edge portion on the peripheral side of the device region 10.

[0070] The wafer structure 1A includes a main surface insulating film 16, which selectively covers the first main surface 3 in the device region 10. The main surface insulating film 16 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 16 has a single-layer structure including a silicon oxide film. The main surface insulating film 16 has a contact opening 17 that exposes the inner edge of the diode region 14 and the protection region 15.

[0071] The main surface insulating film 16 covers the inner part of the device area 10 with intervals from the periphery of the device area 10 to the inside, so that the first main surface 3 (first area 7) is exposed from the periphery of the device area 10. In other words, the main surface insulating film 16 exposes the boundary parts (multiple planned cutting lines 12) of the plurality of device areas 10. Of course, the main surface insulating film 16 may also cover the boundary parts (multiple planned cutting lines 12) of the plurality of device areas 10.

[0072] The wafer structure 1A includes a first electrode 18, which covers the first main surface 3 in the device region 10. In this embodiment, the first electrode 18 is formed as an anode electrode. The first electrode 18 is arranged inwardly from the periphery of the device region 10 with a gap. The first electrode 18 is formed in a polygonal shape (a quadrilateral shape in this embodiment) along the periphery of the device region 10 when viewed from above. The first electrode 18 enters the contact opening 17 from above the main surface insulating film 16 and is electrically connected to the inner edge of the diode region 14 and the protection region 15. Specifically, the first electrode 18 forms a Schottky junction with the diode region 14.

[0073] The first electrode 18 may also have a stacked structure including a Ti-based metal film and an Al-based metal film stacked in sequence from the first main surface 3 side. The Ti-based metal film may also include at least one of a Ti film and a Ti alloy film. The Al-based metal film is preferably thicker than the Ti-based metal film. The Al-based metal film includes at least one of an Al film and an Al alloy film. For example, the Al-based metal film may also include at least one of an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0074] The wafer structure 1A includes an insulating film 19 that covers the first electrode 18 in the device region 10. The insulating film 19 covers the peripheral portion of the first electrode 18 with a gap from the peripheral edge of the device region 10 to the inside. The insulating film 19 defines a pad opening 20 in the inner portion of the device region 10 and defines a scribe line opening 21 in the peripheral portion of the device region 10. The pad opening 20 exposes the inner portion of the first electrode 18. The pad opening 20 is formed in a polygonal shape (a quadrilateral shape in this embodiment) along the peripheral edge of the first electrode 18 when viewed from above.

[0075] The cut-way opening 21 extends along the periphery of the device area 10 to expose the first main surface 3. Specifically, the cut-way opening 21 divides the plurality of insulating films 19 adjacent in the first direction X and the second direction Y into a grid shape extending in the first direction X and the second direction Y, thereby exposing the boundary portions (plurality of predetermined cutting lines 12) of the plurality of device areas 10. Of course, in the case where the main surface insulating film 16 covering the first main surface 3 is formed in the boundary portions of the plurality of device areas 10, the cut-way opening 21 may also expose the main surface insulating film 16 in the boundary portions of the plurality of device areas 10.

[0076] The insulating film 19 is preferably thicker than the first electrode 18. The thickness of the insulating film 19 is preferably smaller than the thickness of the wafer 2. The thickness of the insulating film 19 may be 3 μm or more and 35 μm or less. The thickness of the insulating film 19 is preferably 25 μm or less.

[0077] In this embodiment, the insulating film 19 has a stacked structure including an inorganic insulating film 22 (inorganic film) and an organic insulating film 23 (organic film) stacked in order from the first electrode 18 side. The inorganic insulating film 22 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 22 preferably includes an insulating material different from that of the main surface insulating film 16. In this embodiment, the inorganic insulating film 22 has a single-layer structure including a silicon nitride film. The thickness of the inorganic insulating film 22 may also be greater than 0.1 μm and less than 5 μm.

[0078] The organic insulating film 23 is thicker than the inorganic insulating film 22 and covers the inorganic insulating film 22. The organic insulating film 23 is preferably composed of a photosensitive resin film. The organic insulating film 23 may also include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. The thickness of the organic insulating film 23 may also be greater than 3 μm and less than 30 μm. The thickness of the organic insulating film 23 is preferably less than 20 μm.

[0079] The organic insulating film 23 may expose one or both of the inner edge and the outer edge of the inorganic insulating film 22. In this embodiment, the organic insulating film 23 exposes both of the inner edge and the outer edge of the inorganic insulating film 22, and defines the inorganic insulating film 22, the pad opening 20, and the dicing street opening 21. Of course, the organic insulating film 23 may cover the entire region of the inorganic insulating film 22.

[0080] The wafer structure 1A includes a second electrode 24 covering the second main surface 4. In this embodiment, the second electrode 24 is formed as a cathode electrode and is electrically connected to the second region 8 exposed from the second main surface 4. The second electrode 24 has a plating reaction rate faster than the plating reaction rate of the wafer 2. That is, the second electrode 24 includes an electrode material having a faster redox reaction rate than the wafer 2.

[0081] The second electrode 24 exposes at least a portion of the peripheral portion of the wafer 2 as the plating reaction inhibitor 25. In other words, the plating reaction inhibitor 25 is an exposed portion of the second main surface 4 that is exposed from the second electrode 24. In this embodiment, the second electrode 24 exposes the entire periphery of the wafer 2 as the plating reaction inhibitor 25.

[0082] That is, the plating reaction inhibiting portion 25 exposes the SiC single crystal (in this embodiment, the carbon surface of the SiC single crystal) exposed from the peripheral portion of the second main surface 4. In addition, the plating reaction inhibiting portion 25 exposes the grinding marks formed on the peripheral portion of the second main surface 4. The portion of the second main surface 4 where the plating reaction inhibiting portion 25 is formed is formed on the same surface as the portion of the second main surface 4 hidden by the second electrode 24. That is, the plating reaction inhibiting portion 25 extends in the horizontal direction, and no step portion recessed toward the first main surface 3 is formed in the second main surface 4.

[0083] The plating reaction hindering portion 25 has a portion extending in an arc shape in the region outside the mark 6 in a plan view, and has a portion extending in a straight line in the region along the mark 6. The plating reaction hindering portion 25 is formed in a region outside the plurality of device regions 10 in a plan view, and is opposed to the space 11 in the thickness direction of the wafer 2. That is, the plating reaction hindering portion 25 is formed in a ring shape that surrounds the plurality of device regions 10 in a plan view.

[0084] The exposed width W of the plating reaction inhibitor 25 is preferably larger than the thickness of the second electrode 24. The exposed width W is preferably larger than the thickness of the first electrode 18. The exposed width W is preferably larger than the thickness of the insulating film 19. The exposed width W is particularly preferably larger than the thickness of the wafer 2.

[0085] The exposed width W may also be greater than 0.5 mm and less than 5 mm. The exposed width W is preferably greater than 1 mm and less than 2 mm. The exposed width W is particularly preferably less than the length of one side of the device area 10. According to this structure, the number of multiple device areas 10 (that is, the number of semiconductor devices) can be suppressed from being reduced due to the introduction of the plating reaction hindering portion 25.

[0086] The second electrode 24 may also include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film. The Al-based metal film may also include at least one of an Al film and an Al alloy film. For example, the Al-based metal film may also include at least one of an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0087] The Ti-based metal film may also include at least one of a Ti film and a Ti alloy film. The Ni-based metal film may also include at least one of a Ni film and a Ni alloy film. The Pd-based metal film may also include at least one of a Pd film and a Pd alloy film. The Au-based metal film may also include at least one of an Au film and an Au alloy film. The Ag-based metal film may also include at least one of an Ag film and an Ag alloy film.

[0088] Reference Figure 6 In this embodiment, the second electrode 24 has a stacked structure including a Ti film 31, a Ni film 32, and an Au film 33 stacked in sequence from the second main surface 4 side. The Ti film 31 directly covers the second main surface 4. In this embodiment, the Ti film 31 does not form a silicide (TiSi) layer in the surface portion of the second main surface 4. Of course, the Ti film 31 may also form a silicide layer in the surface portion of the second main surface 4. The Ti film 31 may also have Above and The following thickness.

[0089] The Ni film 32 is thicker than the Ti film 31 and covers the Ti film 31. The thickness of the Ni film 32 may be Above and The Au film 33 is thinner than the Ni film 32 and covers the Ni film 32. The thickness of the Au film 33 can also be Above and the following.

[0090] Reference Fig. 7AThe second electrode 24 may also have a stacked structure including an AlSi alloy film 34, a Ti film 35, a Ni film 36, and an Au film 37 stacked in sequence from the second main surface 4 side. The AlSi alloy film 34 directly covers the second main surface 4. In this embodiment, the AlSi alloy film 34 does not form a silicide (AlSi) layer in the surface portion of the second main surface 4. Of course, the AlSi alloy film 34 may also form a silicide layer in the surface portion of the second main surface 4. The AlSi alloy film 34 may also have Above and The following thickness.

[0091] The Ti film 35 is thinner than the AlSi alloy film 34 and covers the AlSi alloy film 34. The thickness of the Ti film 35 may be Above and The Ni film 36 is thicker than the Ti film 35 and covers the Ti film 35. The Ni film 36 may also have Above and The Au film 37 is thinner than the Ni film 36 and covers the Ni film 36. The Au film 37 may also have Above and The following thickness.

[0092] Reference Figure 7B The second electrode 24 may also have a stacked structure including a Ti film 38, a Ni film 39, an Au film 40, and an Ag film 41 stacked in sequence from the second main surface 4 side. The Ti film 38 directly covers the second main surface 4. In this embodiment, the Ti film 38 does not form a silicide (TiSi) layer in the surface portion of the second main surface 4. Of course, the Ti film 38 may also form a silicide layer in the surface portion of the second main surface 4. The Ti film 38 may also have Above and The following thickness.

[0093] The Ni film 39 is thicker than the Ti film 38 and covers the Ti film 38. The thickness of the Ni film 39 may be Above and The Au film 40 is thinner than the Ni film 39 and covers the Ni film 39. The thickness of the Au film 33 can also be Above and The Ag film 41 is thicker than the Au film 40 and covers the Au film 40. The thickness of the Ag film 41 may also be Above and the following.

[0094] The wafer structure 1A includes a protective tape 45, which is attached to the second electrode 24 of the wafer 2. The protective tape 45 may also be referred to as a "protective film", "support tape", "support film", etc. The protective tape 45 is preferably thicker than the second electrode 24. The thickness of the protective tape 45 is preferably greater than the thickness of the first electrode 18. The thickness of the protective tape 45 is preferably greater than the thickness of the insulating film 19. The thickness of the protective tape 45 is preferably less than the thickness of the wafer 2. Of course, the thickness of the protective tape 45 may also be greater than the thickness of the wafer 2.

[0095] The protective tape 45 includes a base film 46 and an adhesive layer 47. The base film 46 is composed of an optically transparent organic film. The base film 46 preferably has a planar shape corresponding to the planar shape of the wafer 2. In this embodiment, the base film 46 is formed into a circular shape when viewed from above. In the case of a rectangular parallelepiped wafer 2, the base film 46 is preferably formed into a quadrilateral shape when viewed from above.

[0096] The base film 46 is preferably thicker than the second electrode 24. The thickness of the base film 46 is preferably greater than the thickness of the first electrode 18. The thickness of the base film 46 is preferably greater than the thickness of the insulating film 19. The thickness of the base film 46 is preferably less than the thickness of the wafer 2. Of course, the thickness of the base film 46 may be greater than the thickness of the wafer 2. The thickness of the base film 46 may also be greater than 10 μm and less than 100 μm. The thickness of the base film 46 is preferably greater than 20 μm and less than 50 μm.

[0097] The adhesive layer 47 is provided on one side of the base film 46. The adhesive layer 47 is preferably provided on the entire one side of the base film 46. The adhesive layer 47 is preferably thicker than the second electrode 24. The thickness of the adhesive layer 47 is preferably greater than the thickness of the first electrode 18.

[0098] The thickness of the adhesive layer 47 is preferably greater than the thickness of the insulating film 19. The thickness of the adhesive layer 47 is preferably less than the thickness of the wafer 2. Of course, the thickness of the adhesive layer 47 may be greater than the thickness of the wafer 2. The thickness of the adhesive layer 47 is preferably greater than 10 μm and less than 100 μm. The thickness of the adhesive layer 47 is preferably greater than 20 μm and less than 50 μm.

[0099] The adhesive layer 47 may also include, for example, a photocurable adhesive whose adhesive force decreases by irradiation with ultraviolet rays. The adhesive layer 47 has a characteristic that the adhesive force (adhesive strength) with respect to the wafer 2 is higher than the adhesive force (adhesive strength) with respect to the second electrode 24. That is, the protective tape 45 has a characteristic that the adhesive force with respect to the plating reaction inhibiting portion 25 (the peripheral portion of the second main surface 4) is higher than the adhesive force with respect to the second electrode 24.

[0100] The adhesive strength of the protective tape 45 (adhesive layer 47) to the wafer 2 is preferably greater than 14.1N / 25mm. For example, the adhesive strength of the protective tape 45 to the SiC wafer is preferably greater than 14.4N / 25mm. The adhesive strength of the protective tape 45 to the second electrode 24 is greater than 8N / 25mm and less than 14N / 25mm. For example, the adhesive strength of the protective tape 45 to the Au film 33 is about 8.9N / 25mm. For example, the adhesive strength of the protective tape 45 to the Ag film 41 is about 10N / 25mm.

[0101] The protective tape 45 is adhered to the second electrode 24 and the plating reaction inhibiting portion 25 (the peripheral portion of the second main surface 4) by the adhesive layer 47 and is attached to the second main surface 4 side of the wafer 2. The protective tape 45 covers the entire area of ​​the second electrode 24 and extends in a film-like manner from the second electrode 24 to the plating reaction inhibiting portion 25. In this embodiment, the protective tape 45 covers the plating reaction inhibiting portion 25 over the entire circumference of the peripheral portion of the wafer 2.

[0102] That is, the protective tape 45 covers the SiC single crystal (in this embodiment, the carbon surface of the SiC single crystal) exposed as the plating reaction inhibitor 25. In addition, the protective tape 45 covers the polishing marks formed in the plating reaction inhibitor 25. In this case, the adhesive layer 47 preferably fills the polishing marks.

[0103] According to this structure, the bonding area of ​​the protective tape 45 (adhesive layer 47) with respect to the plating reaction inhibiting portion 25 (the peripheral portion of the second main surface 4) is increased due to the grinding marks. Therefore, the adhesion of the protective tape 45 with respect to the plating reaction inhibiting portion 25 (the peripheral portion of the second main surface 4) is increased. That is, the grinding marks also function as anchor holes with respect to the protective tape 45.

[0104] The adhesive portion of the protective tape 45 relative to the plating reaction inhibitor 25 has a portion extending in an arc shape in the area outside the mark 6 when viewed from above, and has a portion extending in a straight line in the area along the mark 6. Specifically, the adhesive portion of the protective tape 45 is formed in the area outside the plurality of device areas 10 when viewed from above, and is opposite to the space 11 via the wafer 2. That is, the adhesive portion of the protective tape 45 is formed in a ring shape that surrounds the plurality of device areas 10 together when viewed from above.

[0105] The protective tape 45 may also form a gap 48 between the second main surface 4 and the edge of the second electrode 24. That is, the protective tape 45 may also be attached to the second electrode 24 and the plating reaction inhibitor 25 in such a way that the edge of the second electrode 24 is exposed. The gap 48 may also be formed in a part or the entire circumference of the edge of the second electrode 24. Of course, the protective tape 45 may also cover the edge of the second electrode 24 in a part or the entire circumference of the edge of the second electrode 24 in such a way that the gap 48 is not formed.

[0106] The edge of the protective tape 45 has a portion extending in an arc shape in the area outside the mark 6 and a portion extending in a straight line in the area along the mark 6 when viewed from above. The protective tape 45 preferably extends from the area on the second main surface 4 to the area outside the second main surface 4 in the horizontal direction. According to this structure, the entire area of ​​the second main surface 4 can be hidden by the protective tape 45. In this case, the portion of the adhesive layer 47 covering the peripheral edge of the base film 46 can also be exposed from the wafer 2.

[0107] The protective tape 45 preferably exposes the side surface 5 of the wafer 2. The protective tape 45 particularly preferably exposes the entire side surface 5. The protective tape 45 exposing the entire side surface 5 means that the base film 46 is not attached to the side surface 5 of the wafer 2 via the adhesive layer 47. Therefore, in a structure in which a part of the adhesive layer 47 overlaps with the lower end of the side surface 5, when the base film 46 is not opposed to the side surface 5 via the adhesive layer 47, the protective tape 45 exposes the entire side surface 5.

[0108] The extension width Wo of the protective tape 45 may be larger than the thickness of the wafer 2. The extension width Wo may be larger than the thickness of the second electrode 24. The extension width Wo may be larger than the thickness of the first electrode 18. The extension width Wo may be larger than the thickness of the insulating film 19. The extension width Wo is preferably smaller than the exposed width W of the plating reaction inhibitor 25. The extension width Wo may be greater than 0.1 mm and less than 2 mm. The extension width Wo is preferably greater than 0.5 mm and less than 1 mm.

[0109] Figure 8A to Figure 8F It is a cross-sectional view showing a method for manufacturing the semiconductor device SD1. Figures 9A to 9C It is a cross-sectional view showing a step of forming the second electrode 24 . Figure 8A to Figure 8F (Figure 9F~ Fig. 9C ) is also part of the manufacturing process of wafer structure 1A.

[0110] Reference Fig. 8A First, a wafer structure 1A before the step of forming the second electrode 24 is prepared. The wafer structure 1A includes a diode region 14, a protection region 15, a main surface insulating film 16, a first electrode 18, and an insulating film 19 in each device region 10. The wafer structure 1A before the step of forming the second electrode 24 includes a wafer 2 having a thickness of 200 μm or more. The wafer 2 may also have a thickness of 200 μm or more and 1000 μm or less. The wafer 2 preferably has a thickness of 250 μm or more and 500 μm or less.

[0111] Next, refer to Figure 8B, a thinning process of the wafer 2 is performed. The wafer 2 may also be thinned from the second main surface 4 side by at least one of a grinding method and an etching method. In this method, the wafer 2 is thinned by a grinding method relative to the second main surface 4. In this method, the wafer 2 is ground to a thickness of less than 200 μm. Thus, grinding marks are formed on the second main surface 4 while the wafer 2 is thinned.

[0112] Next, refer to Figure 8C , the step of forming the second electrode 24 is performed. Fig. 9A In this process, a mask jig 50 is prepared as a mask for the peripheral portion of the second main surface 4. The mask jig 50 may be made of inorganic materials such as metal (e.g., stainless steel), glass, and ceramics, or may be made of organic materials such as resin. The mask jig 50 is configured to cover at least a portion of the peripheral portion of the second main surface 4, exposing the inner portion of the second main surface 4.

[0113] That is, the mask jig 50 is configured to cover the area of ​​the peripheral portion of the second main surface 4 to be formed as the plating reaction inhibitor 25. In this embodiment, the mask jig 50 is configured to be annular (specifically, circular) in a plan view in such a manner that the mask jig 50 covers the entire periphery of the second main surface 4 and exposes the inner portion of the second main surface 4.

[0114] The mask jig 50 has a portion extending in an arc shape in a region outside the mark 6 in a plan view, and has a portion extending in a linear shape in a region along the mark 6. The mask jig 50 is preferably thicker than the second electrode 24 to be formed.

[0115] Next, refer to Fig. 9B , the mask fixture 50 abuts against the peripheral portion of the second main surface 4. The mask fixture 50 abuts against the SiC single crystal (in this embodiment, the carbon surface of the SiC single crystal) exposed from the peripheral portion of the second main surface 4. The mask fixture 50 is arranged in an area outside the plurality of device areas 10 when viewed from above, and is opposite to the space 11 across the wafer 2. That is, the plating reaction hindering portion 25 is arranged to surround the plurality of device areas 10 together when viewed from above. The covering width (abutting width) of the mask fixture 50 relative to the peripheral portion of the second main surface 4 is equivalent to the exposed width W of the plating reaction hindering portion 25.

[0116] Next, in a state where the mask holder 50 is in contact with the second main surface 4, the second electrode 24 is deposited on the second main surface 4 and the mask holder 50 by sputtering. The thickness of the second electrode 24 is smaller than the thickness of the mask holder 50. The second electrode 24 may also include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film.

[0117] The Al-based metal film, Ti-based metal film, Ni-based metal film, Pd-based metal film, Au-based metal film, and Ag-based metal film can be formed by sputtering. Figure 6 , Fig. 7A as well as Figure 7B ) is formed by appropriately adjusting the film formation order of these metal films.

[0118] Next, refer to Fig. 9C The mask jig 50 is removed from the second main surface 4 . Thus, the portion of the second electrode 24 covering the mask jig 50 is also removed, and a plating reaction inhibitor 25 having a layout corresponding to the layout of the mask jig 50 is formed on the periphery of the second main surface 4 .

[0119] Next, refer to Fig.8D The protective tape 45 is attached to the second electrode 24 and the plating reaction inhibitor 25 (the peripheral edge of the second main surface 4). Figure 1 to Figure 6 The wafer structure 1A is shown. The wafer structure 1A is conveyed in a state where the protective tape 45 is attached thereto.

[0120] Next, refer to Fig. 8E , a plating film 51 is formed on the first electrode 18 by a plating method. The plating film 51 can also be regarded as a component of the wafer structure 1A. In this process, the entire wafer structure 1A is immersed in the plating solution, and the plating film 51 is formed on the first electrode 18. This process may also include a process of swinging the wafer structure 1A in the plating solution. The swinging process includes a stirring process for diffusing bubbles generated by the plating reaction in the liquid. According to this process, the poor film formation of the plating film 51 caused by bubbles can be suppressed.

[0121] In the case of a wafer 2 having a thickness of less than 200 μm, the wafer 2 is deformed by the stress from the plating solution during the swinging process. The protective tape 45 protects the second electrode 24 from the plating solution and suppresses the deformation of the wafer 2 in the plating solution. Thus, abnormal film formation of the plating film 51 relative to the second electrode 24 is suppressed, and cracks in the wafer 2 are suppressed.

[0122] Furthermore, the second electrode 24 exposes the peripheral portion of the second main surface 4, and the protective tape 45 covers the peripheral portion of the second main surface 4. In this structure, the protective tape 45 has a characteristic that the adhesion force with respect to the peripheral portion of the second main surface 4 is higher than the adhesion force with respect to the second electrode 24. According to this structure, peeling of the protective tape 45 in the peripheral portion of the second main surface 4 can be suppressed.

[0123] Thus, abnormal plating film formation on the second electrode 24 caused by peeling of the protective tape 45 is suppressed. In addition, since the adhesion of the protective tape 45 to the peripheral portion of the second main surface 4 is improved, it is possible to suppress the intrusion of the plating solution into the area between the second main surface 4 and the protective tape 45. Thus, abnormal plating film formation on the second electrode 24 can be suppressed.

[0124] Furthermore, the peripheral edge of the second main surface 4 is exposed as a plating reaction inhibitor 25 whose reaction speed is slow relative to the plating solution. In the plating reaction inhibitor 25, the formation of the plated film 51 is inhibited. Therefore, even if the plating solution intrudes into the area between the second main surface 4 and the protective tape 45, the plating reaction inhibitor 25 can suppress abnormal plating film formation.

[0125] In this method, the process of forming the plated film 51 includes the process of forming the Ni plated film 52, the Pd plated film 53 and the Au plated film 54 in order from the first electrode 18 side. The process of forming the Ni plated film 52 includes the process of forming the Ni plated film 52 on the first electrode 18 by electroless plating. The process of forming the Ni plated film 52 includes the process of immersing the wafer structure 1A in the Ni plating solution. In addition, the process of forming the Ni plated film 52 includes the process of swinging the wafer structure 1A in the Ni plating solution.

[0126] The peripheral portion of the second main surface 4 is preferably exposed as a plating reaction inhibitor 25 having a slow reaction rate at least with respect to the Ni plating solution. By suppressing abnormal film formation of the Ni plating film 52 on the second main surface 4 side, abnormal film formation of the Pd plating film 53 and the Au plating film 54 on the second main surface 4 side can also be suppressed in subsequent steps.

[0127] The Ni plating film 52 is preferably thicker than the inorganic insulating film 22. In this case, the Ni plating film 52 is preferably formed on the first electrode 18 in the pad opening 20 so as to jump over the edge of the inorganic insulating film 22. The Ni plating film 52 is preferably formed with a gap in the vertical direction Z from the opening end of the pad opening 20 toward the first electrode 18 side.

[0128] In this embodiment, the Ni plated film 52 covers the first electrode 18 and the inorganic insulating film 22 in the pad opening 20 and is in contact with the organic insulating film 23. Of course, the Ni plated film 52 may be formed in the pad opening 20 with a gap from the organic insulating film 23 and covers the edge of the first electrode 18 and the inorganic insulating film 22.

[0129] The Ni plating film 52 may have a thickness of 0.1 μm to 15 μm. The thickness of the Ni plating film 52 may be 0.1 μm to 1 μm, 1 μm to 3 μm, 3 μm to 6 μm, 6 μm to 9 μm, 9 μm to 12 μm, or 12 μm to 15 μm. The thickness of the Ni plating film 52 is preferably 2 μm to 8 μm.

[0130] The step of forming the Pd plated film 53 includes a step of forming the Pd plated film 53 on the Ni plated film 52 by electroless plating. The step of forming the Pd plated film 53 includes a step of immersing the wafer structure 1A in a Pd plating solution. In addition, the step of forming the Pd plated film 53 includes a step of swinging the wafer structure 1A in the Pd plating solution.

[0131] The peripheral portion of the second main surface 4 is preferably exposed as a plating reaction inhibitor 25 having a slow reaction rate with respect to the Pd plating solution. By suppressing abnormal film formation of the Pd plating film 53 on the second main surface 4 side, abnormal film formation of the Au plating film 54 on the second main surface 4 side can also be suppressed in subsequent steps.

[0132] The Pd plated film 53 is formed in a film shape along the outer surface of the Ni plated film 52. The Pd plated film 53 is preferably formed with a gap from the opening end of the pad opening 20 to the Ni plated film 52 side. The Pd plated film 53 is in contact with the organic insulating film 23 in the pad opening 20 in the vertical direction Z. Of course, in the case where the Ni plated film 52 is separated from the organic insulating film 23, the Pd plated film 53 may cover the Ni plated film 52 with a gap from the organic insulating film 23. In this case, the Pd plated film 53 may also cover the edge of the inorganic insulating film 22.

[0133] The Pd plating film 53 preferably has a thickness smaller than that of the Ni plating film 52. The thickness of the Pd plating film 53 may be 0.01 μm to 1 μm. The thickness of the Pd plating film 53 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0134] The step of forming the Au plating film 54 includes a step of forming the Au plating film 54 on the Pd plating film 53 by an electroless plating method. The step of forming the Au plating film 54 includes a step of immersing the wafer structure 1A in the Au plating solution. In addition, the step of forming the Au plating film 54 includes a step of swinging the wafer structure 1A in the Au plating solution. The peripheral portion of the second main surface 4 is preferably exposed as a plating reaction hindering portion 25 whose reaction speed is slow relative to the Au plating solution.

[0135] The Au plated film 54 is formed in a film shape along the outer surface of the Pd plated film 53. The Au plated film 54 is preferably formed with a gap from the opening end of the pad opening 20 to the Pd plated film 53 side in the vertical direction Z. The Au plated film 54 is in contact with the organic insulating film 23 in the pad opening 20. Of course, in the case where the Ni plated film 52 and the Pd plated film 53 are separated from the organic insulating film 23, the Au plated film 54 may also cover the Pd plated film 53 with a gap from the organic insulating film 23. In this case, the Au plated film 54 may also cover the edge of the inorganic insulating film 22.

[0136] The Au plating film 54 preferably has a thickness smaller than that of the Ni plating film 52. The thickness of the Au plating film 54 may be 0.01 μm to 1 μm. The thickness of the Au plating film 54 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0137] In this embodiment, an example is shown in which the plated film 51 includes the Ni plated film 52, the Pd plated film 53, and the Au plated film 54. However, the plated film 51 may have a laminated structure including only the Ni plated film 52 and the Au plated film 54 laminated in order from the first electrode 18 side. Of course, the plated film 51 may also have a single-layer structure consisting of the Ni plated film 52, the Pd plated film 53, or the Au plated film 54.

[0138] Next, refer to Figure 8F , the protective tape 45 is peeled off from the second main surface 4 and the second electrode 24. This process includes irradiating the adhesive layer 47 of the protective tape 45 with ultraviolet rays to reduce the adhesive force of the adhesive layer 47. In addition, this process includes peeling the base film 46 from the second electrode 24 together with the adhesive layer 47.

[0139] Next, refer to Figure 8G, the wafer 2 is cut along a plurality of predetermined cutting lines 12. The wafer 2 can be cut (cut) along the vertical direction Z by a dicing blade, or can be cut (cleaved) along the vertical direction Z by a cleaving method using a laser irradiation process. In the cleaving method, a modified layer in which a part of the crystal structure is modified is formed inside the wafer 2 by laser irradiation, and the wafer 2 is cleaved along the vertical direction Z with the modified layer as the starting point. Through the processes including the above description, a semiconductor device SD1 (in this method, a SiC semiconductor device) is manufactured.

[0140] As described above, the wafer structure 1A includes a wafer 2, a first electrode 18, a second electrode 24, and a protective tape 45. The wafer 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The first electrode 18 covers the first main surface 3. The second electrode 24 covers the inner part of the second main surface 4 in a manner that the peripheral portion of the second main surface 4 is exposed. The protective tape 45 is attached to the peripheral portion of the second main surface 4 and the second electrode 24. The protective tape 45 has a characteristic that the adhesion force to the peripheral portion of the second main surface 4 is higher than the adhesion force to the second electrode 24.

[0141] According to this structure, it is possible to suppress the peeling of the protective tape 45 from the second main surface 4 and the second electrode 24. Thus, when the wafer structure 1A is applied to the manufacturing method of the semiconductor device SD1, it is possible to suppress manufacturing defects caused by the peeling of the protective tape 45. Therefore, it is possible to provide a wafer structure 1A that helps to manufacture a semiconductor device SD1 with high reliability. For example, when the wafer structure 1A is immersed in a plating solution, it is possible to suppress the intrusion of the plating solution into the area between the second main surface 4 and the protective tape 45. Thus, abnormal film formation due to plating relative to the second electrode 24 can be suppressed.

[0142] When the second electrode 24 has a higher plating reaction speed than the wafer 2, the second electrode 24 preferably exposes the periphery of the wafer 2 as a plating reaction inhibitor 25. That is, the periphery of the wafer 2 is preferably made of a material that inhibits plating film formation.

[0143] In this case, the protective tape 45 is preferably attached to the plating reaction inhibiting portion 25. According to this structure, it is possible to suppress the plating solution from invading the region between the plating reaction inhibiting portion 25 and the protective tape 45. In addition, even if the plating solution intrudes into the region between the second main surface 4 and the protective tape 45, the plating reaction inhibiting portion 25 can suppress abnormal film formation.

[0144] The wafer 2 preferably includes a SiC single crystal. In this case, the second electrode 24 preferably exposes the SiC single crystal from the peripheral portion of the second main surface 4. In addition, the protective tape 45 is preferably attached to the SiC single crystal in the peripheral portion of the second main surface 4. The SiC single crystal has a physical property that makes it difficult to precipitate metal by plating. Therefore, even if the plating solution intrudes into the area between the second main surface 4 and the protective tape 45, abnormal film formation by plating can be suppressed by the SiC single crystal.

[0145] The wafer 2 preferably has a thickness of less than 200 μm. According to this structure, the on-resistance caused by the thickness of the wafer 2 can be reduced. In addition, according to the protective tape 45, the wafer 2 can be conveyed while suppressing deformation of the relatively thin wafer 2.

[0146] The second electrode 24 is preferably exposed over the entire periphery of the second main surface 4. In this case, the protective tape 45 is preferably attached to the entire periphery of the second main surface 4. According to this structure, it is possible to suppress the peeling of the protective tape 45 from the second main surface 4 over the entire periphery of the second main surface 4. In addition, it is possible to suppress the intrusion of the plating solution into the area between the second main surface 4 and the protective tape 45 over the entire periphery of the second main surface 4.

[0147] The exposed width W of the plating reaction inhibitor 25 (the peripheral edge of the second main surface 4) is preferably larger than the thickness of the second electrode 24. The exposed width W is preferably larger than the thickness of the wafer 2. With these structures, the risk of the plating solution contacting the second electrode 24 can be appropriately reduced.

[0148] The second main surface 4 preferably has grinding marks. In this case, the second electrode 24 preferably exposes the grinding marks in the peripheral portion of the second main surface 4. In addition, the protective tape 45 is preferably attached to the peripheral portion having the grinding marks. According to this structure, the adhesion of the protective tape 45 to the peripheral portion of the second main surface 4 can be improved by the grinding marks.

[0149] The second main surface 4 is preferably a flat surface. That is, the second main surface 4 preferably has no stepped portion that is recessed toward the first main surface 3. According to this structure, it is possible to appropriately suppress the formation of a fragile portion of the wafer 2 in the second main surface 4. In particular, this structure is preferably applied to a wafer 2 of less than 200 μm.

[0150] The wafer structure 1A may include a plating film 51 covering the first electrode 18. In this case, the second electrode 24 preferably exposes the peripheral edge of the wafer 2 as a plating reaction inhibitor 25 that inhibits the formation of the plating film 51. The plating film 51 may include at least one of a Ni plating film 52, a Pd plating film 53, and an Au plating film 54.

[0151] The wafer structure 1A may include a plurality of device regions 10 set in the inner portion of the first main surface 3. In this case, the second electrode 24 preferably exposes regions outside the plurality of device regions 10 in a plan view. With this configuration, the semiconductor device SD1 including the second electrode 24 can be appropriately manufactured.

[0152] From another perspective, the manufacturing method of the semiconductor device SD1 includes a preparation step of a wafer structure 1A, a formation step of a second electrode 24, and a bonding step of a protective tape 45. In the preparation step of the wafer structure 1A, a wafer structure 1A is prepared, which includes a wafer 2 having a first surface on one side and a second main surface 4 on the other side, and a first electrode 18 covering the first surface.

[0153] In the step of forming the second electrode 24, the second electrode 24 is formed so as to cover the inner portion of the second main surface 4 in such a manner that the peripheral portion of the second main surface 4 is exposed. In the step of attaching the protective tape 45, the protective tape 45 having a property that the adhesion force to the peripheral portion of the second main surface 4 is higher than the adhesion force to the second electrode 24 is attached to the peripheral portion of the second main surface 4 and the second electrode 24.

[0154] According to this manufacturing method, it is possible to suppress the peeling of the protective tape 45 from the second main surface 4 and the second electrode 24. Thus, it is possible to suppress manufacturing defects caused by the peeling of the protective tape 45. Therefore, it is possible to provide a manufacturing method that helps to manufacture a semiconductor device SD1 with high reliability. For example, when the wafer 2 is immersed in the plating solution in a state where the protective tape 45 is attached, it is possible to suppress the intrusion of the plating solution into the area between the second main surface 4 and the protective tape 45. Thus, it is possible to suppress abnormal film formation due to plating relative to the second electrode 24.

[0155] When the second electrode 24 has a higher plating reaction speed than the wafer 2, the second electrode 24 preferably exposes the periphery of the wafer 2 as a plating reaction inhibitor 25. That is, the periphery of the wafer 2 is preferably made of a material that inhibits plating film formation.

[0156] In this case, the protective tape 45 is preferably attached to the plating reaction inhibiting portion 25. According to this manufacturing method, it is possible to suppress the plating solution from invading the region between the plating reaction inhibiting portion 25 and the protective tape 45. In addition, even if the plating solution intrudes into the region between the second main surface 4 and the protective tape 45, the plating reaction inhibiting portion 25 can suppress abnormal film formation.

[0157] The method for manufacturing the semiconductor device SD1 preferably further includes the step of immersing the wafer structure 1A in a plating solution in a state where the protective tape 45 is attached, and forming a plating film 51 on the first electrode 18. According to this manufacturing method, it is possible to suppress the plating solution from invading the area between the second main surface 4 and the protective tape 45. Thus, it is possible to suppress abnormal film formation due to plating with respect to the second electrode 24.

[0158] The step of forming the plating film 51 preferably includes a step of swinging the wafer structure 1A in the plating solution. According to this manufacturing method, bubbles generated by the plating reaction can be diffused into the liquid. Thus, poor film formation of the plating film 51 caused by bubbles can be suppressed. In addition, according to this manufacturing method, the second electrode 24 can be protected from the plating solution by the protective tape 45, and the deformation of the wafer 2 in the plating solution can be suppressed by the protective tape 45.

[0159] This suppresses abnormal film formation of the plating film 51 relative to the second electrode 24 and suppresses cracks in the wafer 2. In particular, a relatively thin wafer 2 of less than 200 μm is easily deformed by stress from the plating solution during the swinging process, but the protective tape 45 can appropriately suppress deformation of the relatively thin wafer 2.

[0160] The step of forming the plating film 51 may also include at least one of a step of immersing the wafer structure 1A in a Ni plating solution to form a Ni plating film 52, a step of immersing the wafer structure 1A in a Pd plating solution to form a Pd plating film 53, and a step of immersing the wafer structure 1A in an Au plating solution to form an Au plating film 54. According to this manufacturing method, at least one of abnormal film formation of the Ni plating film 52, abnormal film formation of the Pd plating film 53, and abnormal film formation of the Au plating film 54 on the second main surface 4 side can be suppressed by the protective tape 45.

[0161] The wafer 2 preferably includes a SiC single crystal. In this case, the second electrode 24 is preferably formed so that the SiC single crystal is exposed from the peripheral portion of the second main surface 4. In addition, the protective tape 45 is preferably attached to the SiC single crystal in the peripheral portion of the second main surface 4. The SiC single crystal has a physical property that it is difficult to precipitate metal by plating. Therefore, even if the plating solution intrudes into the area between the second main surface 4 and the protective tape 45, abnormal film formation by plating can be suppressed by the SiC single crystal.

[0162] In the step of preparing the wafer structure 1A, the wafer structure 1A including the wafer 2 having a thickness of 200 μm or more is preferably prepared. In this case, the method of manufacturing the semiconductor device SD1 preferably includes a step of thinning the wafer 2 to a thickness of less than 200 μm before forming the second electrode 24 .

[0163] According to this manufacturing method, the wafer 2 can be conveyed while suppressing deformation of the wafer 2 using a relatively thick wafer 2 until the thinning step of the wafer 2. In addition, in the thinning step of the wafer 2, the on-resistance caused by the thickness of the wafer 2 can be reduced. Furthermore, after the step of attaching the protective tape 45, the wafer 2 can be conveyed while suppressing deformation of the relatively thin wafer 2 using the protective tape 45.

[0164] The thinning process of the wafer 2 may also include a process of grinding the entire surface of the second main surface 4 by a grinding method. In this case, the second electrode 24 is preferably formed so that the grinding marks are exposed in the peripheral portion of the second main surface 4. In addition, the protective tape 45 is preferably attached to the peripheral portion having the grinding marks. According to this manufacturing method, the adhesion of the protective tape 45 to the peripheral portion of the second main surface 4 can be improved by the grinding marks.

[0165] Fig.10 This is a plan view of the wafer structure 1B according to the second embodiment as viewed from the first main surface 3 side. Fig.11 is along Fig.10 A cross-sectional view taken along line XI-XI is shown. Fig.12 Yes means Fig.11 An enlarged cross-sectional view of the main parts of the functional device 13 is shown. Fig.13 yes Fig.10 The schematic cross-sectional view of the wafer structure 1B is shown.

[0166] Reference Figure 10 to Figure 12 The wafer structure 1B has a different structure from the above-mentioned wafer structure 1A in that the functional device 13 includes a MISFET instead of an SBD. Fig.11 In FIG. 1 , the functional device 13 is shown in simplified form by a dotted line.

[0167] In this embodiment, the MISFET is a trench gate type. The other structures in the wafer structure 1B are substantially the same as those in the wafer structure 1A. The following describes the differences between the wafer structure 1B and the wafer structure 1A. In addition, the following describes the structure of one device region 10.

[0168] The wafer structure 1B includes a p-type body region 60, which is formed on the surface of the first main surface 3 in the device region 10. The body region 60 is formed with a gap from the bottom of the first region 7 toward the first main surface 3, and extends in a layered manner on the surface of the first main surface 3. The body region 60 may also be formed on the entire first main surface 3.

[0169] The wafer structure 1B includes an n-type source region 61 formed in the surface portion of the body region 60 in the device region 10. The source region 61 may be formed in the inner portion of the device region 10 at a distance from the periphery of the device region 10. The source region 61 has a higher n-type impurity concentration than the first region 7. The source region 61 is formed at a distance from the bottom of the body region 60 toward the first main surface 3, and extends in a layered manner on the surface portion of the first main surface 3. The source region 61 forms a channel with the first region 7 in the body region 60.

[0170] The wafer structure 1B includes a plurality of first trench structures 62, which are formed on the first main surface 3 in the device area 10. The first trench structure 62 can also be called a "trench gate structure". The plurality of first trench structures 62 control the inversion and non-inversion of the channel. The plurality of first trench structures 62 penetrate the main region 60 and the source region 61 to reach the first region 7. The plurality of first trench structures 62 can also be arranged at intervals in the first direction X when viewed from above, and are respectively formed into strips extending in the second direction Y. The plurality of first trench structures 62 are formed at intervals from the bottom of the first region 7 to the side of the first main surface 3.

[0171] Each first trench structure 62 includes a first trench 63, a first insulating film 64, and a first embedded electrode 65. The first trench 63 is formed in the first main surface 3, and defines the wall surface of the first trench 63. The first insulating film 64 covers the wall surface of the first trench 63. The first embedded electrode 65 is embedded in the first trench 63 via the first insulating film 64. The first embedded electrode 65 is opposite to the channel via the first insulating film 64.

[0172] The wafer structure 1B includes a plurality of second trench structures 66 formed in the first main surface 3 in the device region 10. The second trench structures 66 may also be referred to as “trench source structures.” The plurality of second trench structures 66 are formed in the region between two adjacent first trench structures 62, respectively.

[0173] The plurality of second trench structures 66 may be formed in a strip shape extending in the second direction Y in a plan view. The plurality of second trench structures 66 penetrate the body region 60 and the source region 61 to reach the first region 7. The plurality of second trench structures 66 are formed at intervals from the bottom of the first region 7 toward the first main surface 3 and are formed deeper than the first trench structures 62.

[0174] Each second trench structure 66 includes a second trench 67, a second insulating film 68, and a second embedded electrode 69. The second trench 67 is formed in the first main surface 3 to define the wall surface of the second trench 67. The second insulating film 68 covers the wall surface of the second trench 67. The second embedded electrode 69 is embedded in the second trench 67 via the second insulating film 68.

[0175] The wafer structure 1B includes a plurality of p-type contact regions 70, which are formed in the device region 10 and in the wafer 2 in regions along the plurality of second trench structures 66. The plurality of contact regions 70 have a higher p-type impurity concentration than the body region 60. Each contact region 70 covers the sidewalls and bottom wall of each second trench structure 66 and is electrically connected to the body region 60.

[0176] The wafer structure 1B includes a plurality of p-type well regions 71, which are formed in the device region 10 and in the wafer 2 in regions along the plurality of second trench structures 66. Each well region 71 has a p-type impurity concentration higher than that of the body region 60 and lower than that of the contact region 70. Each well region 71 covers the corresponding second trench structure 66 via the corresponding contact region 70. Each well region 71 covers the sidewalls and bottom wall of the corresponding second trench structure 66 and is electrically connected to the body region 60.

[0177] The wafer structure 1B includes a main surface insulating film 16, which covers the first main surface 3 in the device area 10. The main surface insulating film 16 is connected to the first insulating film 64 and the second insulating film 68, so that the first buried electrode 65 and the second buried electrode 69 are exposed. In this embodiment, the main surface insulating film 16 covers the peripheral portion of the device area 10 (the boundary portion of multiple device areas 10). In other words, the main surface insulating film 16 covers the entire area of ​​the first main surface 3. Of course, the main surface insulating film 16 can also expose the peripheral portion of the device area 10 (the boundary portion of multiple device areas 10).

[0178] The wafer structure 1B includes an interlayer insulating film 72 that covers the main surface insulating film 16 in the device region 10. The interlayer insulating film 72 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon nitride oxide film. The interlayer insulating film 72 covers the plurality of first trench structures 62 and the plurality of second trench structures 66.

[0179] In this embodiment, the interlayer insulating film 72 covers the peripheral portion of the device region 10 (the boundary portion of the plurality of device regions 10) via the main surface insulating film 16. The interlayer insulating film 72 may also cover the entire first main surface 3. Of course, in the case where the main surface insulating film 16 exposes the first main surface 3 in the peripheral portion of the device region 10, the interlayer insulating film 72 may also expose the first main surface 3 in the peripheral portion of the device region 10.

[0180] As in the first embodiment, the wafer structure 1B includes the first embedded electrode 65 disposed on the interlayer insulating film 72 in the device region 10. The first electrode 18 may have a stacked structure including a Ti-based metal film and an Al-based metal film stacked in order from the first main surface 3 side.

[0181] In this embodiment, the first electrode 18 includes a gate electrode 73 and a source electrode 74. In this embodiment, the gate electrode 73 is arranged in a region close to the center of one side of the device region 10 in a plan view. The gate electrode 73 may be arranged in a corner of the device region 10 in a plan view. In this embodiment, the gate electrode 73 is formed in a quadrilateral shape in a plan view.

[0182] The source electrode 74 is disposed on the interlayer insulating film 72 at a distance from the gate electrode 73. In this embodiment, the source electrode 74 is formed in a polygonal shape having a concave portion along the gate electrode 73 when viewed from above. Of course, the source electrode 74 may also be formed in a quadrilateral shape when viewed from above. The source electrode 74 penetrates the interlayer insulating film 72 and the main surface insulating film 16, and is electrically connected to the body region 60, the source region 61, and the plurality of second trench structures 66.

[0183] The wafer structure 1B includes a gate wiring electrode 75, which is drawn from the gate electrode 73 to the interlayer insulating film 72 in the device region 10. The gate wiring electrode 75, like the gate electrode 73 (first electrode 18), may also have a stacked structure including a Ti-based metal film and an Al-based metal film stacked in sequence from the first main surface 3. The gate wiring electrode 75 is formed in a strip shape extending along the periphery of the device region 10 in a manner that intersects (specifically, is orthogonal to) the ends of the plurality of first trench structures 62 when viewed from above. The gate wiring electrode 75 penetrates the interlayer insulating film 72 and is electrically connected to the plurality of first trench structures 62.

[0184] The wafer structure 1B includes an insulating film 19 that covers the first electrode 18 in the device region 10. As in the first embodiment, the insulating film 19 has a laminated structure including an inorganic insulating film 22 and an organic insulating film 23 that are laminated in order from the first electrode 18 side. In this embodiment, the insulating film 19 covers the periphery of the gate electrode 73 and the periphery of the source electrode 74 with a gap inward from the periphery of the device region 10. The insulating film 19 covers the entire region of the gate wiring electrode 75.

[0185] The insulating film 19 defines a plurality of pad openings 20 for exposing the inner portion of the gate electrode 73 and the inner portion of the source electrode 74, and defines a scribe line opening 21 for exposing the interlayer insulating film 72 in the peripheral portion of the device region 10. In this embodiment, the plurality of pad openings 20 include a gate pad opening 76 for exposing the inner portion of the gate electrode 73, and a source pad opening 77 for exposing the inner portion of the source electrode 74.

[0186] In this embodiment, gate pad opening 76 is divided into a quadrilateral shape along the periphery of gate electrode 73 in a plan view. In this embodiment, source pad opening 77 is formed into a polygonal shape along the periphery of source electrode 74 in a plan view. Slice opening 21 is formed in the same manner as in the first embodiment.

[0187] The organic insulating film 23 may expose the edge of the inorganic insulating film 22 in the gate pad opening 76. The organic insulating film 23 may expose the edge of the inorganic insulating film 22 in the source pad opening 77. The organic insulating film 23 may expose the edge of the inorganic insulating film 22 in the scribe line opening 21. Of course, the organic insulating film 23 may cover the entire region of the inorganic insulating film 22.

[0188] The wafer structure 1B includes a second electrode 24 covering the second main surface 4. In this embodiment, the second electrode 24 is formed as a drain electrode and is electrically connected to the second region 8 exposed from the second main surface 4. The second electrode 24 is formed in the same manner as in the first embodiment. The other descriptions of the second electrode 24 apply to the descriptions of the first embodiment.

[0189] Figures 14A to 14G Yes means Fig.10 2 is a cross-sectional view of a method for manufacturing a semiconductor device SD2 having a wafer structure 1B shown. Figures 14A to 14G It is also a part of the manufacturing process of the wafer structure 1B.

[0190] Reference Fig.14A First, a wafer structure 1B before the step of forming the second electrode 24 is prepared. The wafer structure 1B includes a main region 60, a source region 61, a first trench structure 62, a second trench structure 66, a contact region 70, a well region 71, a main surface insulating film 16, an interlayer insulating film 72, a gate electrode 73 (first electrode 18), a source electrode 74 (first electrode 18), a gate wiring electrode 75, and an insulating film 19 in each device region 10. The wafer structure 1A before the step of forming the second electrode 24 includes a wafer 2 having a thickness of 200 μm or more. The wafer 2 may also have a thickness of 200 μm or more and 1000 μm or less. The wafer 2 preferably has a thickness of 250 μm or more and 500 μm or less.

[0191] Next, refer to Fig. 14B , a thinning process of the wafer 2 is performed. The wafer 2 may also be thinned from the second main surface 4 side by at least one of a grinding method and an etching method. In this method, the wafer 2 is thinned by a grinding method relative to the second main surface 4. In this method, the wafer 2 is ground to a thickness of less than 200 μm. Thus, grinding marks are formed on the second main surface 4.

[0192] Next, refer to Fig. 14C, the second electrode 24 is formed. The second electrode 24 is formed by the same process as described above. Figures 9A to 9C Thus, the plating reaction inhibiting portion 25 having a layout corresponding to the layout of the mask jig 50 is formed on the peripheral portion of the second main surface 4 .

[0193] Next, refer to Fig.14D A protective tape 45 is attached to the second electrode 24 and the plating reaction inhibitor 25 (the peripheral edge of the second main surface 4). Figure 10 to Figure 13 The wafer structure 1B is shown. The wafer structure 1B is conveyed in a state where the protective tape 45 is attached thereto.

[0194] Next, refer to Fig.14E , a plating film 51 is formed on the first electrode 18 by a plating method. In this method, the step of forming the plating film 51 includes a step of forming a gate plating film 78 on the gate electrode 73 and a step of forming a source plating film 79. The plating film 51 (gate plating film 78 and source plating film 79) can also be regarded as a component of the wafer structure 1B.

[0195] As in the case of the first embodiment, the step of forming the plating film 51 includes the step of forming the Ni plating film 52, the Pd plating film 53, and the Au plating film 54 in order from the side of the first electrode 18. The Ni plating film 52, the Pd plating film 53, and the Au plating film 54 are formed in the pad opening 20 (the gate pad opening 76 and the source pad opening 77) in the same manner as in the case of the first embodiment.

[0196] Of course, the plated film 51 may have a laminated structure including only the Ni plated film 52 and the Au plated film 54 laminated in order from the first electrode 18. Alternatively, the plated film 51 may have a single-layer structure including the Ni plated film 52, the Pd plated film 53 or the Au plated film 54.

[0197] Next, refer to Fig.14F , the protective tape 45 is peeled off from the second main surface 4 and the second electrode 24. This step includes the step of irradiating the adhesive layer 47 of the protective tape 45 with ultraviolet rays to reduce the adhesive force of the adhesive layer 47. In addition, this step includes the step of peeling the base film 46 from the second electrode 24 together with the adhesive layer 47.

[0198] Next, refer to Figure 14G , the wafer 2 is cut along a plurality of predetermined cutting lines 12. The wafer 2 can be cut (cut) by a dicing blade or cut (cleaved) by a cleaving method using a laser irradiation process. Through the above-described processes, a semiconductor device SD2 (in this embodiment, a SiC semiconductor device) is manufactured.

[0199] The wafer structure 1B also achieves the same effects as those described for the wafer structure 1A. In addition, the method for manufacturing the semiconductor device SD2 of the wafer structure 1B also achieves the same effects as those described for the method for manufacturing the semiconductor device SD2 of the wafer structure 1A.

[0200] Fig.15 FIG. 2 is a top view of a wafer 2 according to a modification of each of the above-mentioned embodiments. The mark 6 of the wafer 2 according to each of the above-mentioned embodiments includes an orientation flat surface. Fig.15 The mark 6 of the wafer 2 of the modified example includes an orientation notch that is recessed in a tapered shape (a cone shape or a triangle shape) toward the center of the first main surface 3 in the side surface 5 .

[0201] The orientation notch may also be recessed in the first direction X or the second direction Y (a-axis direction or m-axis direction) when viewed from above. Of course, the mark 6 may also include a first orientation notch recessed in the first direction X and a first orientation notch recessed in the second direction Y. In addition, the mark 6 may also include at least one orientation plane and at least one orientation notch.

[0202] The second electrode 24 does not need to have a portion extending in a straight line along the directional notch. The second electrode 24 covers the second main surface 4 with a gap inward from the directional notch in a manner that the directional notch is exposed. The second electrode 24 may also expose the peripheral portion of the second main surface 4 in a circular ring shape. That is, the plating reaction hindering portion 25 may also expose the peripheral portion of the second main surface 4 in a circular ring shape in the area along the mark 6 and the area outside the mark 6.

[0203] The edge of the protective tape 45 does not need to have a portion extending linearly along the orientation notch. The edge of the protective tape 45 may be formed in a circular shape over the entire periphery of the second main surface 4 in a plan view.

[0204] Fig.16 It is a schematic cross-sectional view showing a process of forming the second electrode 24 according to the first modified example to which the above-described embodiments are applied. Fig.17 It is a schematic cross-sectional view showing a process of forming the second electrode 24 according to the second modified example applied to each of the above-mentioned embodiments. Fig.18 1 is a schematic cross-sectional view showing a step of forming the second electrode 24 according to the third modified example to which the above-described embodiments are applied. In the above-described embodiments, the step of forming the second electrode 24 using the mask jig 50 is described.

[0205] However, refer to Fig.16The second electrode 24 may also be formed on the second main surface 4 by a lift-off method. In this case, a resist mask 81 is formed on the second main surface 4 instead of the mask jig 50, and the resist mask 81 may be removed after the second electrode 24 is formed. Considering the man-hour and the load on the wafer 2, the process using the mask jig 50 is preferred.

[0206] Of course, refer to Fig.17 , the second electrode 24 may also be formed in a predetermined layout by etching. In this case, after forming the second electrode 24 on the second main surface 4, a resist mask 82 of a predetermined layout is formed on the second electrode 24, and the second electrode 24 is formed in a predetermined layout by etching through the resist mask 82. After removing unnecessary portions of the second electrode 24, the resist mask 82 is removed. Considering the man-hours and the load on the wafer 2, the process using the mask jig 50 is preferred.

[0207] In addition, refer to Fig.18 , the second electrode 24 can also be formed in a predetermined layout by a grinding method. In this case, the unnecessary part of the second electrode 24 is removed by a slope grinding method on the peripheral portion of the second electrode 24 (the peripheral portion of the second main surface 4). In this case, a part of the wafer 2 can also be removed together with a part of the second electrode 24. That is, the plating reaction hindering portion 25 can also have a step portion 83 dug down toward the first main surface 3 in the peripheral portion of the second main surface 4. If the working hours and the load on the wafer 2 are considered, the process using the mask fixture 50 is preferred.

[0208] The above embodiments have been described, but each embodiment may also be implemented in other ways. For example, in the thinning process of the wafer 2 in each of the above embodiments, the second region 8 may be removed until the thickness becomes smaller than the thickness of the first region 7. Of course, in the thinning process of the wafer 2 in each of the above embodiments, the entire second region 8 may be removed. That is, a wafer 2 having a single-layer structure consisting of the first region 7 (SiC epitaxial layer) may also be formed.

[0209] In these cases, in the step of attaching the protective tape 45, the protective tape 45 having a thickness greater than that of the wafer 2 may be attached to the second main surface 4. In the case where a member for reinforcing or supporting the wafer 2 is provided on the first main surface 3, the protective tape 45 having a thickness less than that of the wafer 2 may be attached to the second main surface 4.

[0210] In the above-mentioned embodiments, an example is shown in which the functional device 13 includes either an SBD or a MISFET. However, the functional device 13 may include both an SBD and a MISFET. That is, both the SBD and the MISFET may be formed in the same device region 10. Of course, in the above-mentioned embodiments, the functional device 13 including the SBD and the functional device 13 including the MISFET may be formed in different device regions 10 in the same wafer 2.

[0211] In the second embodiment described above, an example in which a trench gate type MISFET is formed as an example of the functional device 13 is described. However, the functional device 13 may include a planar gate type MISFET instead of the trench gate type.

[0212] In the above-mentioned second embodiment, a p-type second region 8 may be used instead of an n-type second region 8. In this case, the functional device 13 includes an IGBT (Insulated Gate Bipolar Transistor) instead of a MISFET. The specific structure of this case can be obtained by replacing the "source" of the MISFET with the "emitter" of the IGBT and replacing the "drain" of the MISFET with the "collector" of the IGBT in the above description.

[0213] In the above embodiments, the structure in which the first conductivity type is n-type and the second conductivity type is p-type is described. However, in the above embodiments, the structure in which the first conductivity type is p-type and the second conductivity type is n-type may also be adopted. The specific structure of this case can be obtained by replacing the n-type region with the p-type region and the p-type region with the n-type region in the above description and the accompanying drawings.

[0214] The following are examples of features extracted from the specification and the accompanying drawings. The following numbers, etc. indicate corresponding components in the above-mentioned embodiments, and do not limit the scope of each item (Clause) to the embodiment. The "wafer structure" in the following items can also be replaced with "wide bandgap semiconductor wafer structure", "SiC wafer structure", etc. as needed. In addition, the "semiconductor device" in the following items can also be replaced with "wide bandgap semiconductor device", "SiC semiconductor device", etc. as necessary.

[0215] [A1] A wafer structure 1A, 1B, comprising: a wafer 2 having a first surface 3 on one side and a second surface 4 on the other side; a first electrode 18, which covers the above-mentioned first surface 3; a second electrode 24, which covers the inner square portion of the above-mentioned second surface 4 in a manner that exposes the peripheral portion of the above-mentioned second surface 4; and a protective tape 45, which has a characteristic that the sealing force relative to the above-mentioned peripheral portion of the above-mentioned second surface 4 is higher than the sealing force relative to the above-mentioned second electrode 24, and is adhered to the above-mentioned peripheral portion of the above-mentioned second surface 4 and the above-mentioned second electrode 24.

[0216] [A2] According to the wafer structures 1A and 1B described in A1, the second electrode 24 has a plating reaction rate higher than the plating reaction rate of the wafer 2, so that the peripheral portion of the wafer 2 is exposed as a plating reaction inhibitory portion 25, and the protective tape 45 is adhered to the plating reaction inhibitory portion 25.

[0217] [A3] According to the wafer structure 1A, 1B described in A1 or A2, the wafer 2 includes a SiC single crystal, the second electrode 24 exposes the SiC single crystal from the peripheral portion of the second surface 4, and the protective tape 45 is adhered to the SiC single crystal in the peripheral portion of the second surface 4.

[0218] [A4] The wafer structure 1A or 1B according to any one of A1 to A3, wherein the wafer 2 has a thickness of less than 200 μm.

[0219] [A5] According to the wafer structure 1A or 1B described in any one of A1 to A4, the second electrode 24 is exposed along the entire circumference of the peripheral portion, and the protective tape 45 is attached to the entire circumference of the peripheral portion.

[0220] [A6] The wafer structure 1A or 1B according to any one of A1 to A5, wherein the exposed width W of the peripheral portion is larger than the thickness of the second electrode 24 .

[0221] [A7] According to the wafer structures 1A and 1B described in A6, the exposed width W is larger than the thickness of the wafer 2.

[0222] [A8] According to the wafer structure 1A, 1B described in any one of A1 to A7, the wafer 2 has the second surface 4, the second surface 4 has grinding marks, the second electrode 24 exposes the peripheral portion having the grinding marks, and the protective tape 45 is adhered to the peripheral portion having the grinding marks.

[0223] [A9] According to the wafer structure 1A or 1B described in any one of A1 to A8, the second surface 4 is composed of a flat surface.

[0224] [A10] The wafer structure 1A or 1B according to any one of A1 to A9, further including a plating film 51 covering the first electrode 18 .

[0225] [A11] According to the wafer structures 1A and 1B described in A10, the plating film 51 includes at least one of the Ni plating film 52, the Pd plating film 53 and the Au plating film 54.

[0226] [A12] The wafer structure 1A or 1B according to any one of A1 to A11 further includes a plurality of device areas 10, wherein the plurality of device areas 10 are set in the inner portion of the first surface 3, and the second electrode 24 exposes areas outside the plurality of device areas 10 when viewed from above.

[0227] [A13] A method for manufacturing a semiconductor device SD1, SD2, comprising the following steps: a step of preparing a wafer structure 1A, 1B, wherein the wafer structure 1A, 1B includes a wafer 2 having a first surface 3 on one side and a second surface 4 on the other side, and a first electrode 18 covering the above-mentioned first surface 3; a step of forming a second electrode 24, wherein the second electrode 24 covers the inner portion of the above-mentioned second surface 4 in a manner that exposes the peripheral portion of the above-mentioned second surface 4; and a step of attaching a protective tape 45 to the above-mentioned peripheral portion of the above-mentioned second surface 4 and the above-mentioned second electrode 24, wherein the protective tape 45 has a characteristic that the sealing force relative to the above-mentioned peripheral portion of the above-mentioned second surface 4 is higher than the sealing force relative to the above-mentioned second electrode 24.

[0228] [A14] According to the method for manufacturing semiconductor devices SD1 and SD2 described in A13, the second electrode 24 has a plating reaction rate higher than the plating reaction rate of the wafer 2, so that the peripheral edge portion of the wafer 2 is exposed as a plating reaction inhibitory portion 25.

[0229] [A15] The method for manufacturing the semiconductor device SD1 or SD2 according to A13 or A14 further includes the following step: immersing the wafer structure 1A or 1B in a plating solution in a state where the protective tape 45 is attached thereto, and forming a plating film 51 on the first electrode 18.

[0230] [A16] According to the method for manufacturing the semiconductor devices SD1 and SD2 described in A15, the step of forming the plating film 51 includes the step of causing the wafer structures 1A and 1B to oscillate in the plating solution.

[0231] [A17] According to the manufacturing method of the semiconductor device SD1, SD2 described in A15 or A16, the process of forming the above-mentioned plating film 51 includes at least one process of immersing the above-mentioned wafer structure 1A, 1B in a Ni plating solution to form a Ni plating film 52, immersing the above-mentioned wafer structure 1A, 1B in a Pd plating solution to form a Pd plating film 53, and immersing the above-mentioned wafer structure 1A, 1B in an Au plating solution to form an Au plating film 54.

[0232] [A18] According to the manufacturing method of the semiconductor device SD1, SD2 recorded in any one of A13 to A17, the above-mentioned wafer 2 includes a SiC single crystal, the above-mentioned second electrode 24 makes the above-mentioned SiC single crystal exposed from the above-mentioned peripheral portion of the above-mentioned second surface 4, and the above-mentioned protective tape 45 is adhered to the above-mentioned SiC single crystal in the above-mentioned peripheral portion of the above-mentioned second surface 4.

[0233] [A19] The manufacturing method of the semiconductor device SD1, SD2 described in any one of A13 to A18 further includes the following steps: a step of preparing the above-mentioned wafer structure 1A, 1B, wherein the above-mentioned wafer structure 1A, 1B includes the above-mentioned wafer 2 having a thickness of more than 200μm; and a step of thinning the above-mentioned wafer 2 to a thickness of less than 200μm before the step of forming the above-mentioned second electrode 24.

[0234] [A20] According to the method for manufacturing the semiconductor devices SD1 and SD2 described in A19, the step of thinning the wafer 2 includes a step of grinding the second surface 4 by a grinding method.

[0235] The embodiments are described in detail above, but these are only specific examples to clarify the technical contents. Various technical ideas extracted from this specification are not limited to the order of description in the specification, the order of the embodiments, etc., and can be combined appropriately.

[0236] Explanation of symbols

[0237] 1A—wafer structure, 1B—wafer structure, 2—wafer, 3—first main surface, 4—second main surface, 10—device area, 18—first electrode, 24—second electrode, 25—plating reaction inhibitor, 45—protective band, 51—plating film, 52—Ni plating film, 53—Pd plating film, 54—Au plating film, W—exposed width, SD1—semiconductor device, SD2—semiconductor device.

Claims

1. A wafer structure, characterized in that: include: A wafer having a first surface on one side and a second surface on the other side; A first electrode covering the first surface; a second electrode covering an inner portion of the second surface in a manner that a peripheral portion of the second surface is exposed; as well as The protective tape has a property that the adhesion force with respect to the peripheral portion of the second surface is higher than the adhesion force with respect to the second electrode, and is attached to the peripheral portion of the second surface and the second electrode.

2. The wafer structure according to claim 1, characterized in that: The second electrode has a plating reaction speed higher than a plating reaction speed of the wafer, so that the peripheral edge of the wafer is exposed as a plating reaction hindering portion. The protective tape is attached to the plating reaction inhibiting portion.

3. The wafer structure according to claim 1 or 2, characterized in that: The above-mentioned wafer comprises a SiC single crystal, The second electrode exposes the SiC single crystal from the peripheral portion of the second surface. The protective tape is bonded to the SiC single crystal at the peripheral portion of the second surface.

4. The wafer structure according to any one of claims 1 to 3, characterized in that: The wafer has a thickness of less than 200 μm.

5. The wafer structure according to any one of claims 1 to 4, characterized in that: The second electrode exposes the entire periphery of the peripheral portion. The protective tape is attached to the entire circumference of the peripheral portion.

6. The wafer structure according to any one of claims 1 to 5, characterized in that: An exposed width of the peripheral portion is larger than a thickness of the second electrode.

7. The wafer structure according to claim 6, characterized in that: The exposed width is greater than the thickness of the wafer.

8. The wafer structure according to any one of claims 1 to 7, characterized in that: The wafer has the second surface, and the second surface has grinding marks. The second electrode exposes the peripheral portion having the grinding marks. The protective tape is attached to the peripheral portion having the polishing marks.

9. The wafer structure according to any one of claims 1 to 8, characterized in that: The second surface is composed of a flat surface.

10. The wafer structure according to any one of claims 1 to 9, characterized in that: It also includes a plating film, which covers the first electrode.

11. The wafer structure according to claim 10, characterized in that: The plating film includes at least one of a Ni plating film, a Pd plating film, and an Au plating film.

12. The wafer structure according to any one of claims 1 to 11, characterized in that: It also includes a plurality of equipment areas, which are set in the inner part of the first surface. The second electrode exposes a plurality of regions outside the device region in a plan view.

13. A method for manufacturing a semiconductor device, characterized in that: Including the following processes: A step of preparing a wafer structure, the wafer structure including a wafer having a first surface on one side and a second surface on the other side, and a first electrode covering the first surface; forming a second electrode covering an inner portion of the second surface in such a manner that a peripheral portion of the second surface is exposed; as well as A step of attaching a protective tape to the peripheral portion of the second surface and the second electrode, the protective tape having a property of having a higher adhesion force to the peripheral portion of the second surface than to the second electrode.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The second electrode has a plating reaction rate higher than a plating reaction rate of the wafer, and exposes the peripheral edge portion of the wafer as a plating reaction inhibitory portion.

15. The method for manufacturing a semiconductor device according to claim 13 or 14, characterized in that: The method further includes the step of immersing the wafer structure with the protective tape attached thereto in a plating solution to form a plating film on the first electrode.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The step of forming the plating film includes the step of causing the wafer structure to oscillate in the plating solution.

17. The method for manufacturing a semiconductor device according to claim 15 or 16, characterized in that: The step of forming the above-mentioned plating film includes at least one of a step of immersing the above-mentioned wafer structure in a Ni plating solution to form a Ni plating film, a step of immersing the above-mentioned wafer structure in a Pd plating solution to form a Pd plating film, and a step of immersing the above-mentioned wafer structure in an Au plating solution to form an Au plating film.

18. The method for manufacturing a semiconductor device according to any one of claims 13 to 17, wherein: The above-mentioned wafer comprises a SiC single crystal, The second electrode exposes the SiC single crystal from the peripheral portion of the second surface. The protective tape is bonded to the SiC single crystal at the peripheral portion of the second surface.

19. The method for manufacturing a semiconductor device according to any one of claims 13 to 18, wherein: It also includes the following steps: a step of preparing the wafer structure, the wafer structure including the wafer having a thickness of 200 μm or more; and Prior to the step of forming the second electrode, the wafer is thinned to a thickness less than 200 μm.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The wafer thinning step includes a step of grinding the second surface by a grinding method.

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