Light detection device

Abstract

The present disclosure relates to a light detection device capable of providing improved modulation power for the light detection device. A light detection device includes a photogate electrode disposed over a photodiode and one or more transfer transistors that transfer charges obtained by photoelectric conversion performed by the photodiode to a charge storage unit. The transfer transistors are vertical transistors each including a buried gate electrode portion in which a gate electrode is buried in a semiconductor substrate. For example, the technology of the present disclosure may be applied to a ranging module that measures a distance to an object.

Description

Technical Field

[0001] This disclosure relates to an optical detection device, and more particularly to an optical detection device capable of increasing modulation power. Background Technology

[0002] A distance sensor is known to measure the distance to an object using the time-of-flight (ToF) method. ToF-based distance sensors use photodiodes to perform photoelectric conversion on reflected light emitted from a light source and reflected from an object. The signal charge generated by the photoelectric conversion is distributed to two charge storage cells via a pair of alternately driven gate electrodes.

[0003] For example, Patent Document 1 discloses a distance sensor that includes a photogate electrode, first and second gate electrodes, and first and second semiconductor regions. The distance sensor applies charge transfer signals with different phases to the first and second gate electrodes and distributes the charge generated in the semiconductor substrate due to the incident pulse light to the region directly below the first and second gate electrodes.

[0004] Citation List

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2011-112614 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] In the distance sensor of Patent Document 1, a planar MOS transistor is used as the photogate electrode and the gate electrode. With planar MOS transistors, there are concerns about the relatively low modulation power and the difficulty in applying a distributed electric field. To enhance the distributed electric field, it is necessary to increase the modulation power.

[0009] This disclosure was made in view of this situation and is intended to improve modulation power.

[0010] Solution to the problem

[0011] The photodetector according to a first aspect of this disclosure is a photodetector comprising: a photogate electrode disposed above a photodiode; and one or more transfer transistors that transfer charge obtained by photoelectric conversion performed by the photodiode to a charge storage unit. The transfer transistors are vertical transistors, each of which includes a buried gate electrode portion wherein the gate electrode is embedded in a semiconductor substrate.

[0012] In a first aspect of this disclosure, a photogate electrode is disposed above a photodiode, and one or more transfer transistors are provided. The transfer transistors transfer charge obtained by photoelectric conversion performed by the photodiode to a charge storage unit. The transfer transistors are vertical transistors, each including a buried gate electrode portion in which the gate electrode is embedded in a semiconductor substrate.

[0013] The photodetector according to a second aspect of this disclosure is a photodetector comprising: a photogate electrode disposed above a photodiode; and one or more transfer transistors that transfer charge obtained by photoelectric conversion performed by the photodiode to a charge storage unit. The photogate electrode is a vertical transistor comprising a buried gate electrode portion embedded in a semiconductor substrate.

[0014] In a second aspect of this disclosure, a photogate electrode and one or more transfer transistors are provided above a photodiode. The transfer transistors transfer charge obtained from photoelectric conversion performed by the photodiode to a charge storage unit. The photogate electrode is a vertical transistor that includes a buried gate electrode portion embedded in a semiconductor substrate.

[0015] The optical detection device can be a standalone device or a module incorporated into another device. Attached Figure Description

[0016] Figure 1 This is a block diagram illustrating a schematic configuration example of a light detection device applying this technology.

[0017] Figure 2 This is a diagram showing a first configuration example of a photogate electrode and a transmission transistor.

[0018] Figure 3 This is a diagram showing a second configuration example of a photogate electrode and a transmission transistor.

[0019] Figure 4 This is a diagram showing a third configuration example of a photogate electrode and a transmission transistor.

[0020] Figure 5 This is a diagram illustrating the difference in effect caused by the relationship between the width of the photogate electrode and the width of the transmission transistor.

[0021] Figure 6 This is another graph illustrating the difference in effect caused by the relationship between the width of the photogate electrode and the width of the transmission transistor.

[0022] Figure 7 This is a diagram showing a fourth configuration example of a photogate electrode and a transmission transistor.

[0023] Figure 8This is a diagram showing a fifth configuration example of a photogate electrode and a transmission transistor.

[0024] Figure 9 This is a diagram showing the effect when the photogate electrode is a vertical gate electrode.

[0025] Figure 10 This is another diagram illustrating the effect when the photogate electrode is a vertical gate electrode.

[0026] Figure 11 This is a diagram showing the driving of the photogate electrode and the transmission transistor.

[0027] Figure 12 This is another diagram showing the drive of the photogate electrode and the transmission transistor.

[0028] Figure 13 This is a diagram showing an example of the first circuit configuration of a pixel.

[0029] Figure 14 This is a diagram showing an example of the second circuit configuration of a pixel.

[0030] Figure 15 This is a diagram showing a first arrangement example where the charge storage cell is a memory MEM.

[0031] Figure 16 This is a diagram illustrating a second arrangement example where the charge storage cell is a memory MEM.

[0032] Figure 17 This is a diagram illustrating an example of a transmission transistor configured in a single pixel.

[0033] Figure 18 This is a diagram showing an example of four transmission transistors configured in a single pixel.

[0034] Figure 19 This is a diagram illustrating an example where each transmission transistor includes a buried gate electrode.

[0035] Figure 20 This is a plan view showing an example of the arrangement of charge discharge transistors.

[0036] Figure 21 This is a plan view showing an example of the arrangement of charge discharge transistors.

[0037] Figure 22 This is a plan view showing an example of the arrangement of a single pixel transistor.

[0038] Figure 23 This is a plan view showing an example of the arrangement of individual pixel transistors in the case of shared pixel transistors.

[0039] Figure 24 This is a block diagram illustrating an example of the configuration of a smartphone as an electronic device applying this technology.

[0040] Figure 25 This is a block diagram illustrating a schematic example of the configuration of a vehicle control system.

[0041] Figure 26 This is an explanatory diagram showing an example of the mounting positions of the vehicle exterior information detection unit and the imaging unit. Detailed Implementation

[0042] The following description, with reference to the accompanying drawings, illustrates a mode for implementing the technology of this disclosure (hereinafter referred to as an implementation scheme). The description will proceed in the following order.

[0043] 1. Example of the configuration of a light detection device

[0044] 2. First configuration example of photogate electrode and transmission transistor

[0045] 3. A second configuration example of a photogate electrode and a transmission transistor

[0046] 4. A third configuration example of photogate electrode and transmission transistor

[0047] 5. The effect of width difference of photograting electrodes in the vertical direction

[0048] 6. Fourth configuration example of photogate electrode and transmission transistor

[0049] 7. Fifth configuration example of photogate electrode and transmission transistor

[0050] 8. Effect when the photograting electrode is a vertical grating electrode

[0051] 9. Driving the photogate electrode and the transmission transistor

[0052] 10. Example of a pixel's circuit structure

[0053] 11. First arrangement example when the charge storage unit is a memory

[0054] 12. Second arrangement example when the charge storage unit is a memory

[0055] 13. Number of transmission transistors

[0056] 14. Number of embedded grid electrode sections

[0057] 15. Example of charge discharge transistor arrangement

[0058] 16. Examples of other pixel transistor arrangements

[0059] 17. Application examples of optical detection devices

[0060] 18. Examples of the composition of electronic devices

[0061] 19. Examples of applications of moving bodies

[0062] In the accompanying drawings referenced in the following description, identical or similar parts are indicated by identical or similar reference numerals, and repeated descriptions are omitted where appropriate. The drawings are schematic, and the relationships between thicknesses and planar dimensions, the thickness ratios of layers, etc., differ from actual dimensions. Furthermore, drawings may include parts with different dimensional relationships or scales.

[0063] Furthermore, the definitions of directions such as up and down in the following description are for illustrative purposes only and are not intended to limit the technical concept of this disclosure. For example, when observing an object while rotating it 90°, up and down are considered to be converted to left and right, while when observing an object while rotating it 180°, up and down are considered to be reversed.

[0064] <1. Example of the configuration of an optical detection device>

[0065] Figure 1 This is a block diagram illustrating a schematic configuration example of a light detection device applying this technology.

[0066] Figure 1 The light detection device 1 shown is a distance sensor that outputs ranging information through an indirect ToF method.

[0067] The light detection device 1 receives light (irradiation light) emitted from a predetermined light source and reflected light (reflected light) from an object, and outputs a depth image that stores the distance information to the object as a depth value. Note that, for example, the irradiation light emitted from the light source is infrared light with a wavelength in the range of 780 nm to 1000 nm, and is pulsed light that is repeatedly turned on and off at a predetermined period.

[0068] The light detection device 1 includes a pixel array unit 21 formed on a semiconductor substrate (not shown) and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 21. For example, the peripheral circuit unit includes a vertical driving unit 22, a column processing unit 23, a horizontal driving unit 24, a system control unit 25, etc.

[0069] The photodetector 1 also includes a signal processing unit 26 and a data storage unit 27. Note that the signal processing unit 26 and the data storage unit 27 can be mounted on the same substrate as the photodetector 1, or they can be configured on a substrate in a different module than the photodetector 1.

[0070] The pixel array unit 21 is configured such that pixels 10, which generate charges corresponding to the amount of received light and output signals corresponding to those charges, are arranged in a matrix-like two-dimensional configuration in both the row and column directions. That is, the pixel array unit 21 includes a plurality of pixels 10 that perform photoelectric conversion on incident light and output signals corresponding to the charges obtained as a result of the photoelectric conversion. Here, the row direction refers to the horizontal arrangement of the pixels 10, and the column direction refers to the vertical arrangement of the pixels 10. The row direction is the left-right direction in the figure, and the column direction is the up-down direction in the figure. (Referring to later...) Figure 2 The following attached diagrams illustrate the details of pixel 10.

[0071] In pixel array unit 21, for each pixel array matrix, a pixel driving line 28 is provided in the row direction for each pixel row, and two vertical signal lines 29 are provided in the column direction for each pixel column. The pixel driving line 28 transmits driving signals for driving pixels 10, so as to read signals. Note that although... Figure 1 Each pixel driving line 28 is shown as a wiring, but the number of wirings for each pixel driving line 28 is not limited to one. One end of each pixel driving line 28 is connected to the output of the vertical driving unit 22 in the corresponding row.

[0072] The vertical drive unit 22 includes a shift register, an address decoder, etc., and drives all individual pixels 10 of the pixel array unit 21 simultaneously or row by row. In other words, the vertical drive unit 22, together with the system control unit 25 that controls the vertical drive unit 22, constitutes a drive unit that controls the operation of each pixel 10 of the pixel array unit 21.

[0073] The detection signals output from each pixel 10 in the pixel row according to the drive control of the vertical drive unit 22 are input to the column processing unit 23 through the corresponding vertical signal line 29. The column processing unit 23 performs predetermined signal processing on the detection signals output from each pixel 10 through the corresponding vertical signal line 29, and temporarily holds the signal-processed detection signals. More specifically, the column processing unit 23 performs noise removal processing, analog-to-digital (AD) conversion processing, etc. as signal processing.

[0074] The horizontal drive unit 24 includes a shift register, an address decoder, etc., and sequentially selects the unit circuits in the column processing unit 23 corresponding to the pixel column. As a result of the selective scanning performed by the horizontal drive unit 24, the detection signals, after signal processing performed by the column processing unit 23 on a unit circuit basis, are sequentially output to the signal processing unit 26.

[0075] The system control unit 25 includes a timing generator that generates various timing signals, and controls the driving of the vertical drive unit 22, column processing unit 23, horizontal drive unit 24, etc. based on the various timing signals generated by the timing generator.

[0076] The signal processing unit 26 has at least arithmetic processing capabilities and performs various types of signal processing, such as arithmetic processing, based on the detection signal output from the column processing unit 23. For example, the signal processing unit 26 performs processing to generate a depth image that stores the distance information of an object as a depth value, based on the detection signal output from the column processing unit 23. The data storage unit 27 temporarily stores the data required for the signal processing performed by the signal processing unit 26.

[0077] The light detection device 1 configured as described above performs processing to generate a depth image that stores distance information to an object as depth values. Optionally, the light detection device 1 outputs a detection signal as the source of distance information to the object in pixels.

[0078] Each pixel 10 in pixel array unit 21 includes two charge storage units, and the charge obtained by performing photoelectric conversion on reflected light, which is illumination light reflected from an object, is alternately distributed to these two charge storage units at regular intervals, so that the charge storage units store charge. Since the timing delay of the emission of reflected light from the light source received by each pixel 10 according to the distance to the object varies, the distribution ratio of the charge stored in the two charge storage units changes according to the delay time corresponding to the distance to the object. The distance to the object can be obtained from the distribution ratio of the charge stored in the two charge storage units.

[0079] The following will describe the configuration of the allocation unit that distributes the charge generated by the photoelectric conversion element to the two charge storage units in the structure of each pixel 10 included in the pixel array unit 21.

[0080] <2. First Configuration Example of Photogate Electrode and Transmission Transistor>

[0081] Figure 2 These are plan views and cross-sectional views showing a first configuration example of the photogate electrode and the transmission transistor. The cross-sectional view on the right corresponds to the cross-sectional view taken along line X-X' in the plan view on the left.

[0082] exist Figure 2In the first configuration example shown, pixel 10 includes a photodiode (PD) 41 as a photoelectric conversion element, a photogate electrode PG, two transmission transistors TG1 and TG2 as two transmission transistors TG, and two floating diffusion regions FD1 and FD2 as two floating diffusion regions FD. The two transmission transistors TG1 and TG2 correspond to distribution units for distributing charge, and the two floating diffusion regions FD1 and FD2 correspond to charge storage units for storing charge.

[0083] As shown in the cross-sectional view, for each pixel, a photodiode 41 is formed in a semiconductor substrate 40, for example, a silicon substrate using silicon (Si) as the semiconductor. The photodiode 41 is a pn junction photodiode, wherein an n-type (second conductivity type) semiconductor region is formed in the region of the p-type (first conductivity type) semiconductor region of the semiconductor substrate 40.

[0084] A photogate electrode PG is formed on a gate insulating film 42 formed on the upper surface of the substrate of the photodiode 41. For example, the photogate electrode PG contains polycrystalline silicon, but other materials (e.g., metallic materials) may also be used. The photogate electrode PG is a charge collection electrode that collects the charge generated by the photodiode 41 in a region below the photogate electrode PG.

[0085] The gate electrode 51 of the transmission transistor TG1 is formed on the left side of the photogate electrode PG, and the gate electrode 52 of the transmission transistor TG2 is formed on the right side of the photogate electrode PG. In other words, the gate electrode 51 of the transmission transistor TG1 and the gate electrode 52 of the transmission transistor TG2 are arranged to face each other across the photogate electrode PG.

[0086] The gate electrode 51 of the transmission transistor TG1, located to the left of the photogate electrode PG, includes a planar gate electrode portion 51P on the upper surface of the semiconductor substrate 40 and a buried gate electrode portion 51VG embedded in the semiconductor substrate 40. A gate insulating film 53 is formed between the gate electrode 51 and the semiconductor substrate 40. A floating diffusion region FD1, composed of a high-concentration n-type semiconductor region (n+), is formed in the semiconductor substrate 40 on the opposite side of the photogate electrode PG, centered on the gate electrode 51 of the transmission transistor TG1.

[0087] The gate electrode 52 of the transmission transistor TG2, located to the right of the photogate electrode PG, includes a planar gate electrode portion 52P on the upper surface of the semiconductor substrate 40 and a buried gate electrode portion 52VG embedded in the semiconductor substrate 40. A gate insulating film 54 is formed between the gate electrode 52 and the semiconductor substrate 40. A floating diffusion region FD2, composed of a high-concentration n-type semiconductor region (n+), is formed in the semiconductor substrate 40 on the opposite side of the photogate electrode PG, centered on the gate electrode 52 of the transmission transistor TG2.

[0088] As shown in the plan view, for example, the gate electrode 51 of the transmission transistor TG1 includes two buried gate electrode portions 51VG formed in a cylindrical shape. Similarly, for example, the gate electrode 52 of the transmission transistor TG2 includes two buried gate electrode portions 52VG formed in a cylindrical shape.

[0089] When the arrangement direction of the gate electrode 51 of the transmission transistor TG1, the photogate electrode PG, and the gate electrode 52 of the transmission transistor TG2 is defined as a horizontal direction (first direction), and the direction perpendicular to this arrangement direction is defined as a vertical direction (second direction), the width W of the photogate electrode PG in the vertical direction is... PG The width W is formed to be greater than the width of the gate electrode 51 of the transmission transistor TG1 and the gate electrode 52 of the transmission transistor TG2. TG .

[0090] Without special distinction, the buried gate electrode portion 51VG of the transmission transistor TG1 and the buried gate electrode portion 52VG of the transmission transistor TG2 will be referred to as the buried gate electrode portion VG.

[0091] In the first configuration example, as described above, the transmission transistor TG1 is a vertical transistor including a buried gate electrode portion 51VG, wherein the gate electrode 51 is buried in the semiconductor substrate 40. Furthermore, the transmission transistor TG2 is also a vertical transistor including a buried gate electrode portion 52VG buried in the semiconductor substrate 40. Since the transmission transistors TG1 and TG2 are vertical transistors, the modulation power of the transmission transistor TG can be increased, and the distributed electric field can be enhanced. Furthermore, since a photogate electrode PG is used and the potential of the photodiode 41 is controlled by voltage, the degradation of the distributed characteristics due to manufacturing variations can be suppressed. Therefore, it is possible to enhance the distributed electric field while suppressing the degradation of the distributed characteristics due to manufacturing variations, and to improve imaging and ranging characteristics.

[0092] <3. Second Configuration Example of Photogate Electrode and Transmission Transistor>

[0093] Figure 3 This is a plan view showing a second configuration example of a photogate electrode and a transmission transistor.

[0094] exist Figure 3 In the second constituent example, with Figure 2 The corresponding parts of the components in the first configuration example shown are given the same reference numerals, and the parts that are different from the first configuration example will be described.

[0095] exist Figure 2 In the first configuration example shown, the width W of the photogate electrode PG is [not specified in the original text]. PGThe width W is formed to be greater than the width of the gate electrode 51 of the transmission transistor TG1 and the gate electrode 52 of the transmission transistor TG2. TG (width W) PG Width W TG ).

[0096] On the other hand, Figure 3 In the second configuration example, regarding the width in the vertical direction, the width W of the photogate electrode PG... PG The width W of the gate electrode 51 of the transmission transistor TG1 and the gate electrode 52 of the transmission transistor TG2 is formed to be equal to or smaller than that of the transmission transistor TG2. TG (width W) PG = Width W TG Or width W PG Width W TG Aside from the difference in the formation size (planar region) of the photogate electrode PG, Figure 3 The second constituent example and Figure 2 The first example shown is similarly formed.

[0097] <4. Third configuration example of photogate electrode and transmission transistor>

[0098] Figure 4 This is a plan view showing a third configuration example of a photogate electrode and a transmission transistor.

[0099] exist Figure 4 In the third configuration example, the parts corresponding to the parts in the first and second configuration examples are also given the same reference numerals, and the parts that are different from those in the first and second configuration examples will be described.

[0100] exist Figure 4 In the third configuration example, similar to the second configuration example, the width W of the photogate electrode PG is [not specified] in the vertical direction. PG The width W is formed to be smaller than the gate electrode 51 of the transmission transistor TG1 and the gate electrode 52 of the transmission transistor TG2. TG (width W) PG Width W TG In addition, in Figure 4 In the third configuration example, the width W of the photogate electrode PG PG The width W is formed to be smaller than the width between the two buried gate electrode portions VG of the transmission transistors TG1 and TG2. VG (width W) PG Width W VG Aside from the difference in the formation size (planar region) of the photogate electrode PG, Figure 4 The third constituent example and Figure 2 The first example shown is similarly formed.

[0101] In the second and third configuration examples of the photogate electrode PG and the transmission transistor TG, the transmission transistors TG1 and TG2 are vertical transistors. As a result, the modulation power of the transmission transistor TG can be increased, and the distributed electric field can be enhanced. Furthermore, since the photogate electrode PG is used and the potential of the photodiode 41 is controlled by voltage, the degradation of the distribution characteristics due to manufacturing variations can be suppressed. Therefore, it is possible to enhance the distributed electric field while suppressing the degradation of the distribution characteristics due to manufacturing variations, and to improve imaging and ranging characteristics.

[0102] <5. The Influence of Width Differences in the Vertical Direction of the Photograting Electrode>

[0103] Reference Figure 5 and Figure 6 This will explain the difference in width W between the photogate electrode PG and the vertical direction. PG Width W in the vertical direction of the transmission transistor TG TG The difference in effects is due to the relationship between them. Figure 5 and Figure 6 In the diagram, the two buried gate electrode portions VG of the transmission transistors TG1 and TG2 are shown with different patterns to prioritize visibility.

[0104] In the first example, such as Figure 5 As shown, the charge generated by the photodiode 41 of the semiconductor substrate 40 is randomly collected in a planar region below the photogate electrode PG. For example, if a portion of the randomly collected charge outside the gate electrode 51 of the transmission transistor TG1 and the gate electrode 52 of the transmission transistor TG2 is collected in the floating diffusion region FD2 on the right, the charge is collected in the floating diffusion region FD2 outside the two buried gate electrode portions 52VG and is affected by traps at the interface of the buried gate electrode portions 52VG. As a result, there are concerns about charge loss or transmission delay and degradation of imaging or ranging characteristics.

[0105] On the other hand, such as Figure 6 As shown, similar to the third configuration example, for example, the width W of the photogate electrode PG in the vertical direction... PG The width W between the two buried gate electrode portions 52VG of the transmission transistor TG2 is smaller than that of the transmission transistor TG2. VG In this case, the charges randomly collected in the planar region below the photograting electrode PG pass between the two embedded grating electrode sections 52VG and are collected in the floating diffusion region FD2, unaffected by the interface of the embedded grating electrode sections 52VG. In other words, the influence of the interface state can be suppressed, and imaging and ranging characteristics can be improved.

[0106] Therefore, in the first to third configuration examples, the width W of the photogate electrode PG is... PG Width W greater than that of the transmission transistor TG TG Compared to the first constituent example, where the width W PG The width W of the transmission transistor TG is equal to or less than TG The second configuration example is preferred. Furthermore, the width W of the photogate electrode PG is... PG Less than the width W between the two embedded gate electrode sections VG VG The third constituent example is more preferred than the second constituent example.

[0107] <6. Fourth configuration example of photogate electrode and transmission transistor>

[0108] Figure 7 These are plan and cross-sectional views showing a fourth configuration example of the photogate electrode and the transmission transistor. The cross-sectional view on the right corresponds to the cross-sectional view taken along line X-X' in the plan view on the left. Figure 7 In the fourth constituent example, with Figure 2 The parts corresponding to the parts of the first configuration example shown are given the same reference numerals, and the parts that are different from the first configuration example will be described.

[0109] exist Figure 2 In the first configuration example shown, the transmission transistors TG1 and TG2 are vertical transistors including two buried gate electrode portions VG, and the photogate electrode PG is a planar gate electrode.

[0110] On the other hand, Figure 7 In the fourth configuration example, transmission transistors TG1' and TG2' and a photogate electrode PG' are formed to replace Figure 2 The first configuration example shown includes transmission transistors TG1 and TG2 and a photogate electrode PG.

[0111] Transmission transistor TG1' is a planar transistor, and its gate electrode portion 51' corresponds only to the planar gate electrode portion 51P of the first configuration example. Similarly, transmission transistor TG2' is a planar transistor, and its gate electrode portion 52' corresponds only to the planar gate electrode portion 52P of the first configuration example.

[0112] On the other hand, the photogate electrode PG' includes a planar gate electrode portion 61P' on the upper surface of the semiconductor substrate 40 and a buried gate electrode portion 61VG' embedded in the semiconductor substrate 40. A gate insulating film 62 is formed between the photogate electrode PG' and the semiconductor substrate 40.

[0113] As shown in the plan view, for example, the photogate electrode PG' includes two buried gate electrode portions 61VG' formed in a cylindrical shape. The depth of the buried gate electrode portions 61VG' in the substrate thickness direction is the depth reaching the n-type semiconductor region of the photodiode 41.

[0114] In the fourth configuration example, as described above, the transmission transistors TG1' and TG2' are planar transistors. On the other hand, the photogate electrode PG' is a vertical gate electrode, comprising a planar gate electrode portion 61P' and a buried gate electrode portion 61VG'. Since the photogate electrode PG' is a vertical gate electrode, the distance to the photodiode 41 is shortened, and the voltage applied to the photogate electrode PG' can be lower than the voltage applied to the planar photogate electrode PG. Because control can be performed at a low voltage, power consumption can be suppressed.

[0115] <7. Fifth Configuration Example of Photogate Electrode and Transmission Transistor>

[0116] Figure 8 These are plan and cross-sectional views showing a fifth configuration example of the photogate electrode and the transmission transistor. The cross-sectional view on the right corresponds to the cross-sectional view taken along line X-X' in the plan view on the left.

[0117] exist Figure 8 In the fifth configuration example shown, both the photogate electrode and the transmission transistor include a buried gate electrode portion.

[0118] In other words, Figure 8 Pixel 10 in the middle includes Figure 2 The first configuration example shown includes transmission transistors TG1 and TG2, and Figure 7 The photograting electrode PG' is shown. Although... Figure 7 The photogate electrode PG' shown includes two embedded gate electrode portions 61VG', however... Figure 8 The photogate electrode PG' includes a buried gate electrode portion 61VG'. Regarding its depth in the substrate thickness direction, the buried gate electrode portion 61VG' is formed to be shorter than the buried gate electrode portions VG of the transmission transistors TG1 and TG2. That is, when the depth of the buried gate electrode portion 61VG' is represented by TD1 and the depth of the buried gate electrode portions VG of the transmission transistors TG1 and TG2 is represented by TD2, TD1... <TD2。

[0119] In the fifth configuration example, as described above, the transmission transistors TG1 and TG2 are vertical transistors. As a result, the modulation power of the transmission transistor TG can be increased, and the distributed electric field can be enhanced. Furthermore, since a photogate electrode PG' is used and the potential of the photodiode 41 is controlled by voltage, the degradation of the distributed characteristics due to manufacturing variations can be suppressed. Therefore, it is possible to enhance the distributed electric field while suppressing the degradation of the distributed characteristics due to manufacturing variations, and to improve imaging and ranging characteristics. Moreover, the photogate electrode PG' is composed of a vertical gate electrode. As a result, the voltage applied to the photogate electrode PG' can be lower, and power consumption can be suppressed.

[0120] <8. Effect when the photograting electrode is a vertical grating electrode>

[0121] Reference Figure 9 and Figure 10 This will explain the effect when the photograting electrode is a vertical grating electrode.

[0122] like Figure 9 As shown in the plan and cross-sectional views on the left, in the photogate electrode PG without a vertical gate electrode structure, since the sensor potential SP, which is the location with the highest potential in the photodiode 41, and the photogate electrode PG are separated from each other in the depth direction, a high voltage needs to be applied to the photogate electrode PG in order to control the potential at the sensor potential SP. As a result, power consumption increases. Furthermore, when a voltage is applied to the photogate electrode PG, the sensor potential SP shifts to the vicinity of the interface of the semiconductor substrate 40 above the photodiode 41, and is easily affected by the substrate interface during charge transport.

[0123] On the other hand, in the photogate electrode PG' with a vertical gate electrode structure, since the distance between the sensor potential SP and the photogate electrode PG in the depth direction is shortened, the applied voltage used to control the potential at the sensor potential SP can be set to a low voltage. As a result, power consumption can be reduced. Furthermore, by controlling the depth of the embedded gate electrode portion 61VG' of the photogate electrode PG', the sensor potential SP can be set at a desired position in the substrate depth direction. As a result, the influence of the substrate interface during charge transport can be reduced.

[0124] In addition, such as Figure 10 As shown in the cross-sectional view on the left, when the depth TD1 of the buried gate electrode portion 61VG' of the photogate electrode PG' in the substrate thickness direction is greater than the depth TD2 of the buried gate electrode portion VG of the transmission transistors TG1 and TG2 in the substrate thickness direction (TD1>TD2), the distance from the sensor potential SP to the floating diffusion region FD (FD1 or FD2) that serves as the transmission destination becomes longer, and a high voltage needs to be applied to the transmission transistor TG during transmission.

[0125] As shown Figure 10 in the cross-sectional view on the right side, by making the depth TD1 in the substrate thickness direction of the buried gate electrode portion 61VG' of the photogate electrode PG' smaller than the depth TD2 in the substrate thickness direction of the buried gate electrode portion VG of the transfer transistors TG1 and TG2 (TD1 < TD2), the transfer distance can be shortened, and the voltage applied to the transfer transistor TG during transfer can be reduced. In addition, it is possible to make it less susceptible to variations in distribution.

[0126] <9. Driving of Photogate Electrode and Transfer Transistor>

[0127] will be described with reference to Figure 11 and Figure 12 the driving of the photogate electrode and the transfer transistors. In Figure 11 and Figure 12 the driving of the photogate electrode PG and the transfer transistors TG in the first configuration example will be described, but this also applies to the case of the photogate electrode PG' and the transfer transistors TG' other than the first configuration example.

[0128] Figure 11 is a timing chart of the signals applied to the photogate electrode PG and the two transfer transistors TG1 and TG2 in the first configuration example.

[0129] The transfer drive signal TG1g is a pulse signal supplied to the gate electrode �1 of the transfer transistor TG1, and the transfer drive signal TG2g is a pulse signal supplied to the gate electrode �2 of the transfer transistor TG2. The control signal PGTG is a pulse signal supplied to the photogate electrode PG.

[0130] In order to output a detection signal (pixel signal) once, as Figure 11 shown, the pixel 10 has a TG cutoff period and a TG drive period. In the TG cutoff period, the driving of the transfer transistor TG is cut off, and in the TG drive period, the driving of alternately turning on the two transfer transistors TG1 and TG2 is performed.

[0131] In the TG cutoff period, the transfer drive signal TG1g and the transfer drive signal TG2g are set to a low level. On the other hand, in the TG cutoff period, the control signal PGTG supplied to the photogate electrode PG is set to a high level.

[0132] On the other hand, in the TG drive period, the transfer drive signal TG1g and the transfer drive signal are alternately set to a high level, and the control signal PGTG supplied to the photogate electrode PG is set to a low level.

[0133] Figure 12 ​​These are potential diagrams of the photogate electrode PG and the two transmission transistors TG1 and TG2 during the TG cutoff period and the TG drive period, respectively.

[0134] During the TG cutoff period, a first voltage Φ is supplied to the photogate electrode PG via the control signal PGTG. PG1 Furthermore, by transmitting drive signals TG1g and TG2g, a cutoff voltage Φ is provided to the two transmission transistors TG1 and TG2 to turn off the transmission transistor TG. TG-OFF Here, the first voltage Φ PG1 and cutoff voltage Φ TG-OFF The relationship between them is Φ TG-OFF <Φ PG1 In other words, the first voltage Φ PG1 It is higher than the cutoff voltage Φ of the transfer transistor TG. TG-OFF The voltage is such that the potential of the semiconductor region (silicon region) below the photogate electrode PG of the semiconductor substrate 40 is set to be greater than the potential of the semiconductor region (silicon region) below the transmission transistor TG. In other words, the potential below the photogate electrode PG is set to be deeper than the potential below the transmission transistor TG. With the first voltage Φ PG1 and cutoff voltage Φ TG-OFF Increasing the potential difference ΔV between the two regions can reduce leakage to the floating diffusion region FD when the transmission transistor TG is turned off, and can suppress parasitic light sensitivity (PLS). As a result, imaging and ranging characteristics can be improved.

[0135] On the other hand, during the TG driving period, a second voltage Φ is provided to the photogate electrode PG via the control signal PGTG. PG2 (Φ PG2 <Φ PG1 Furthermore, by transmitting drive signals TG1g and TG2g, the on-state voltage Φ for turning on the transmission transistor TG is alternately provided to the two transmission transistors TG1 and TG2. TG-ON . To which no on-state voltage Φ is provided TG-ON Another of the transfer transistors TG1 and TG2 provides a cutoff voltage Φ TG-OFF Here, the second voltage Φ PG2 and the on-state voltage Φ TG-ON The relationship between them is Φ TG-ON ≥Φ PG2 That is, the second voltage Φ PG2 It is the on-state voltage Φ of the transfer transistor TG that is lower than or equal to the on-state voltage Φ. TG-ONThe voltage is such that the potential of the semiconductor region (silicon region) below the photogate electrode PG of the semiconductor substrate 40 is set to be lower than or equal to the potential of the semiconductor region (silicon region) below the transmission transistor TG. In other words, the potential below the conducting transmission transistor TG is set deeper than the potential below the photogate electrode PG. As a result, distribution variations can be suppressed and ranging characteristics can be improved.

[0136] As described above, the vertical drive unit 22 will have a first voltage Φ PG1 Second voltage Φ PG2 Two or more control signals PGTG are provided to the photograting electrode PG, and different voltages are applied to the photograting electrode PG during the TG cutoff period and the TG drive period. As a result, imaging and ranging characteristics can be improved.

[0137] <10. Example of a pixel's circuit structure>

[0138] Figure 13 A first circuit configuration example of pixels 10 arranged in two dimensions in pixel array unit 21 is shown.

[0139] Figure 13 The first circuit configuration example shown is a configuration in which the charge storage unit for storing distributed charge is a floating diffusion region FD as described above.

[0140] Pixel 10 includes a photodiode (PD) 41 as a photoelectric conversion element and a photogate electrode PG formed on the upper surface of the substrate of the photodiode 41. A predetermined control signal PGTG is applied to the photogate electrode PG by the vertical driving unit 22.

[0141] In addition, pixel 10 includes two transmission transistors TG, two floating diffusion regions FD, two amplification transistors AMP, two reset transistors RST, and two selection transistors SEL. Furthermore, pixel 10 includes a charge discharge transistor OFG.

[0142] Here, as Figure 13 As shown, with the two transmission transistors TG, two floating diffusion regions FD, two amplification transistors AMP, two reset transistors RST, and two selection transistors SEL set for pixel 10 being distinguished from each other, these components will be referred to as transmission transistors TG1 and TG2, floating diffusion regions FD1 and FD2, amplification transistors AMP1 and AMP2, reset transistors RST1 and RST2, and selection transistors SEL1 and SEL2.

[0143] For example, the transfer transistor TG, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the charge discharge transistor OFG are n-type MOS transistors.

[0144] When the transmission drive signal TG1g supplied to the gate electrode of transmission transistor TG1 becomes active, transmission transistor TG1 turns on in response, thereby transferring the charge stored in photodiode 41 to floating diffusion region FD1. When the transmission drive signal TG2g supplied to the gate electrode of transmission transistor TG2 becomes active, transmission transistor TG2 turns on in response, thereby transferring the charge stored in photodiode 41 to floating diffusion region FD2.

[0145] The floating diffusion regions FD1 and FD2 are charge storage units that temporarily hold the charge transferred from the photodiode 41.

[0146] When the reset drive signal RST1g supplied to the gate electrode of reset transistor RST1 becomes active, reset transistor RST1 turns on in response, thereby resetting the potential of floating diffusion region FD1. When the reset drive signal RST2g supplied to the gate electrode of reset transistor RST2 becomes active, reset transistor RST2 turns on in response, thereby resetting the potential of floating diffusion region FD2.

[0147] When the discharge drive signal OFG1g provided to the gate electrode of the charge discharge transistor OFG becomes active, the charge discharge transistor OFG turns on in response, thereby discharging the charge stored in the photodiode 41.

[0148] When the source electrode of amplifying transistor AMP1 is connected to vertical signal line 29A via select transistor SEL1, amplifying transistor AMP1 is connected to a constant current source (not shown) to form a source follower circuit. When the source electrode of amplifying transistor AMP2 is connected to vertical signal line 29B via select transistor SEL2, amplifying transistor AMP2 is connected to a constant current source (not shown) to form a source follower circuit.

[0149] The select transistor SEL1 is connected between the source electrode of the amplifier transistor AMP1 and the vertical signal line 29A. When the select signal SEL1g supplied to the gate electrode of the select transistor SEL1 becomes active, the select transistor SEL1 turns on in response, thereby outputting the detection signal VSL1 from the amplifier transistor AMP1 to the vertical signal line 29A.

[0150] The select transistor SEL2 is connected between the source electrode of the amplifier transistor AMP2 and the vertical signal line 29B. When the select signal SEL2g supplied to the gate electrode of the select transistor SEL2 becomes active, the select transistor SEL2 turns on in response, thereby outputting the detection signal VSL2 from the amplifier transistor AMP2 to the vertical signal line 29B.

[0151] The transmission transistors TG1 and TG2, the amplification transistors AMP1 and AMP2, the selection transistors SEL1 and SEL2, and the charge discharge transistor OFG of pixel 10 are controlled by the vertical drive unit 22.

[0152] The operation of pixel 10 will be briefly explained.

[0153] First, before light reception begins, a reset operation is performed in all pixels to reset the charge in pixel 10. That is, the charge discharge transistor OFG and reset transistors RST1 and RST2 are turned on, and the charge stored in photodiode 41 and floating diffusion regions FD1 and FD2 is discharged.

[0154] After the stored charge is discharged, light begins to be received in all pixels.

[0155] During the light receiving period, transmission transistors TG1 and TG2 are driven alternately. That is, in the first period, transmission transistor TG1 is turned on, while transmission transistor TG2 is turned off. During this first period, the charge generated by photodiode 41 is transferred to the floating diffusion region FD1. In the second period following the first period, transmission transistor TG1 is turned off, while transmission transistor TG2 is turned on. During this second period, the charge generated by photodiode 41 is transferred to the floating diffusion region FD2. As a result, the charge generated by photodiode 41 is distributed and stored in the floating diffusion regions FD1 and FD2. During the charge distribution period generated by photodiode 41, the control signal PGTG applied to the photogate electrode PG is set to a low level.

[0156] After the light receiving period ends, the control signal PGTG applied to the photogate electrode PG is set to a high level, and each pixel 10 of the pixel array unit 21 is selected row by row. In the selected pixels 10, selection transistors SEL1 and SEL2 are turned on. As a result, the charge stored in the floating diffusion region FD1 is output to the column processing unit 23 as a detection signal VSL1 via the vertical signal line 29A. The charge stored in the floating diffusion region FD2 is output to the column processing unit 23 as a detection signal VSL2 via the vertical signal line 29B.

[0157] Therefore, once one optical receiving operation ends, the next optical receiving operation, which begins with the reset operation, is executed.

[0158] The reflected light received by pixel 10 is delayed from the timing of the light source emission based on the distance to the object. Since the distribution ratio of the charges stored in the two floating diffusion regions FD1 and FD2 varies according to the delay time corresponding to the distance to the object, the distance to the object can be obtained from the distribution ratio of the charges stored in the two floating diffusion regions FD1 and FD2.

[0159] Figure 14 An example of a second circuit configuration is shown, which is another circuit configuration for pixel 10.

[0160] Note that in Figure 14 In, with Figure 13 Corresponding parts in the figures are given the same reference numerals, and their descriptions are omitted as appropriate.

[0161] Figure 14 The second circuit configuration example shown is a configuration example where the charge storage unit for storing distributed charges is a memory MEM.

[0162] Figure 13 The first pixel circuit shown includes two transmission transistors TG, two floating diffusion regions FD, two amplification transistors AMP, two reset transistors RST, and two selection transistors SEL.

[0163] On the other hand, Figure 14 In the second pixel circuit, the number of floating diffusion region FD, reset transistor RST, amplification transistor AMP, and selection transistor SEL becomes 1. Figure 13 In the first pixel circuit shown, the charge generated by photodiode 41 is held in the floating diffusion region FD, but... Figure 14 In the second pixel circuit, the charge is held in the memory MEM. Furthermore, in Figure 14 In the second pixel circuit, a new switching transistor FDG and an additional capacitor FDL are added.

[0164] Pixel 10 includes a photodiode 41, a charge discharge transistor OFG, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. Additionally, pixel 10 includes two first transmission transistors TG, two second transmission transistors MTR, and two memory transistors MEM.

[0165] Here, in the case where the two first transmission transistors TG, the two second transmission transistors MTR, and the two memories MEM in pixel 10 are different from each other, such as Figure 3 As shown, these components will be referred to as first transfer transistors TG1 and TG2, second transfer transistors MTR1 and MTR2, and memories MEM1 and MEM2.

[0166] For example, the first transfer transistor TG, the second transfer transistor MTR, the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the charge discharge transistor OFG are n-type MOS transistors.

[0167] exist Figure 14 In the second pixel circuit, the charge generated by the photodiode 41 is transferred and stored in the memories MEM1 and MEM2, which are set as charge storage units.

[0168] In other words, when the first transmission drive signal TG1g supplied to the gate electrode of the first transmission transistor TG1 becomes active, the first transmission transistor TG1 turns on in response, thereby transferring the charge stored in the photodiode 41 to the memory MEM1. When the first transmission drive signal TG2g supplied to the gate electrode of the first transmission transistor TG2 becomes active, the first transmission transistor TG2 turns on in response, thereby transferring the charge stored in the photodiode 41 to the memory MEM2.

[0169] Furthermore, when the second transmission drive signal MT1g supplied to the gate electrode of the second transmission transistor MTR1 becomes active, the second transmission transistor MTR1 turns on in response, thereby transferring the charge stored in the memory MEM1 to the floating diffusion region FD. When the second transmission drive signal MT2g supplied to the gate electrode of the second transmission transistor MTR2 becomes active, the second transmission transistor MTR2 turns on in response, thereby transferring the charge stored in the memory MEM2 to the floating diffusion region FD.

[0170] When the FD drive signal FDG1g provided to the gate electrode of the switching transistor FDG becomes active, the switching transistor FDG becomes on, thereby connecting the additional capacitor FDL to the floating diffusion region FD.

[0171] For example, in high-illuminance conditions where the incident light intensity is high, the vertical drive unit 22 activates the switching transistor FDG to connect the floating diffusion region FD and the additional capacitor FDL to each other. Therefore, in high-illuminance conditions, more charge can be stored.

[0172] In low-light conditions where the incident light intensity is low, the vertical drive unit 22 cuts off the switching transistor FDG to separate the additional capacitor FDL from the floating diffusion region FD. As a result, the conversion efficiency can be improved.

[0173] When the reset drive signal RST1g supplied to the gate electrode of the reset transistor becomes active, the reset transistor RST turns on in response, thereby resetting the potential of the floating diffusion region FD. Note that when the reset transistor RST is active, the second transfer transistors MTR1 and MTR2, as well as the switching transistor FDG, are also active simultaneously, and the memories MEM1 and MEM2, as well as the additional capacitor FDL, are also reset.

[0174] The source electrode of the amplifying transistor AMP is connected to the vertical signal line 29 via the select transistor SEL, thus connecting the amplifying transistor AMP to a constant current source (not shown) to form a source follower circuit. The select transistor SEL is connected between the source electrode of the amplifying transistor AMP and the vertical signal line 29. When the select signal SEL1g supplied to the gate electrode of the select transistor SEL becomes active, the select transistor SEL turns on in response, thereby outputting the detection signal VSL from the amplifying transistor AMP to the vertical signal line 29.

[0175] exist Figure 14 In the second pixel circuit, the charge generated by photodiode 41 is distributed and accumulated in memories MEM1 and MEM2. Then, the charge held in memories MEM1 and MEM2 is transferred to the floating diffusion region FD during read timing and output from pixel 10.

[0176] Note that the circuit configuration of pixel 10 is not limited to... Figure 13 or Figure 14 The composition can also adopt other compositions. For example, in Figure 14 In the configuration shown, the distributed charge is held in memories MEM1 and MEM2, as... Figure 13 Similar to the first pixel circuit, it can be configured with two amplifying transistors AMP, two reset transistors RST, and two select transistors SEL.

[0177] Despite targeting Figure 13 and Figure 14 The circuit configuration illustrates the use of Figures 2 to 4 The pixel circuit shown includes the photogate electrode PG and transfer transistors TG1 and TG2, but this also applies to the use of... Figure 7 and Figure 8 The photogate electrode PG' and the transmission transistors TGA' and TG2' are shown.

[0178] <11. First Arrangement Example When the Charge Storage Unit is a Memory>

[0179] Figure 15 This shows that in a charge storage cell such as Figure 14The diagram shows a plan view and a cross-sectional view of a first arrangement example of the memory MEM and the second transmission transistor MTR in the case where the second pixel circuit is also a memory MEM. For the cross-sectional views, a cross-sectional view taken along the X-X' line in the plan view and a cross-sectional view taken along the Y-Y' line are shown.

[0180] exist Figure 15 In this document, descriptions of portions of the drawings that share the same reference numerals as those described above have been appropriately omitted. Figure 15 In the process, for the photogate electrode PG and the transfer transistor TG, the following were adopted: Figure 2 The first example is shown, but some reference numerals have been omitted for simplicity.

[0181] The memory MEM1 is formed on the opposite side of the photogate electrode PG, centered on the first transmission transistor TG1. The memory MEM1 is configured as a MIS capacitor (MOS capacitor), which includes a high-density n-type semiconductor region (n+) 81 formed in the semiconductor substrate 40, an insulating film 82, and a gate electrode 83 containing polysilicon, etc.

[0182] Furthermore, the memory MEM2 is formed on the opposite side of the photogate electrode PG, centered on the first transmission transistor TG2. The memory MEM2 is configured as a MIS capacitor (MOS capacitor), which includes a high-density n-type semiconductor region (n+) 91 formed in the semiconductor substrate 40, an insulating film 92, and a gate electrode 93 containing polysilicon, etc.

[0183] With the arrangement direction of the first transmission transistor TG1, photogate electrode PG and the first transmission transistor TG2 defined as horizontal and the direction perpendicular to this arrangement direction defined as vertical, the second transmission transistor MTR1 and the floating diffusion region FD1 are arranged side by side in the vertical direction of the memory MEM1.

[0184] The second transmission transistor MTR1 includes a gate electrode 101 containing polysilicon and the like, and a gate insulating film 102. The high-concentration n-type semiconductor region 81 of the memory MEM1 and the high-concentration n-type semiconductor region of the floating diffusion region FD1 correspond to the source region or the drain region.

[0185] Similarly, the second transmission transistor MTR2 and the floating diffusion region FD2 are arranged side-by-side in the vertical direction of the memory MEM2. The second transmission transistor MTR2 includes a gate electrode 111 containing polysilicon or the like and a gate insulating film (not shown). The high-concentration n-type semiconductor region 91 of the memory MEM2 and the high-concentration n-type semiconductor region FD2 correspond to the source region or the drain region. The high-concentration n-type semiconductor regions of the floating diffusion regions FD1 and FD2 are electrically connected to each other by metal wiring formed in the wiring layer, thereby forming a floating diffusion region FD.

[0186] <12. Example of a second arrangement where the charge storage unit is a memory>

[0187] Figure 16 This shows that in a charge storage cell such as Figure 14 The second pixel circuit shown is a plan view and a cross-sectional view of a second arrangement example of the memory MEM and the second transmission transistor MTR, in the case where the memory MEM is also present. For the cross-sectional views, a cross-sectional view taken along the X-X' line in the plan view and a cross-sectional view taken along the Y-Y' line are shown.

[0188] exist Figure 16 In the text, the part related to is appropriately omitted. Figure 15 The description of the parts shown in the first arrangement example that share the same reference numerals is provided. Figure 16 In the middle, similarly, with Figure 15 Similarly, for the sake of simplicity, some figure labels have been omitted.

[0189] Despite Figure 15 The first arrangement example shown illustrates an example in which the memories MEM1 and MEM2 are constructed as MIS capacitors, but the memories MEM1 and MEM2 can be composed of only high-concentration n-type semiconductor regions, just like the floating diffusion regions FD1 and FD2.

[0190] Figure 16 The second arrangement example illustrates an instance where memories MEM1 and MEM2 consist solely of high-concentration n-type semiconductor regions. Figure 16 In the second arrangement example, with Figure 15 Compared to the first arrangement example shown, the insulating film 82 and gate electrode 83 are omitted in memory MEM1, and the insulating film 92 and gate electrode 93 are omitted in memory MEM2. Other components are the same as... Figure 15 The components in the first embodiment shown are similar, and therefore their description is omitted.

[0191] <13. Number of transmission transistors>

[0192] Although the example above illustrates the configuration of setting two transmission transistors TG for a pixel, the number of transmission transistors TG set in a pixel is not limited to two.

[0193] For example, such as Figure 17 As shown, a single transmission transistor TG (transmission transistor TG1 only) can be set for each pixel, or as... Figure 18 As shown, four transmission transistors TG1-TG4 can be set for one pixel. A floating diffusion region FD, serving as charge storage units, is also provided, with the same number of transmission transistors TG.

[0194] For example, if a transmission transistor TG1 is set for a single pixel, the charge generated by the photodiode 41 is read in a time-division manner, and the distance to the object can be obtained from the read charge distribution ratio.

[0195] For example, if four transmission transistors TG1 to TG4 are set for a pixel, the distance to the object can be obtained by a four-phase method in which charge is stored in floating diffusion regions FD1 to FD4 while the phase is shifted by 90 degrees each time.

[0196] <14. Number of Embedded Gate Electrode Sections>

[0197] In the above example, for example, with Figure 2 Similar to the first configuration example, this paper describes the configuration of one of the transmission transistors TG, which includes two buried gate electrode sections VG.

[0198] However, the number of buried gate electrode portions VG included in a single transmission transistor TG is not limited to two, and can also be other numbers. For example, such as Figure 19 As shown, the number of buried gate electrode portions VG included in the transmission transistor TG can be one. Alternatively, although not shown, the number of buried gate electrode portions VG included in the transmission transistor TG can be three or more. The planar shape of the buried gate electrode portion VG is not limited to a circle, and can also be a polygon such as a quadrilateral or an octagon (including shapes with rounded corners).

[0199] <15. Example of charge discharge transistor arrangement>

[0200] exist Figure 13 The first circuit configuration example shown and Figure 14 In the second circuit configuration example shown, the configuration of pixel 10 including charge discharge transistor OFG has been explained.

[0201] Figure 20 This is a plan view showing an example arrangement of a charge discharge transistor (OFG).

[0202] Due to such Figure 13 and Figure 14 As shown in the circuit configuration, the charge discharge transistor OFG is connected to the photodiode 41 and the transfer transistors TG1 and TG2, therefore, as Figure 20As shown, the charge-exhaust transistor OFG is arranged near the photogate electrode PG. More specifically, transport transistors TG1 and TG2 can be configured on two opposite sides of a quadrilateral surrounding the central photogate electrode PG, and the charge-exhaust transistor OFG can be configured on one of the remaining two opposite sides of the quadrilateral. The charge-exhaust transistor OFG can be a vertical transistor, which includes a buried gate electrode portion VG similar to that of the transport transistor TG. On the outer side of the charge-exhaust transistor OFG opposite to the photogate electrode PG side, a drain region OFD is formed by a high-concentration n-type semiconductor region, to which unwanted charge is discharged.

[0203] In addition, for charge discharge transistors OFG, such as Figure 21 As shown, two charge discharge transistors OFG1 and OFG2 can be configured symmetrically, similar to two transmission transistors TG1 and TG2. In this case, the charge discharge transistors OFG1 and OFG2 are arranged on two sides of the quadrilateral surrounding the central photogate electrode PG, which are different from the sides where the transmission transistors TG1 and TG2 are located.

[0204] <16. Examples of other pixel transistor arrangements>

[0205] Figure 22 It is shown in pixels such as Figure 14 The plan view shows an example of the arrangement of the pixel transistors in pixel 10, excluding the first transmission transistors TG1 and TG2, in the configuration indicated by the second circuit configuration example shown.

[0206] Figure 22 Each pixel transistor shown corresponds to Figure 14 The pixel transistors shown in the second circuit configuration example are given the same reference numerals.

[0207] The arrangement of the first transfer transistors TG1 and TG2, the memories MEM1 and MEM2, the second transfer transistors MTR1 and MTR2, and the floating diffusion regions FD1 and FD2 is similar to that of the reference. Figure 15 The first arrangement example is described above, and therefore its description is omitted. Furthermore, since the arrangement of the charge discharge transistor OFG is similar to the reference... Figure 20 The arrangement described herein is therefore omitted from the description.

[0208] In a region near the outermost pixel boundary, where memories MEM1 and MEM2, floating diffusion regions FD1 and FD2, etc., are configured, an amplifying transistor AMP, a selecting transistor SEL, a switching transistor FDG, and a reset transistor RST are arranged. The amplifying transistor AMP and the selecting transistor SEL are arranged side-by-side near a predetermined edge of the quadrilateral pixel region (in... Figure 22 In the region (middle, top), the switching transistor FDG and the reset transistor RST are arranged side by side on another predetermined side near the quadrilateral pixel region (in Figure 22 In the area (middle, bottom).

[0209] Figure 22 The pixel transistor arrangement shown is an example of a situation where the amplifying transistor AMP, the selection transistor SEL, the switching transistor FDG, and the reset transistor RST are contained in the pixel cell, but these pixel transistors can be shared by multiple pixels.

[0210] Figure 23 This is a plan view showing an example arrangement of the amplification transistor AMP, the selection transistor SEL, the switching transistor FDG, and the reset transistor RST when each pixel transistor is shared by multiple pixels.

[0211] exist Figure 23 In the example, the amplifying transistor AMP, the selecting transistor SEL, the switching transistor FDG, and the reset transistor RST are shared by four pixels. Any one of the amplifying transistor AMP, the selecting transistor SEL, the switching transistor FDG, and the reset transistor RST is configured in each of the four pixels 10 arranged in a 2x2 pattern as shared units.

[0212] Note that the shared unit of a shared pixel transistor is not limited to four pixels; the pixel transistor can be shared by a different number of pixels (e.g., eight pixels). Furthermore, even if the shared unit is four pixels, for example, the pixel transistor can be shared by four pixels arranged in a 1x4 configuration, i.e., one pixel in one direction (horizontal and vertical) and four pixels in the other direction, instead of four pixels arranged in a 2x2 configuration.

[0213] <17. Application Examples of Optical Detection Devices>

[0214] The light detection device 1 constructed as described above can be used not only as a light receiving device for a ranging system that measures the distance to a subject using an indirect ToF method, but also as a solid-state imaging device that detects the distribution of incident infrared or visible light and captures that distribution as an image.

[0215] <18. Examples of the Structure of Electronic Devices>

[0216] For example, the aforementioned light detection device 1 can be installed on electronic devices such as smartphones, head-mounted displays, tablet terminals, mobile phones, personal computers, game consoles, television receivers, wearable terminals, digital cameras, or digital video cameras.

[0217] Figure 24 This is a block diagram illustrating an example of the configuration of a smartphone, which is an electronic device equipped with a light detection device 1.

[0218] like Figure 24 As shown, the smartphone 201 is configured by connecting the ranging module 202, imaging device 203, display 204, speaker 205, microphone 206, communication module 207, sensor unit 208, touch panel 209, and control unit 210 via a bus 211. Furthermore, the control unit 210 executes programs using a CPU, thus functioning as an application processing unit 221 and an operating system processing unit 222.

[0219] The ranging module 202 may include Figure 1 The light detection device 1 and the light source emitting active light are described. The ranging module 202 receives reflected light, that is, light emitted from a predetermined light source and reflected by an object, and outputs a depth image in which the distance information to the object is stored as a depth value. For example, the ranging module 202 is disposed in front of the smartphone 201, measures the distance to the user of the smartphone 201, and outputs the depth value of the surface shape of the user's face, hands, fingers, etc. as the ranging result.

[0220] The imaging device 203 is positioned in front of the smartphone 201 and captures an image of the user of the smartphone 201 as the subject, so as to obtain an image of the user. Figure 1 The light detection device 1 can be used as the imaging device 203. Note that, although not shown, at least one of the ranging module 202 and the imaging device 203 can also be configured on the back of the smartphone 201.

[0221] The display 204 displays an operation screen for processing performed by the application processing unit 221 and the operating system processing unit 222, images captured by the imaging device 203, and the like. For example, the speaker 205 and microphone 206 output the other party's voice and collect the user's voice when making a phone call using the smartphone 201.

[0222] The communication module 207 performs communication via a communication network. The sensor unit 208 senses speed, acceleration, proximity, etc., and the touch panel 209 receives touch operations performed by the user on the operation screen displayed on the display 204.

[0223] Application processing unit 221 performs processing for providing various services on smartphone 201. For example, application processing unit 221 can perform processing for creating a face and displaying it on display 204 by virtually reproducing the user's facial expression based on computer graphics provided by the ranging module 202. Furthermore, for example, application processing unit 221 can perform processing for creating three-dimensional shape data of arbitrary three-dimensional objects based on the depth provided by the ranging module 202.

[0224] The operating system processing unit 222 performs processing for implementing the basic functions and operations of the smartphone 201. For example, the operating system processing unit 222 may perform processing for authenticating the user's face and unlocking the smartphone 201 based on depth values ​​provided from the ranging module 202. Furthermore, for example, the operating system processing unit 222 may perform processing for recognizing the user's gestures based on the depth values ​​provided from the ranging module 202, and processing for inputting one of various operations based on the gestures.

[0225] In the smartphone 201 configured as described above, for example, it is possible to calculate and output ranging information or output captured images of infrared or visible light by applying the light detection device 1 described above.

[0226] <19. Examples of Applications of Moving Bodies>

[0227] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology according to the Technology disclosed can be implemented as a device installed on any of the following types of mobile bodies: automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, unmanned aerial vehicles, ships, robots, etc.

[0228] Figure 25 This is a block diagram illustrating an example of the schematic configuration of a vehicle control system, which is an example of a mobile body control system to which the technology of the embodiments of this disclosure can be applied.

[0229] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 25 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional components of the comprehensive control unit 12050.

[0230] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for the following devices: a drive force generating device, such as an internal combustion engine or a drive motor, for generating the driving force of the vehicle; a drive force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle.

[0231] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves or signals from various switches transmitted from a portable device that serves as a substitute for a key can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0232] The exterior information detection unit 12030 detects information about the exterior of the vehicle having the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform detection processing for objects such as people, vehicles, obstacles, markings, or symbols on the road surface, or detection processing for the distance to these objects.

[0233] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output an electrical signal as an image, or it can output an electrical signal as information about the measured distance. Furthermore, the light received by imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0234] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0235] The microcomputer 12051 can calculate target control values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior or exterior (obtained by the exterior information detection unit 12030 or the interior information detection unit 12040), and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control aimed at realizing the functions of an advanced driver assistance system (ADAS), including: collision avoidance or impact mitigation, following distance based on the vehicle's distance, vehicle speed maintenance, collision warning, or lane departure warning, etc.

[0236] Furthermore, the microcomputer 12051 can perform cooperative control designed for autonomous driving, enabling the vehicle to drive autonomously by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the inside or outside of the vehicle (which is obtained by the external information detection unit 12030 or the internal information detection unit 12040), without relying on the driver's operation.

[0237] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the vehicle's exterior (obtained by the exterior information detection unit 12030). For example, the microcomputer 12051 can perform coordinated control aimed at preventing glare by controlling the headlights to switch from high beams to low beams, based on the position of the vehicle ahead or oncoming vehicle detected by the exterior information detection unit 12030.

[0238] The sound / image output unit 12052 transmits at least one output signal of sound and image to an output device capable of visually or audibly notifying passengers of the vehicle or the outside of the vehicle. Figure 25 In the example, audio speaker 12061, display unit 12062, and instrument panel 12063 are shown as output devices. For example, display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0239] Figure 26 This is a diagram showing an example of the mounting position of the imaging unit 12031.

[0240] exist Figure 26 In the vehicle 12100, imaging units 12101, 12102, 12103, 12104 and 12105 are imaging units 12031.

[0241] Imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, installed on the front nose, side mirrors, rear bumper, rear door, and upper part of the interior windshield of vehicle 12100. Imaging unit 12101 installed on the front nose and imaging unit 12105 installed on the upper part of the interior windshield primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 installed on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 installed on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. The front images acquired by imaging units 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, or lanes ahead.

[0242] Notice, Figure 26 An example of the imaging range of imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging unit 12101 installed on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 installed on the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 installed on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a top-down image of the vehicle 12100 as viewed from above is obtained.

[0243] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0244] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104, thereby extracting the nearest three-dimensional object as the vehicle ahead. Specifically, this three-dimensional object exists on the driving path of the vehicle 12100 and is traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can set the following distance to be maintained between the vehicle in front and the vehicle ahead, and perform automatic braking control (including following stop control) or automatic acceleration control (including following start control), etc. Therefore, cooperative control intended for autonomous driving can be performed, enabling the vehicle to drive autonomously without relying on driver operation, etc.

[0245] For example, microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, microcomputer 12051 determines the collision risk, which represents the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and performs forced deceleration or evasive steering through drive system control unit 12010. Microcomputer 12051 can thus assist in driving to avoid collision.

[0246] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by a procedure that extracts feature points from the images captured by the imaging units 12101 to 12104 (which are infrared cameras) and by a procedure that determines whether a person is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 so that an icon or the like representing a pedestrian is displayed at a desired location.

[0247] Examples of vehicle control systems to which the technology of this disclosure can be applied have been described above. The technology of this disclosure can be applied to the external information detection unit 12030 and the internal information detection unit 12040 in the above configuration. More specifically, by utilizing the light detection device 1 as a distance measurement for both the external information detection unit 12030 and the internal information detection unit 12040, processing for recognizing driver gestures can be performed, and various operations (e.g., audio system, navigation system, and air conditioning system) can be executed based on the gestures, thus more accurately detecting the driver's state. Furthermore, the unevenness of the road surface can be identified using the distance measurement performed by the light detection device 1 or the image captured by the light detection device 1, and the identified unevenness can be reflected in the suspension control.

[0248] The embodiments disclosed herein are not limited to the above embodiments, and various modifications can be made without departing from the technical points of this disclosure.

[0249] For example, a pattern that combines all or part of the above-mentioned constituent examples can be adopted.

[0250] Note that the effects described in this specification are merely illustrative and not limiting, and there may be effects other than those described in this specification.

[0251] Note that the technology disclosed herein may have the following configuration.

[0252] (1) A light detection device, comprising:

[0253] The photogate electrode is disposed above the photodiode; and

[0254] One or more transfer transistors transfer the charge obtained by the photoelectric conversion performed by the photodiode to a charge storage cell, wherein

[0255] The transmission transistor is a vertical transistor, and each of the vertical transistors includes a buried gate electrode portion in which the gate electrode is embedded in the semiconductor substrate.

[0256] (2) The optical detection device according to (1), wherein

[0257] When the arrangement direction of the photogate electrode and the transmission transistor is defined as a first direction, in a second direction perpendicular to the first direction, the width of the photogate electrode is formed to be equal to or less than the width of the transmission transistor.

[0258] (3) The optical detection device according to (1) or (2), wherein

[0259] The transmission transistors each include two of the buried gate electrode portions, and

[0260] When the arrangement direction of the photogate electrode and the transmission transistor is defined as a first direction, in a second direction perpendicular to the first direction, the width of the photogate electrode is formed to be smaller than the width of the two embedded gate electrode portions of each of the transmission transistors.

[0261] (4) The light detection device according to any one of (1) to (3), wherein

[0262] The photogate electrode is a vertical gate electrode, which includes an embedded gate electrode portion embedded in the semiconductor substrate.

[0263] (5) The optical detection device according to (4), wherein

[0264] Regarding the depth in the thickness direction of the substrate, the buried gate electrode portion of the photogate electrode is formed to be shorter than the buried gate electrode portion of each of the transmission transistors.

[0265] (6) The light detection device according to any one of (1) to (5), wherein

[0266] A first voltage or a second voltage is applied to the photograting electrode.

[0267] (7) The optical detection device according to (6), wherein

[0268] During a cutoff period in which one or more of the transmission transistors are turned off, the first voltage is applied to the photogate electrode, and

[0269] The first voltage is a voltage higher than the cutoff voltage used to turn off the transmission transistor.

[0270] (8) The optical detection device according to (6) or (7), wherein

[0271] During a drive period in which two or more of the transmission transistors are alternately turned on, the second voltage is applied to the photogate electrode, and

[0272] The second voltage is equal to or less than the turn-on voltage used to turn on the transmission transistor.

[0273] (9) The light detection device according to any one of (1) to (8), wherein

[0274] Two or four of the aforementioned transmission transistors are provided for each pixel.

[0275] (10) The light detection apparatus according to any one of (1) to (9), wherein

[0276] The charge storage unit includes a floating diffusion region or a MIS capacitor.

[0277] (11) A light detection device, comprising:

[0278] The photogate electrode is disposed above the photodiode; and

[0279] One or more transfer transistors transfer the charge obtained by the photoelectric conversion performed by the photodiode to a charge storage cell, wherein

[0280] The photogate electrode is a vertical transistor, which includes an embedded gate electrode portion embedded in a semiconductor substrate.

[0281] (12) The optical detection device according to (11), wherein

[0282] The transmission transistor is a vertical transistor, and each vertical transistor includes a buried gate electrode portion in which the gate electrode is embedded in a semiconductor substrate.

[0283] (13) The optical detection device according to (12), wherein

[0284] When the arrangement direction of the photogate electrode and the transmission transistor is defined as a first direction, in a second direction perpendicular to the first direction, the width of the photogate electrode is formed to be equal to or less than the width of the transmission transistor.

[0285] (14) The optical detection device according to (12) or (13), wherein

[0286] The transmission transistors each include two buried gate electrode portions, and

[0287] When the arrangement direction of the photogate electrode and the transmission transistor is defined as a first direction, in a second direction perpendicular to the first direction, the width of the photogate electrode is formed to be smaller than the width of the two embedded gate electrode portions of each transmission transistor.

[0288] (15) The light detection apparatus according to any one of (12) to (14), wherein

[0289] Regarding the depth in the thickness direction of the substrate, the buried gate electrode portion of the photogate electrode is formed to be shorter than the buried gate electrode portion of each of the transmission transistors.

[0290] (16) The light detection apparatus according to any one of (11) to (15), wherein

[0291] A first voltage or a second voltage is applied to the photogate electrode.

[0292] (17) The optical detection device according to (16), wherein

[0293] During a cutoff period in which one or more of the transmission transistors are turned off, the first voltage is applied to the photogate electrode, and

[0294] The first voltage is a voltage higher than the cutoff voltage used to turn off the transmission transistor.

[0295] (18) The optical detection device according to (16) or (17), wherein

[0296] During a drive period in which two or more of the transmission transistors are alternately turned on, the second voltage is applied to the photogate electrode, and

[0297] The second voltage is equal to or less than the turn-on voltage used to turn on the transmission transistor.

[0298] List of reference numerals

[0299] 1. Optical detection device

[0300] 10 pixels

[0301] 40 Semiconductor substrate

[0302] 41 Photodiode

[0303] 51, 51' gate electrode

[0304] 51P planar grid electrode section

[0305] 51VG Embedded Gate Electrode Section

[0306] 52, 52' gate electrode

[0307] 52P planar grid electrode section

[0308] 52VG Embedded Gate Electrode Section

[0309] 61P' Planar Grid Electrode Section

[0310] 61VG' Embedded Gate Electrode Section

[0311] 83 Gate electrode

[0312] 93 Gate electrode

[0313] 101 gate electrode

[0314] 111 Gate electrode

[0315] 201 Smartphones

[0316] 202 Distance Measuring Module

[0317] 203 Imaging Device

[0318] PG, PG' photograting electrodes

[0319] TG, TG' transfer transistors

[0320] FD floating diffusion region

[0321] FDG switching transistor

[0322] FDL Additional Capacitors

[0323] MEM memory

[0324] MTR Second Transmission Transistor

[0325] AMP amplification transistor

[0326] RST reset transistor

[0327] OFG charge discharge transistor

Claims

1. A light detection device, comprising: a photogate electrode disposed above the photodiode; and one or more transfer transistors that transfer the charge obtained by the photoelectric conversion performed by the photodiode to a charge storage unit, wherein The transfer transistors are vertical transistors, each of which includes a buried gate electrode portion in which a gate electrode is buried in a semiconductor substrate.

2. The light detection device according to claim 1, wherein When the arrangement direction of the photogate electrode and the transfer transistor is defined as a first direction, the width of the photogate electrode is formed to be equal to or smaller than the width of the transfer transistor in a second direction perpendicular to the first direction.

3. The light detection device according to claim 1, wherein The transfer transistors each include two of the buried gate electrode portions, and When the arrangement direction of the photogate electrode and the transfer transistor is defined as a first direction, in a second direction perpendicular to the first direction, the width of the photogate electrode is formed to be smaller than the width of the two buried gate electrode portions of each of the transfer transistors.

4. The light detection device according to claim 1, wherein The photogate electrode is a vertical gate electrode including a buried gate electrode portion buried in the semiconductor substrate.

5. The light detection device according to claim 4, wherein The buried gate electrode portion of the photo gate electrode is formed to be shorter than the buried gate electrode portion of each of the transfer transistors in terms of depth in the substrate thickness direction.

6. The light detection device according to claim 1, wherein A first voltage or a second voltage is applied to the photogate electrode.

7. The light detection device according to claim 6, wherein During a turn-off period in which one or more of the transfer transistors are turned off, the first voltage is applied to the photogate electrode, and The first voltage is a voltage higher than a turn-off voltage for turning off the transfer transistor.

8. The light detection device according to claim 6, wherein During a driving period in which two or more of the transfer transistors are alternately turned on, the second voltage is applied to the photogate electrode, and The second voltage is a voltage equal to or lower than an on-voltage for turning on the pass transistor.

9. The light detection device according to claim 1, wherein Two or four transfer transistors are provided for one pixel.

10. The light detection device according to claim 1, wherein The charge storage unit includes a floating diffusion region or a MIS capacitor.

11. A light detection device, comprising: a photogate electrode disposed above the photodiode; and one or more transfer transistors that transfer the charge obtained by the photoelectric conversion performed by the photodiode to a charge storage unit, wherein The photogate electrode is a vertical transistor including a buried gate electrode portion buried in a semiconductor substrate.

12. The light detection device according to claim 11, wherein The transfer transistors are vertical transistors each including a buried gate electrode portion in which a gate electrode is buried in a semiconductor substrate.

13. The light detection device according to claim 12, wherein When the arrangement direction of the photogate electrode and the transfer transistor is defined as a first direction, the width of the photogate electrode is formed to be equal to or smaller than the width of the transfer transistor in a second direction perpendicular to the first direction.

14. The light detection device according to claim 12, wherein The transfer transistors each include two buried gate electrode portions, and When the arrangement direction of the photogate electrode and the transfer transistor is defined as a first direction, the width of the photogate electrode in a second direction perpendicular to the first direction is formed to be smaller than the width of two buried gate electrode portions of each of the transfer transistors.

15. The light detection device according to claim 12, wherein The buried gate electrode portion of the photo gate electrode is formed to be shorter than the buried gate electrode portion of each of the transfer transistors in terms of depth in the substrate thickness direction.

16. The light detection device according to claim 11, wherein A first voltage or a second voltage is applied to the photogate electrode.

17. The light detection device according to claim 16, wherein During a turn-off period in which one or more of the transfer transistors are turned off, the first voltage is applied to the photogate electrode, and The first voltage is a voltage higher than a turn-off voltage for turning off the transfer transistor.

18. The light detection device according to claim 16, wherein During a driving period in which two or more of the transfer transistors are alternately turned on, the second voltage is applied to the photogate electrode, and The second voltage is a voltage equal to or lower than an on-voltage for turning on the pass transistor.

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