Method and device for measuring threshold voltage of field effect transistor

Abstract

The invention relates to the technical field of semiconductors, and provides a threshold voltage measurement method and device for a field effect transistor, and the method comprises the steps: applying a grid voltage to a to-be-measured field effect transistor based on an initial grid voltage incremental algorithm, and obtaining a first grid voltage-drain current change curve corresponding to the initial grid voltage incremental algorithm; applying a gate voltage to the field effect transistor to be tested based on a reverse gate voltage decline algorithm corresponding to the initial gate voltage decline algorithm, and obtaining a second gate voltage-drain current change curve corresponding to the reverse gate voltage decline algorithm; a threshold voltage is determined based on the first gate voltage-drain current curve and the second gate voltage-drain current curve. According to the method, the limitation that the threshold voltage is measured depending on a simple grid voltage increasing process in the prior art is overcome, and the accuracy of a threshold voltage measurement result is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method and device for measuring the threshold voltage of a field effect transistor. Background Art

[0002] Field effect transistors are widely used in electronic circuits as switches or amplifiers, and one of the important parameters of their operating characteristics is the threshold voltage. Accurately measuring the threshold voltage of field effect transistors is crucial for circuit design and optimization.

[0003] Existing threshold voltage measurement methods usually rely on a simple gate voltage increment process, which determines the threshold voltage by observing the change in drain current by gradually increasing the gate voltage. However, the measurement accuracy of this method is not high. Summary of the invention

[0004] The present application provides a method and device for measuring the threshold voltage of a field effect transistor, aiming to solve the problems raised by the above-mentioned background technology.

[0005] In a first aspect, the present application provides a method for measuring a threshold voltage of a field effect transistor, comprising: Applying a gate voltage to the field effect transistor to be tested based on an initial gate voltage increasing algorithm, and obtaining a first gate voltage-drain current variation curve corresponding to the initial gate voltage increasing algorithm; Applying a gate voltage to the field effect transistor to be tested based on a reverse gate voltage decreasing algorithm corresponding to the initial gate voltage increasing algorithm, and obtaining a second gate voltage-drain current variation curve corresponding to the reverse gate voltage decreasing algorithm; Determining whether a similarity between the first gate voltage-drain current variation curve and the second gate voltage-drain current variation curve is greater than a preset similarity; If yes, the threshold voltage corresponding to the field effect transistor to be tested is determined based on the first gate voltage-drain current variation curve.

[0006] In a possible implementation manner, after determining whether the first gate voltage-drain current variation curve is consistent with the second gate voltage-drain current variation curve, the method further includes: If not, adjusting the initial gate voltage increasing algorithm based on the similarity to obtain a target gate voltage increasing algorithm; Applying a gate voltage to the field effect transistor to be tested based on the target gate voltage increasing algorithm, and obtaining a latest first gate voltage-drain current variation curve corresponding to the target gate voltage increasing algorithm; Applying a gate voltage to the field effect transistor to be tested based on a target reverse gate voltage decreasing algorithm corresponding to the target gate voltage increasing algorithm, and obtaining a latest second gate voltage-drain current variation curve corresponding to the target reverse gate voltage decreasing algorithm; Determining whether the similarity between the latest first gate voltage-drain current change curve and the latest second gate voltage-drain current change curve is greater than a preset similarity; The above method steps are iterated until the similarity is greater than the preset similarity, and the threshold voltage corresponding to the field effect transistor to be tested is determined based on the latest first gate voltage-drain current change curve.

[0007] In a possible implementation, applying a gate voltage to the field effect transistor to be tested based on an initial gate voltage increasing algorithm includes: Obtaining the initial current threshold of the drain current of the field effect transistor to be tested; Applying a gate voltage to the field effect transistor to be tested based on a first preset gate step voltage starting from an initial gate voltage, and in the process of applying the gate voltage to the field effect transistor to be tested based on the first preset gate step voltage, determining in real time whether a difference between the initial current threshold and the drain current is less than a preset threshold; If yes, a gate voltage is applied to the field effect transistor to be tested based on a second preset gate step voltage, and in the process of applying the gate voltage to the field effect transistor to be tested based on the second preset gate step voltage, it is determined in real time whether the drain current is greater than the initial current threshold; wherein the second preset gate step voltage is less than the first preset gate step voltage; If so, a gate voltage is applied to the field effect transistor to be tested until the maximum gate voltage is reached based on a third preset gate step voltage; wherein the third preset gate step voltage is less than the second preset gate step voltage.

[0008] In a possible implementation, the step of obtaining the initial current threshold of the drain current of the field effect transistor to be tested includes: Applying a drain voltage to the field effect transistor to be tested based on a preset drain step voltage, and in the process of applying the drain voltage to the field effect transistor to be tested, determining the drain voltage corresponding to the starting point where the drain current is not 0 as a reference drain voltage; The sum of the reference drain voltage and the preset voltage increment is determined as the target drain voltage, a drain voltage is applied to the field effect transistor to be tested based on the target drain voltage, and a drain current corresponding to the target drain voltage is determined as the initial current threshold.

[0009] In a possible implementation, the method further includes: Obtaining the identification code of the field effect transistor to be tested; The identification code is bound to the threshold voltage to obtain a binding result, and the binding result is stored in a database.

[0010] In a possible implementation manner, binding the identification code with the threshold voltage to obtain a binding result includes: Performing encoding operation on the threshold voltage based on a preset encoding algorithm to obtain a coding sequence; wherein the coding sequence does not include any character in the identification code; Generating an initial set based on each coded character of the coded sequence; Extracting each number in the identification code to obtain a number set, and extracting each letter in the identification code to obtain a letter set; Performing a Cartesian product operation on the initial set, the number set, and the letter set to obtain a plurality of target sets; Combining the target sets including the same coded character in each of the target sets to obtain a plurality of target set groups; The target set groups are arranged in sequence based on the sequence of the coding characters corresponding to each target set group in the coding sequence to obtain a target set group sequence; the target set group sequence is the binding result.

[0011] In a second aspect, the present application provides a threshold voltage measurement device for a field effect transistor, comprising: A first acquisition module, configured to apply a gate voltage to the field effect transistor to be tested based on an initial gate voltage increasing algorithm, and to obtain a first gate voltage-drain current variation curve corresponding to the initial gate voltage increasing algorithm; A second acquisition module is used to apply a gate voltage to the field effect transistor to be tested based on a reverse gate voltage decreasing algorithm corresponding to the initial gate voltage increasing algorithm, and obtain a second gate voltage-drain current variation curve corresponding to the reverse gate voltage decreasing algorithm; A judging module, used for judging whether the similarity between the first gate voltage-drain current variation curve and the second gate voltage-drain current variation curve is greater than a preset similarity; A determination module is used to determine the threshold voltage corresponding to the field effect transistor to be tested based on the first gate voltage-drain current change curve when the similarity between the first gate voltage-drain current change curve and the second gate voltage-drain current change curve is greater than a preset similarity.

[0012] The present application provides a method and device for measuring the threshold voltage of a field effect transistor, wherein the method includes: applying a gate voltage to the field effect transistor to be measured based on an initial gate voltage increasing algorithm, and obtaining a first gate voltage-drain current change curve corresponding to the initial gate voltage increasing algorithm; applying a gate voltage to the field effect transistor to be measured based on a reverse gate voltage decreasing algorithm corresponding to the initial gate voltage increasing algorithm, and obtaining a second gate voltage-drain current change curve corresponding to the reverse gate voltage decreasing algorithm; judging whether the similarity between the first gate voltage-drain current change curve and the second gate voltage-drain current change curve is greater than a preset similarity; if so, determining the threshold voltage corresponding to the field effect transistor to be measured based on the first gate voltage-drain current change curve. This method overcomes the limitation of the prior art that the threshold voltage is measured by relying on a simple gate voltage increasing process, and improves the accuracy of the threshold voltage measurement result. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0014] Figure 1 A schematic diagram of a flow chart of a method for measuring the threshold voltage of a field effect transistor provided in an embodiment of the present application; Figure 2 A schematic block diagram of the structure of a field effect transistor threshold voltage measurement device provided in an embodiment of the present application; Figure 3 A schematic block diagram of the structure of a terminal device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all contents and operations / steps, nor must they be performed in the order described. For example, operations / steps may also be based on decomposition, combination or partial merging, so the order of actual execution may change based on actual conditions.

[0017] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0018] It should be further understood that the term “and / or” used in the specification and appended claims of this application refers to any combination of one or more of the associated listed items based on and including all possible combinations.

[0019] Field effect transistors are widely used in electronic circuits as switches or amplifiers, and one of the important parameters of their operating characteristics is the threshold voltage. Accurately measuring the threshold voltage of field effect transistors is crucial for circuit design and optimization.

[0020] Existing threshold voltage measurement methods usually rely on a simple gate voltage increment process, by gradually increasing the gate voltage to observe the change in drain current, and then determine the threshold voltage. However, the measurement accuracy of this method is not high. To this end, the present application provides a field effect transistor threshold voltage measurement method and device based on solving the above problems.

[0021] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0022] See also Figure 1 , Figure 1 A flow chart of a method for measuring the threshold voltage of a field effect transistor provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method for measuring the threshold voltage of a field effect transistor provided in the embodiment of the present application includes steps S1 to S4.

[0023] Step S1, applying a gate voltage to the field effect transistor to be tested based on an initial gate voltage increasing algorithm, and obtaining a first gate voltage-drain current variation curve corresponding to the initial gate voltage increasing algorithm.

[0024] Step S2, applying a gate voltage to the field effect transistor to be tested based on a reverse gate voltage decreasing algorithm corresponding to the initial gate voltage increasing algorithm, and obtaining a second gate voltage-drain current variation curve corresponding to the reverse gate voltage decreasing algorithm.

[0025] Step S3: determining whether the similarity between the first gate voltage-drain current variation curve and the second gate voltage-drain current variation curve is greater than a preset similarity.

[0026] Step S4: If yes, determine the threshold voltage corresponding to the field effect transistor to be tested based on the first gate voltage-drain current variation curve.

[0027] It should be noted that before executing the method of this embodiment, the field effect tube to be tested is connected to an automated testing device. Specifically, the source of the field effect tube to be tested is connected to a reference potential, the drain of the field effect tube to be tested is connected to an adjustable power supply, and the gate of the field effect tube to be tested is connected to an adjustable power supply. The graphic code on the field effect tube to be tested is scanned by a preset code scanning device to obtain an identification code of the field effect tube to be tested, and the specification information of the field effect tube to be tested is obtained in a database based on the identification code.

[0028] In this embodiment, as described in the above step S1, a gate voltage is applied to the field effect transistor to be tested based on an initial gate voltage increasing algorithm, and a first gate voltage-drain current variation curve corresponding to the initial gate voltage increasing algorithm is obtained.

[0029] Wherein, applying a gate voltage to the field effect transistor to be tested based on the initial gate voltage increasing algorithm includes: obtaining an initial current threshold of the drain current of the field effect transistor to be tested; applying a gate voltage to the field effect transistor to be tested based on a first preset gate step voltage starting from the initial gate voltage, and in the process of applying the gate voltage to the field effect transistor to be tested based on the first preset gate step voltage, judging in real time whether the difference between the initial current threshold and the drain current is less than the preset threshold; if so, applying a gate voltage to the field effect transistor to be tested based on a second preset gate step voltage, and in the process of applying the gate voltage to the field effect transistor to be tested based on the second preset gate step voltage, judging in real time whether the drain current is greater than the initial current threshold; wherein, the second preset gate step voltage is less than the first preset gate step voltage; if so, applying a gate voltage to the field effect transistor to be tested based on a third preset gate step voltage until the maximum gate voltage; wherein, the third preset gate step voltage is less than the second preset gate step voltage. Among them, the initial gate voltage, the first preset gate step voltage, the second preset gate step voltage and the third preset gate step voltage are all obtained from the specification information, the first preset gate step voltage is not greater than 0.1V, the second preset gate step voltage is not greater than 0.01V, and the second preset gate step voltage is not greater than 0.001V. It can be understood that the method provided in this embodiment realizes the refined management of the gate voltage application method, which helps to improve the accuracy of the measurement result.

[0030] Among them, the obtaining of the first gate voltage-drain current change curve corresponding to the initial gate voltage increasing algorithm includes: in the process of applying the gate voltage to the field effect transistor to be tested based on the initial gate voltage increasing algorithm, obtaining the drain current corresponding to each first gate voltage of the initial gate voltage increasing algorithm; and drawing the first gate voltage-drain current change curve based on the drain current corresponding to each first gate voltage.

[0031] Furthermore, the step of obtaining the initial current threshold of the drain current of the field effect transistor to be tested includes: Based on the preset drain step voltage, a drain voltage is applied to the field effect transistor to be tested, and in the process of applying the drain voltage to the field effect transistor to be tested, the drain voltage corresponding to the starting point where the drain current is not 0 is determined as the reference drain voltage; the sum of the reference drain voltage and the preset voltage increment is determined as the target drain voltage, and based on the target drain voltage, a drain voltage is applied to the field effect transistor to be tested, and the drain current corresponding to the target drain voltage is determined as the initial current threshold. Wherein, the preset voltage increment is not greater than 0.0001V. It can be understood that when the preset voltage increment is not greater than 0.0001V, the initial current threshold can be made as small as possible, thereby improving the accuracy of the measurement result.

[0032] As described in the above step S2, a gate voltage is applied to the field effect transistor to be tested based on the reverse gate voltage decreasing algorithm corresponding to the initial gate voltage increasing algorithm, and a second gate voltage-drain current change curve corresponding to the reverse gate voltage decreasing algorithm is obtained. Specifically, after the gate voltage is applied to the field effect transistor to be tested based on the initial gate voltage increasing algorithm, a reverse gate voltage decreasing algorithm corresponding to the initial gate voltage increasing algorithm is generated to apply a gate voltage to the field effect transistor to be tested, and in the process of applying the gate voltage to the field effect transistor to be tested based on the reverse gate voltage decreasing algorithm, the drain current corresponding to each second gate voltage of the reverse gate voltage decreasing algorithm is obtained; and the first gate voltage-drain current change curve is drawn based on the drain current corresponding to each second gate voltage.

[0033] As described in the above step S3, it is determined whether the similarity between the first gate voltage-drain current change curve and the second gate voltage-drain current change curve is greater than a preset similarity. Specifically, the first gate voltage-drain current change curve is input into a preset curve feature extraction model to obtain a first feature vector, and the second gate voltage-drain current change curve is input into the curve feature extraction model to obtain a second feature vector; the cosine value of the first feature vector and the second feature vector is used as the similarity; and it is determined whether the similarity is greater than a preset similarity.

[0034] As described in step S4 above, if the similarity is greater than the preset similarity, the threshold voltage corresponding to the field effect transistor to be tested is determined based on the first gate voltage-drain current change curve. Specifically, an elbow analysis operation is performed on the first gate voltage-drain current change curve to determine that the gate voltage corresponding to the point where the drain current significantly increases on the first gate voltage-drain current change curve is the threshold voltage.

[0035] The method provided in this embodiment overcomes the limitation of the prior art that the threshold voltage is measured by relying on a simple gate voltage increasing process, by determining the threshold voltage corresponding to the field effect transistor to be tested based on the first gate voltage-drain current change curve when the similarity is greater than a preset similarity, and improves the accuracy of the threshold voltage measurement result.

[0036] In some embodiments, after determining whether the first gate voltage-drain current variation curve is consistent with the second gate voltage-drain current variation curve, the method further includes: If not, adjusting the initial gate voltage increasing algorithm based on the similarity to obtain a target gate voltage increasing algorithm; specifically, the ratio of the voltage increasing rate corresponding to the target gate voltage increasing algorithm to the voltage increasing rate corresponding to the initial gate voltage increasing algorithm is the similarity; Applying a gate voltage to the field effect transistor to be tested based on the target gate voltage increasing algorithm, and obtaining a latest first gate voltage-drain current variation curve corresponding to the target gate voltage increasing algorithm; Applying a gate voltage to the field effect transistor to be tested based on a target reverse gate voltage decreasing algorithm corresponding to the target gate voltage increasing algorithm, and obtaining a latest second gate voltage-drain current variation curve corresponding to the target reverse gate voltage decreasing algorithm; Determining whether the similarity between the latest first gate voltage-drain current change curve and the latest second gate voltage-drain current change curve is greater than a preset similarity; The above method steps are iterated until the similarity is greater than the preset similarity, and the threshold voltage corresponding to the field effect transistor to be tested is determined based on the latest first gate voltage-drain current change curve.

[0037] It should be noted that the iterative steps of the above method refer to iteratively adjusting the initial gate voltage increasing algorithm based on the similarity in this embodiment to obtain a target gate voltage increasing algorithm and subsequent steps.

[0038] The method provided in this embodiment realizes refined control of the gate voltage increasing algorithm when the similarity is not greater than the preset similarity, and realizes accurate measurement of the threshold voltage by reducing the increasing speed of the gate voltage during the increasing process of the gate voltage.

[0039] In some embodiments, the method further comprises: Obtaining the identification code of the field effect transistor to be tested; The identification code is bound to the threshold voltage to obtain a binding result, and the binding result is stored in a database.

[0040] In this embodiment, the binding of the identification code with the threshold voltage to obtain a binding result includes: performing an encoding operation on the threshold voltage based on a preset encoding algorithm to obtain a coding sequence; wherein the coding sequence does not include any character in the identification code; generating an initial set based on each coded character of the coding sequence, for example, if the coding sequence is ηζγ, then the initial set is (η, ζ, γ); extracting each number in the identification code to obtain a number set, and extracting each letter in the identification code to obtain a letter set, for example, if the identification code is W2U68B, then the number set is (2, 6, 8), and the letter set is (W, U, B); performing a Cartesian product operation on the initial set, the number set, and the letter set to obtain multiple target sets; combining the target sets including the same coded character in each of the target sets to obtain multiple target set groups; The target set groups are arranged in sequence based on the sequence of the coded characters corresponding to each target set group in the coded sequence to obtain a target set group sequence; the target set group sequence is the binding result. The Cartesian product operation refers to the operation of the set of all possible ordered pairs in two or two sets. Exemplarily, the initial set is (η, ζ, γ), the number set is (2, 6, 8), and the letter set is (W, U, B). Cartesian operations on (η, ζ, γ), (2, 6, 8), and (W, U, B) are as follows: (η, 2, W), (η, 2, U), (η, 2, B), (η, 6, W), (η, 6, U), (η, 6, B), (η, 8, W), (η, 8, U), (η, 8, B), (ζ, 2, W), (ζ, 2, U), (ζ, 2, B), (ζ, 6, W), (ζ, 6, U), (ζ, 6, B), (ζ, 8, W), (ζ, 8, U), (ζ, 8, B), (γ, 2, W), (γ, 2, U), (γ, 2, B), (γ, 6, W), (γ, 6, U), (γ, 6, B), (γ, 8, W), (γ, 8, U), (γ, 8, B), then the target set group sequence is {(n, 2, W), (n, 2, U), (n, 2 , B), (eta, 6, W), (eta, 6, U), (eta, 6, B), (eta, 8, W), (eta, 8, U), (eta, 8, B)}; {(ζ, 2, W), (ζ, 2, U), (ζ,2,B), (ζ,6,W), (ζ,6,U), (ζ,6,B), (ζ,8,W), (ζ,8,U), (ζ,8,B)}; {(γ,2,W ), (γ,2,U), (γ,2,B), (γ,6,W), (γ,6,U), (γ,6,B), (γ,8,W), (γ,8,U), (γ,8,B)}.

[0041] The method provided in this embodiment, on the one hand, realizes encryption processing of the threshold voltage by encoding operation on the threshold voltage, and on the other hand, realizes orderliness of binding results by arranging target set groups in sequence to generate target set group sequences, which helps to improve the efficiency of data storage and retrieval and facilitates subsequent fast query and matching operations.

[0042] See also Figure 2 , Figure 2 A schematic block diagram of the structure of a field effect transistor threshold voltage measurement device 100 provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, a threshold voltage measuring device 100 of a field effect transistor includes: The first acquisition module 110 is used to apply a gate voltage to the field effect transistor to be tested based on an initial gate voltage increasing algorithm, and to obtain a first gate voltage-drain current variation curve corresponding to the initial gate voltage increasing algorithm.

[0043] The second acquisition module 120 is used to apply a gate voltage to the field effect transistor to be tested based on a reverse gate voltage decreasing algorithm corresponding to the initial gate voltage increasing algorithm, and obtain a second gate voltage-drain current variation curve corresponding to the reverse gate voltage decreasing algorithm.

[0044] The judgment module 130 is used to judge whether the similarity between the first gate voltage-drain current change curve and the second gate voltage-drain current change curve is greater than a preset similarity.

[0045] The determination module 140 is used to determine the threshold voltage corresponding to the field effect transistor to be tested based on the first gate voltage-drain current change curve when the similarity between the first gate voltage-drain current change curve and the second gate voltage-drain current change curve is greater than a preset similarity.

[0046] It should be noted that, technical personnel in the relevant technical field can clearly understand that for the convenience and conciseness of description, the specific working process of the above-described device and each module can be based on the corresponding process in the embodiment of the threshold voltage measurement method of the aforementioned field effect transistor, and will not be repeated here.

[0047] The terminal device 200 provided in the above embodiment can be implemented in the form of a computer program. The computer program can be based on Figure 3 The system is run on the terminal device 200 shown.

[0048] See also Figure 3 , Figure 3 The present application provides a schematic block diagram of the structure of a terminal device 200, wherein the terminal device 200 includes a processor 201 and a memory 202, wherein the processor 201 and the memory 202 are connected via a device bus 203, wherein the memory 202 may be based on a non-volatile storage medium and an internal memory.

[0049] The non-volatile storage medium can store a computer program. The computer program includes program instructions, and when the program instructions are executed by the processor 201, the processor 201 can execute any of the above-mentioned methods for measuring the threshold voltage of a field effect transistor.

[0050] The processor 201 is used to provide computing and control capabilities to support the operation of the entire terminal device 200.

[0051] The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium. When the computer program is executed by the processor 201, the processor 201 can execute any of the above-mentioned methods for measuring the threshold voltage of the field effect transistor.

[0052] Those skilled in the art can understand that Figure 3 The structure shown in the figure is only a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the terminal device 200 involved in the scheme of the present application. The specific terminal device 200 may be based on including more or fewer components than shown in the figure, or combining certain components, or having a different component arrangement.

[0053] It should be understood that the processor 201 may be based on a central processing unit (CPU), and the processor 201 may also be based on other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be based on a microprocessor or the processor may also be based on any conventional processor, etc.

[0054] In some embodiments, the processor 201 is used to run a computer program stored in the memory based on implementing the following steps: Acquire test environment parameter information of the power field effect transistor to be tested in a database; the test environment parameter information includes multiple environment parameter sets; Applying a gate voltage to the field effect transistor to be tested based on an initial gate voltage increasing algorithm, and obtaining a first gate voltage-drain current variation curve corresponding to the initial gate voltage increasing algorithm; Applying a gate voltage to the field effect transistor to be tested based on a reverse gate voltage decreasing algorithm corresponding to the initial gate voltage increasing algorithm, and obtaining a second gate voltage-drain current variation curve corresponding to the reverse gate voltage decreasing algorithm; Determining whether a similarity between the first gate voltage-drain current variation curve and the second gate voltage-drain current variation curve is greater than a preset similarity; If yes, the threshold voltage corresponding to the field effect transistor to be tested is determined based on the first gate voltage-drain current variation curve.

[0055] It should be noted that, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, the specific working process of the terminal device 200 described above can be based on the corresponding process of the threshold voltage measurement method of the aforementioned field effect transistor, and will not be repeated here.

[0056] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by one or more processors, the one or more processors implement the threshold voltage measurement method of the field effect transistor provided in the embodiment of the present application.

[0057] The computer-readable storage medium may be based on an internal storage unit of the terminal device 200 in the aforementioned embodiment, such as a hard disk or memory of the terminal device 200. The computer-readable storage medium may also be based on an external storage device of the terminal device 200, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped with the terminal device 200.

[0058] Based on the above, it is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for measuring the threshold voltage of a field effect transistor, characterized in that: include: Applying a gate voltage to the field effect transistor to be tested based on an initial gate voltage increasing algorithm, and obtaining a first gate voltage-drain current variation curve corresponding to the initial gate voltage increasing algorithm; Applying a gate voltage to the field effect transistor to be tested based on a reverse gate voltage decreasing algorithm corresponding to the initial gate voltage increasing algorithm, and obtaining a second gate voltage-drain current variation curve corresponding to the reverse gate voltage decreasing algorithm; Determining whether a similarity between the first gate voltage-drain current variation curve and the second gate voltage-drain current variation curve is greater than a preset similarity; If yes, the threshold voltage corresponding to the field effect transistor to be tested is determined based on the first gate voltage-drain current variation curve.

2. The method for measuring the threshold voltage of a field effect transistor according to claim 1, characterized in that: After determining whether the first gate voltage-drain current variation curve is consistent with the second gate voltage-drain current variation curve, the method further includes: If not, adjusting the initial gate voltage increasing algorithm based on the similarity to obtain a target gate voltage increasing algorithm; Applying a gate voltage to the field effect transistor to be tested based on the target gate voltage increasing algorithm, and obtaining a latest first gate voltage-drain current variation curve corresponding to the target gate voltage increasing algorithm; Applying a gate voltage to the field effect transistor to be tested based on a target reverse gate voltage decreasing algorithm corresponding to the target gate voltage increasing algorithm, and obtaining a latest second gate voltage-drain current variation curve corresponding to the target reverse gate voltage decreasing algorithm; Determining whether the similarity between the latest first gate voltage-drain current change curve and the latest second gate voltage-drain current change curve is greater than a preset similarity; The above method steps are iterated until the similarity is greater than the preset similarity, and the threshold voltage corresponding to the field effect transistor to be tested is determined based on the latest first gate voltage-drain current change curve.

3. The method for measuring the threshold voltage of a field effect transistor according to claim 1, characterized in that: The method of applying a gate voltage to the field effect transistor to be tested based on an initial gate voltage increasing algorithm comprises: Obtaining the initial current threshold of the drain current of the field effect transistor to be tested; Applying a gate voltage to the field effect transistor to be tested based on a first preset gate step voltage starting from an initial gate voltage, and in the process of applying the gate voltage to the field effect transistor to be tested based on the first preset gate step voltage, determining in real time whether a difference between the initial current threshold and the drain current is less than a preset threshold; If yes, a gate voltage is applied to the field effect transistor to be tested based on a second preset gate step voltage, and in the process of applying the gate voltage to the field effect transistor to be tested based on the second preset gate step voltage, it is determined in real time whether the drain current is greater than the initial current threshold; wherein the second preset gate step voltage is less than the first preset gate step voltage; If so, a gate voltage is applied to the field effect transistor to be tested until the maximum gate voltage is reached based on a third preset gate step voltage; wherein the third preset gate step voltage is less than the second preset gate step voltage.

4. The method for measuring the threshold voltage of a field effect transistor according to claim 3, characterized in that: The step of obtaining the initial current threshold of the drain current of the field effect transistor to be tested includes: Applying a drain voltage to the field effect transistor to be tested based on a preset drain step voltage, and in the process of applying the drain voltage to the field effect transistor to be tested, determining the drain voltage corresponding to the starting point where the drain current is not 0 as a reference drain voltage; The sum of the reference drain voltage and the preset voltage increment is determined as the target drain voltage, a drain voltage is applied to the field effect transistor to be tested based on the target drain voltage, and a drain current corresponding to the target drain voltage is determined as the initial current threshold.

5. The method for measuring the threshold voltage of a field effect transistor according to claim 1, characterized in that: The method further comprises: Obtaining the identification code of the field effect transistor to be tested; The identification code is bound to the threshold voltage to obtain a binding result, and the binding result is stored in a database.

6. The method for measuring the threshold voltage of a field effect transistor according to claim 5, characterized in that: The step of binding the identification code with the threshold voltage to obtain a binding result includes: Performing encoding operation on the threshold voltage based on a preset encoding algorithm to obtain a coding sequence; wherein the coding sequence does not include any character in the identification code; Generating an initial set based on each coded character of the coded sequence; Extracting each number in the identification code to obtain a number set, and extracting each letter in the identification code to obtain a letter set; Performing a Cartesian product operation on the initial set, the number set, and the letter set to obtain a plurality of target sets; Combining the target sets including the same coded character in each of the target sets to obtain a plurality of target set groups; The target set groups are arranged in sequence based on the sequence of the coding characters corresponding to each target set group in the coding sequence to obtain a target set group sequence; the target set group sequence is the binding result.

7. A device for measuring the threshold voltage of a field effect transistor, characterized in that: include: A first acquisition module, configured to apply a gate voltage to the field effect transistor to be tested based on an initial gate voltage increasing algorithm, and to obtain a first gate voltage-drain current variation curve corresponding to the initial gate voltage increasing algorithm; A second acquisition module is used to apply a gate voltage to the field effect transistor to be tested based on a reverse gate voltage decreasing algorithm corresponding to the initial gate voltage increasing algorithm, and obtain a second gate voltage-drain current variation curve corresponding to the reverse gate voltage decreasing algorithm; A judging module, used for judging whether the similarity between the first gate voltage-drain current variation curve and the second gate voltage-drain current variation curve is greater than a preset similarity; A determination module is used to determine the threshold voltage corresponding to the field effect transistor to be tested based on the first gate voltage-drain current change curve when the similarity between the first gate voltage-drain current change curve and the second gate voltage-drain current change curve is greater than a preset similarity.

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