A method for monitoring gate oxide degradation in SiC MOSFETs based on turn-off oscillation

Abstract

The invention discloses a method for monitoring gate oxide degradation of SiC MOSFETs based on turn-off oscillation, utilizing source stray inductance voltage. v cir Measuring the rate of change of drain-source current d when SiC MOSFET is turned off i DS / d t Based on d i DS / d t Middle threshold voltage V TH Negative temperature sensitivity and electron mobility μ To counteract the positive temperature sensitivity, it is proposed to adjust the driving resistance during turn-off. R G and negative pressure V EE Achieving negative peak value of source stray inductor voltage v cir_min Zero temperature sensitivity, and in the selected monitoring drive resistor R G_M and gate voltage V EE_M This method monitors the gate oxide degradation level of SiC MOSFETs. It is highly versatile and provides good monitoring results for gate oxide degradation in various SiC MOSFET models; it is minimally affected by temperature, making it suitable for operation in environments with large temperature fluctuations; it does not require the pins of the monitored device as a measurement interface, minimizing system intrusion; there are numerous and mature parameter measurement methods available; and it has significant potential for online applications.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and more specifically to a method for monitoring the gate oxide layer degradation of SiC MOSFETs based on source stray inductor voltage turn-off oscillation. Background Technology

[0002] SiC MOSFETs, as a typical representative of third-generation wide-bandgap power semiconductor devices, are widely used in new energy, automotive, and consumer electronics fields due to their advantages such as fast switching speed and low conduction loss. They are gradually replacing Si-based devices in high-power, high-power-density applications. However, due to immature process technology, the near-interface state density of the gate oxide layer in SiC MOSFETs is much higher than that in Si devices. Furthermore, the high temperature and high electric field stress combined with the high near-interface state density of SiC MOSFETs leads to threshold voltage instability. When the gate is subjected to stress, channel carriers are trapped by near-interface traps through tunneling, causing threshold voltage drift. Typically, the accumulation of trapped negative charges causes a positive threshold voltage drift, while the accumulation of positive charges causes a negative drift. A positive threshold voltage drift increases the on-resistance of the SiC MOSFET, slows the turn-on speed, and gradually leads to parameter mismatch in parallel operation. A negative drift increases the risk of crosstalk and mis-enabling. Therefore, it is necessary to monitor the gate oxide degradation level of SiC MOSFETs to improve system reliability, especially in high-reliability applications such as automotive and aerospace.

[0003] Existing methods for monitoring the gate oxide state of SiC MOSFETs primarily rely on changes in electrical parameters caused by direct or indirect threshold voltage drift, or on changes in parameters caused by structural variations such as gate leakage current and junction capacitance. The threshold voltage directly reflects the temperature instability of the threshold voltage bias and changes significantly when the gate oxide degrades. However, the threshold voltage itself is highly temperature-sensitive, making it difficult to accurately monitor the degree of gate oxide degradation in practical applications when temperature changes. Furthermore, both static and dynamic measurements of the threshold voltage require high-precision sensors, leading to high sampling costs. Indirect parameter changes caused by threshold voltage drift include on-resistance, body diode voltage drop, drain-source current rate of change, Miller plateau voltage, and duration. Due to the high temperature sensitivity of the threshold voltage, these parameters cannot be excluded from interference from junction temperature. While gate leakage current has extremely low temperature sensitivity, it only shows mA-level changes when the gate is about to break down, making it suitable only for early warning. Junction capacitance has extremely low temperature sensitivity, but sampling is difficult. In addition, these state detection methods require the target pin as a sampling interface, which is somewhat intrusive to the system. Summary of the Invention

[0004] To address the aforementioned shortcomings of existing technologies, the present invention aims to provide a SiC MOSFET gate oxide degradation monitoring method based on source stray inductor voltage turn-off oscillation, thereby solving the problems of existing state monitoring methods being unable to eliminate temperature interference, difficult to detect, and highly invasive.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A method for monitoring gate oxide degradation in SiC MOSFETs based on turn-off oscillations, characterized by utilizing the source stray inductance voltage v cir Measuring the rate of change of drain-source current di during SiC MOSFET turn-off DS / dt, based on di DS Threshold voltage V in / dt TH The negative temperature sensitivity and the positive temperature sensitivity of electron mobility μ cancel each other out by adjusting the driving resistance R when turned off. G and negative pressure V EE Achieving a negative peak value of source stray inductor voltage v cir_min Zero temperature sensitivity, and at the selected monitoring drive resistor R G_M and the gate voltage V EE_M The degree of gate oxide degradation of SiC MOSFETs is monitored based on the negative peak value of the source stray inductance voltage v. cir_min The degree of change can indicate the health status of the gate oxide layer.

[0007] Furthermore, the specific steps include the following: Under normal circumstances, SiC MOSFETs operate at normal R... G and V EE Next; periodically switch R G and V EE R designed for monitoring G_M and V EE_M And measure the negative peak value of the source stray inductance voltage v. cir_min And the negative peak value of the source stray inductance voltage under healthy conditions v cir_min Compare;

[0008] If v cir_min If the temperature decreases, it indicates that the detected SiC MOSFET is experiencing positive bias temperature instability; otherwise, it indicates negative bias temperature instability.

[0009] Due to the gate oxide layer degrading into a long-term aging mechanism, the negative peak value of the source stray inductance voltage v cir_min The measurement period can be set to any time between 10 hours and 100 hours, so the proposed monitoring method has minimal impact on the normal operation of SiC MOSFETs.

[0010] See Figure 7This invention studies the negative peak value of the source stray inductor voltage v. cir_min The degree of change serves as a basis for assessing the health status of the gate oxide layer of the tested SiC MOSFET. (Mechanism diagram)

[0011] Source stray inductance voltage negative peak value v cir_min The negative peak value of the induced voltage caused by the change in turn-off current in the source stray inductance is expressed by the following formula:

[0012] (1)

[0013] (2)

[0014] Among them, I L V is the load current; GS V is the external gate-source voltage; TH The threshold voltage of the device is V; μ is the channel carrier mobility; W CH L is the width of the channel. CH C is the length of the channel; OX C is the gate oxide capacitance per unit area. ciss For the gate input capacitor; R G To turn off the drive resistor; V EE To turn off the gate voltage; L s For common-source parasitic inductance; L cir As a source stray inductance, the threshold voltage V is caused by gate oxide degradation in SiC MOSFETs. TH Drift, which in turn leads to v cir_min Changes occur, therefore v cir_min It can be used as a characteristic quantity for diagnosing gate oxide degradation in SiC MOSFETs.

[0015] Source stray inductance voltage negative peak value v cir_min Threshold voltage V in TH Negatively correlated with temperature; v cir_min The channel carrier mobility μ in the gate is mainly determined by the Coulomb scattering mechanism at low gate voltages, therefore the Coulomb scattering mobility μ C The total mobility μ plays a dominant role, while the Coulomb scattering mobility μ C Positively correlated with temperature, V TH and μ C There is a counteracting effect as temperature changes occur;

[0016] Threshold voltage V TH It can be represented as:

[0017] (3)

[0018] Where, ψ B T is the Fermi potential;j This refers to the junction temperature of the SiC MOSFET; ε SiC q is the dielectric constant of 4H-SiC; k is the elementary charge; k is the Boltzmann parameter; N A The doping concentration in the p-region, and its relationship with temperature, can be expressed as:

[0019] (4)

[0020] (5)

[0021] Where, N C For intrinsically excited carrier concentration, since N C Much greater than N A Therefore, the threshold voltage V TH It exhibits negative temperature sensitivity;

[0022] μ C It can be represented as:

[0023] (6)

[0024] Where N is the model fitting parameter; α and β are model parameters, which are usually set to 1 in 4H-SiC; Q trap Q inv These represent the near-interface trapping charge and inversion layer charge concentrations, respectively; μ C The effect of temperature can be expressed as:

[0025] (7)

[0026] Therefore, the channel carrier mobility μ is positively correlated with temperature.

[0027] Source stray inductance voltage negative peak value v cir_min The relationship with temperature can be described as follows:

[0028] (8)

[0029] in

[0030] (9)

[0031] (10)

[0032] (11)

[0033] (12)

[0034] Therefore, the negative peak value of the source stray inductance voltage v cir_min The relationship with temperature is affected by the turn-off drive resistor R.G and negative pressure V EE The effect is achieved by adjusting R. G and V EE It can achieve v cir_min Its zero temperature sensitivity enables state monitoring of SiC MOSFET gate oxide degradation without temperature interference.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. This invention creatively proposes to address the issue of the negative peak value v of the stray inductor voltage in the turn-off circuit. cir_min Modeling analysis is used to propose a threshold voltage V that will increase with gate oxide layer degradation. TH It changes accordingly, and therefore can be used as a state monitoring characteristic for gate oxide degradation. Furthermore, by analyzing the negative peak value v of the source stray inductance voltage... cir_min V affected by temperature TH The temperature-sensitive modeling analysis of μ yields the negative peak value of the source stray inductance voltage v. cir_min A temperature-sensitive model was developed. Based on the model analysis, a method for changing the turn-off drive resistor R was proposed. G and negative pressure V EE Achieving a negative peak value of source stray inductor voltage v cir_min Its zero temperature sensitivity enables state monitoring of SiC MOSFET gate oxide degradation without temperature interference.

[0037] 2. This monitoring method is highly versatile and provides good monitoring results for gate oxide degradation of different types of SiC MOSFETs. It does not require the pins of the monitored device to serve as the measurement interface; only a current loop is needed, thus minimizing system intrusion. The measurement interface does not need to directly contact the pins of the monitored device, and for already designed hardware circuits, this method requires minimal modification to the original design structure. Furthermore, sampling via stray inductance of the bus can save measurement costs in systems with multiple SiC MOSFETs operating.

[0038] 3. This gate oxide degradation monitoring method is minimally affected by temperature, making it suitable for operation in environments with large temperature fluctuations. It can still accurately monitor the degree of gate oxide degradation even when the device junction temperature or ambient temperature changes. Numerous and mature parameter measurement methods exist, demonstrating significant potential for online applications.

[0039] 4. The state characteristic quantity v used in this method for monitoring the degradation state of the gate oxide layer cir_min The measurement is simple and can be performed using loop stray inductance or existing mature solutions such as Rogowski coils and mutual inductance. The peak hold circuit can greatly reduce the bandwidth requirement for sampling. Attached Figure Description

[0040] Figure 1 This invention relates to the sampling interface and the SiC MOSFET turn-off process; wherein, (a) is a schematic diagram of the sampling interface; and (b) is the gate voltage v during the turn-off process. GS Drain-source voltage v DS and current i DS Source stray inductance voltage v cir Theoretical variation diagram;

[0041] Figure 2 Example 1 shows v under a double-pulse test (600V, 20A). cir_min In V EE_M Temperature sensitivity and R G The test waveform;

[0042] Figure 3 The threshold voltage V in Embodiment 1 of the present invention TH Test waveforms in high-temperature gate bias experiment;

[0043] Figure 4 The v of Embodiment 1 of the present invention under double-pulse testing (600V, 20A) cir_min The changes in the gate oxide layer degradation experiment and the experimental waveforms with temperature; where (a) is v cir (b) varies with gate oxide layer degradation; v cir_min It varies with gate oxide layer degradation and temperature changes;

[0044] Figure 5 The following is an experimental waveform of Embodiment 2 of the present invention under a double-pulse test (600V, 20A); wherein, (a) is R G_M Select the test waveform; (b) is the V waveform of Example 2. TH Test waveforms in the high-temperature grid bias experiment; (c) is v cir Experimental waveforms with gate oxide layer degradation; (d) is v cir_min Experimental waveforms as gate oxide layer degradation and temperature change;

[0045] Figure 6 The following is an experimental waveform of Embodiment 3 of the present invention under a double-pulse test (600V, 20A); wherein, (a) is R G_M Select the test waveform; (b) is the V waveform of Example 3. TH Test waveforms in the high-temperature grid bias experiment; (c) is v cir Experimental waveforms with gate oxide layer degradation; (d) is v cir_min Experimental waveforms as gate oxide layer degradation and temperature change;

[0046] Figure 7 This is a basic logic diagram of the gate oxide layer degradation monitoring method of the present invention. Detailed Implementation

[0047] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0048] This invention provides a method for monitoring gate oxide degradation in SiC MOSFETs based on source stray inductor voltage turn-off oscillation, using the negative peak value v of the source stray inductor voltage. cir_min The degree of change is used as the basis for assessing the health status of the gate oxide layer of the SiC MOSFET, utilizing the source stray inductance voltage v. cir Measuring the rate of change of drain-source current di during SiC MOSFET turn-off DS / dt, based on di DS Threshold voltage V in / dt TH The negative temperature sensitivity and the positive temperature sensitivity of electron mobility μ cancel each other out by adjusting the driving resistance R when turned off. G and negative pressure V EE Achieving a negative peak value of source stray inductor voltage v cir_min Zero temperature sensitivity, and at the selected monitoring drive resistor R G_M and the gate voltage V EE_M The degree of gate oxide degradation of SiC MOSFETs was monitored.

[0049] Select periodic switching of drive resistor voltage to R G_M and V EE_M And measure the negative peak value of the source stray inductance voltage v. cir_min If v cir_min A change indicates that gate oxide degradation has occurred, based on v. cir_min The degree of change can indicate the health status of the gate oxide layer.

[0050] Specifically, the steps include the following: Under normal circumstances, SiC MOSFETs operate at normal R... G and V EE Next; periodically switch R G and V EE R designed for monitoring G_M and V EE_M And measure the negative peak value of the source stray inductance voltage v. cir_min And in a healthy state v cir_min Comparison, if v cir_min If the temperature decreases, it indicates that the tested SiC MSOFET is experiencing positive bias temperature instability; conversely, if it increases, it indicates negative bias temperature instability.

[0051] Because the gate oxide layer degrades into a long-term aging mechanism, v cir_min The measurement period can be set to a relatively long time, so the proposed monitoring method has minimal impact on the normal operation of SiC MOSFETs.

[0052] See Figure 1(a) is a schematic diagram of the SiC MOSFET circuit model and sampling interface. Its measurement interface does not need to directly contact the pins of the monitored device. It only needs to take a current loop as the monitoring interface, so it has minimal intrusion into the system.

[0053] Figure 1 (b) is a theoretical voltage and current change graph during the turn-off process, and the measured parameter v cir_min This is generated by the change in drain-source current during the turn-off process. The state characteristic quantity v is measured using the loop stray inductance. cir_min Indirect measurement di DS The minimum value of / dt is used to monitor the degradation state of the gate oxide layer. Therefore, this method is simple to measure and has low invasiveness.

[0054] This invention measures the minimum value of stray inductance voltage v in the turn-off circuit. cir_min Implement a temperature-independent method for monitoring gate oxide degradation in SiC MOSFETs, v cir_min It can be represented as

[0055] (1)

[0056] The gate oxide layer causes a threshold voltage V TH Drift thus causing v cir_min Change, therefore v cir_min It can be used as a state characteristic quantity for monitoring the degradation of the gate oxide layer of SiC MOSFETs. cir_min The threshold voltage V is the main factor affected by temperature. TH The temperature sensitivity of both electron mobility μ and electron mobility μ can be expressed as:

[0057] (4)

[0058] (7)

[0059] Therefore, v cir_min Thermosensitivity can be expressed as

[0060] (8)

[0061] According to the analysis, v cir_min Thermosensitive and V EE and R G Related, rewrite v cir_min Thermosensitive

[0062] (8)

[0063] Therefore, by changing V EE and R G Implement v cir_minZero temperature sensitivity, thus enabling gate oxide layer condition monitoring that eliminates the influence of temperature.

[0064] The method of this invention was validated in a double-pulse test, which is considered capable of accurately reproducing the transient waveform of a SiC MOSFET under a given load current and bus voltage. A current loop segment at the negative terminal of the test circuit was used as the test interface, and the stray inductance of this loop segment was L. cir .

[0065] Example 1

[0066] The parameters of the SiC MOSFET with model number C3M0040120D under dual-pulse testing and the device under test are shown in Table 1:

[0067] Table 1 Experimental parameters

[0068]

[0069] Monitoring selected V EE It should be as large as possible to meet the needs of more SiC MOSFETs, and a larger V EE_M It can make the corresponding R G_M Smaller, so that |v cir_min A larger V reduces the difficulty of measurement. However, an excessively large V... EE_M This could lead to gate failure and increase the risk of breakdown due to turn-off drain-source overvoltage. Therefore, the minimum turn-off negative voltage recommended in the product datasheet provided by the manufacturer of the device under test should be selected as V. EE_M For optimal performance, the C3M0040120D datasheet recommends a minimum negative voltage of -8V; therefore, V is set to [value missing]. EE_M = 8V. At V EE_M Lower V cir_min Thermosensitive and driving resistance R G Relationship such as Figure 2 As shown.

[0070] according to Figure 2 It can be seen that when R G = 24Ω v cir_min It exhibits zero temperature sensitivity. Therefore, R is set... G_M = 24Ω.

[0071] To verify the effectiveness of this method during gate oxide degradation, a high-temperature gate bias experiment was performed on the device under test (DUT) to achieve gate oxide degradation. The high-temperature gate bias involved applying a 32V DC stress and a 150°C temperature stress to the gate of the DUT, while simultaneously shorting the source and drain of the DUT. Figure 3 This demonstrates the threshold voltage V of two experimental devices from the same batch under high-temperature gate bias. TH The test results. The V values ​​of devices 1 and 2 under 42 hours of stress. THThe increases of 48.88% and 54.38% respectively prove that the gate oxide layer of the device under test has degraded.

[0072] Figure 4 Shown in V EE_M = 8V, R G_M = 24Ω, the voltage of the two devices under test cir_min The changes in cumulative time of high-temperature gate bias experiments and v under different degradation levels cir_min Experimental waveforms with temperature (25℃-150℃). vo values ​​of devices 1 and 2 under 42 hours of stress. cir_min The temperature decreased by 6.55% and 7.09% respectively, affecting the v of the two devices. cir_min The maximum change was 0.103%. According to... Figure 4 It can be seen that in V EE_M = 8V, R G_M = 24Ω, v caused by gate oxide degradation cir_min The changes are much greater than those caused by temperature, therefore it can be considered that the invented state monitoring method has eliminated the influence of temperature.

[0073] Example 2

[0074] The SiC MOSFET, model C3M0032120D, has a minimum gate voltage specified in its datasheet as -8V, therefore V is still set. EE_M = 8V. Figure 5 (a) shows V EE_M = 8V, C3M0032120D's V cir_min Thermosensitivity with R G The test results show that when R G When the Ω is 20Ω, v cir_min Exhibiting zero temperature sensitivity, therefore R is set G_M = 20Ω. Figure 5 (b) Demonstrates the threshold voltage V of the C3M0032120D in a high-temperature gate bias experimental device. TH The test results Figure 5 (c) shows the v in the high-temperature gate bias experiment. cir Experimental waveforms as gate oxide layer degradation time. Figure 5 (d) shows the v in the high-temperature gate bias experiment. cir_min Experimental waveforms with gate oxide layer degradation time and temperature.

[0075] Example 3

[0076] The SiC MOSFET, model C3M0021120D, has a minimum gate voltage specified in its datasheet as -8V, therefore V is still set. EE_M = 8V. Figure 6 (a) shows VEE_M = 8V, C3M0021120D's V cir_min Thermosensitivity with R G The test results show that when R G When the Ω is 8.2Ω, v cir_min Exhibiting zero temperature sensitivity, therefore R is set G_M = 8.2Ω. Figure 6 (b) Demonstrates the threshold voltage V of the C3M0021120D in a high-temperature gate bias experimental device. TH The test results Figure 6 (c) shows the v in the high-temperature gate bias experiment. cir Experimental waveforms as gate oxide layer degradation time. Figure 6 (d) shows the v in the high-temperature gate bias experiment. cir_min Experimental waveforms with gate oxide layer degradation time and temperature.

[0077] The quantitative data of the test results of Example 2 and Example 3 are shown in Table 2.

[0078] Table 2. Experimental results of Examples 2 and 3

[0079]

[0080] As shown in Table 2, the gate oxide degradation state monitoring method of this invention can accurately monitor the degree of degradation for various types of SiC MOSFETs when gate oxide degradation occurs, and the interference caused by temperature is far less than the change caused by gate voltage layer degradation. Due to differences in device structure, the monitoring conditions for different devices may vary and need to be tuned in advance.

[0081] As can be seen from the results of Examples 1, 2 and 3, the gate oxide degradation monitoring method of SiC MOSFET based on turn-off oscillation of the present invention can effectively realize gate oxide degradation state monitoring in various types of SiC MOSFETs without the influence of temperature. Moreover, the measurement is simple and has little intrusion into the system, which makes up for the shortcomings of current SiC MOSFET state monitoring methods that cannot accurately monitor the degree of gate oxide degradation under conditions of large temperature changes or large load fluctuations.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those skilled in the art should understand that any modifications or equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A method for monitoring gate oxide degradation of SiC MOSFETs based on turn-off oscillation, characterized in that, Utilizing source stray inductance voltage v cir Measuring the rate of change of drain-source current di during SiC MOSFET turn-off DS / dt, based on di DS Threshold voltage V in / dt TH The negative temperature sensitivity and the positive temperature sensitivity of electron mobility μ cancel each other out by adjusting the driving resistance R when turned off. G and negative pressure V EE Achieving a negative peak value of source stray inductor voltage v cir_min Zero temperature sensitivity, and at the selected monitoring drive resistor R G_M and the gate voltage V EE_M The degree of gate oxide degradation of SiC MOSFETs is monitored based on the negative peak value of the source stray inductance voltage v. cir_min The degree of change can indicate the health status of the gate oxide layer; The specific steps include: SiC MOSFET operating at normal R G and V EE Next; periodically switch R G and V EE R designed for monitoring G_M and V EE_M And measure the negative peak value of the source stray inductance voltage v. cir_min And the negative peak value of the source stray inductance voltage in a healthy state v cir_min Compare; If v cir_min If the temperature decreases, it indicates that the detected SiC MOSFET is experiencing positive bias temperature instability; otherwise, it indicates negative bias temperature instability. Due to the gate oxide layer degrading into a long-term aging mechanism, the negative peak value of the source stray inductance voltage v cir_min The measurement period can be set to any time between 10 hours and 100 hours, so the proposed monitoring method has minimal impact on the normal operation of SiC MOSFETs.

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