Method of expanding a metal gate layer polish window

Abstract

The application provides a method for expanding a metal gate layer polishing window, and provides a substrate, a long channel device region and a short channel device region on the substrate, a pseudo gate structure with different lengths is formed on the long channel device region and the short channel device region, and an etching stop layer covering the pseudo gate structure is formed; a first interlayer dielectric layer with a preset thickness is formed on the etching stop layer, and then a second interlayer dielectric layer covering the pseudo gate structure is formed on the first interlayer dielectric layer, so that only the first interlayer dielectric layer is filled in a narrow gap between part of the pseudo gate structures, and the first and second interlayer dielectric layers are filled in a wide gap between part of the pseudo gate structures, and the polishing rate of the second interlayer dielectric layer is slower than that of the first interlayer dielectric layer; the first and second interlayer dielectric layers are polished to the pseudo gate polysilicon layer; the pseudo gate polysilicon layer is removed to form a groove, a metal gate layer filling the groove is formed, and the metal gate layer is polished to a required height. The application reduces the degree of disc-shaped defects after the second interlayer dielectric layer is polished, and avoids the problem of a too small process window.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for expanding the polishing window of a metal gate layer. BACKGROUND

[0002] After the source and drain regions are formed, there are silicon nitride and silicon oxide mask templates of different thicknesses remaining on the polysilicon gates in different regions. Currently, a photoresist etch back (PREB) process is used to remove the mask templates on the gates, but it is limited by process bottlenecks. Even after optimization, there is still a height difference of about 100 angstroms in the silicon nitride sidewalls of N / P MOS.

[0003] The prior art method for forming a metal gate includes:

[0004] Step one, providing a substrate 101, forming pseudo-gate structures of different lengths on the long and short channel device regions on the substrate 101, the pseudo-gate structure including a pseudo-gate polysilicon layer 103 and a sidewall structure 104 on the pseudo-gate polysilicon layer 103, and forming an etch stop layer 105 covering the pseudo-gate structure;

[0005] Step two, forming an interlayer dielectric layer 106 covering the pseudo-gate structure, forming a structure as shown in Figure 1

[0006] Step three, polishing the interlayer dielectric layer 106 to the pseudo-gate polysilicon layer 103, forming a structure as shown in Figure 2 In order to cover the height difference of the photoresist etch back and ensure that the pseudo-gate polysilicon layer 103 is completely opened, over polishing is required, which results in serious dishing in the large dielectric layer region.

[0007] Step four, removing the pseudo-gate polysilicon layer 103 to form a recess, forming a metal gate layer 107 filling the recess, forming a structure as shown in Figure 3 Step five, polishing the metal gate layer 107 to the desired height, forming a structure as shown in Figure 4 In order to ensure that the metal on the interlayer dielectric layer 106 is polished cleanly, over polishing is also required, which results in metal scratch defects at a poor level. In addition, because a high selectivity polishing liquid (such as AL:OX≈100:1) is used to polish the metal gate layer 107, the polishing rate of the long channel region is faster than that of the narrow channel region, and finally the long channel region is polished to a lower position (about 70 angstroms lower), which cannot meet the process requirements.

[0008] To solve the above problems, a new method for expanding the polishing window of a metal gate layer is needed. SUMMARY

[0009] ​In view of the above-mentioned disadvantages of the prior art, the present application aims to provide a method for expanding the polishing window of a metal gate layer, so as to solve the problem that the polishing of the interlayer dielectric layer in the prior art forms a large recess, which affects the process window of the subsequent process.

[0010] To achieve the above-mentioned objects and other related objects, the present application provides a method for expanding the polishing window of a metal gate layer, comprising:

[0011] Step one, providing a substrate, forming a pseudo-gate structure with different lengths on the long and short channel device regions on the substrate, the pseudo-gate structure comprising a pseudo-gate polysilicon layer and a sidewall structure on the pseudo-gate polysilicon layer, and forming an etching stop layer covering the pseudo-gate structure;

[0012] Step two, forming a first interlayer dielectric layer with a preset thickness on the etching stop layer, and then forming a second interlayer dielectric layer covering the pseudo-gate structure on the first interlayer dielectric layer, so that only the first interlayer dielectric layer is filled in the narrow gap between part of the pseudo-gate structures, and the first and second interlayer dielectric layers are filled in the wide gap between part of the pseudo-gate structures, and the polishing rate of the second interlayer dielectric layer relative to the first interlayer dielectric layer is slower;

[0013] Step three, polishing the first and second interlayer dielectric layers to the pseudo-gate polysilicon layer;

[0014] Step four, removing the pseudo-gate polysilicon layer to form a recess, forming a metal gate layer filling the recess, and polishing the metal gate layer to a desired height.

[0015] Preferably, a pad oxide layer is also formed on the substrate in step one, and the pseudo-gate structure is formed on the pad oxide layer.

[0016] Preferably, the material of the etching stop layer in step one is silicon nitride.

[0017] Preferably, the first interlayer dielectric layer in step two is an oxide layer formed by sub-atmospheric pressure chemical vapor deposition.

[0018] Preferably, the second interlayer dielectric layer in step two is an oxide layer formed by plasma-enhanced chemical vapor deposition.

[0019] Preferably, the polishing method in step three is chemical mechanical planarization polishing.

[0020] Preferably, the pseudo-gate polysilicon layer is removed by a wet etching method in step four.

[0021] Preferably, before forming the metal gate layer in step four, the method further comprises the step of forming an interface layer, a high-K dielectric layer, a bottom isolation layer, a work function metal layer and a top isolation layer in the recess.

[0022] Preferably, the material of the metal gate layer in step four is Al.

[0023] Preferably, the polishing method in step four is chemical mechanical planarization polishing.

[0024] As described above, the method for expanding the polishing window of the metal gate layer of the present application has the following beneficial effects:

[0025] The present application reduces the degree of dishing defects after polishing the second interlayer dielectric layer, so that there is less metal gate layer residue at this location, thereby increasing the process window of the metal gate layer residue, reducing the over-polishing time, and improving the polishing scratch defects of the final metal gate layer. In addition, the polishing rate difference between the long-channel device area and the first interlayer dielectric layer is reduced, and the gate height difference between the long-channel device area and the short-channel device area is also improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A schematic diagram showing the formation of an interlayer dielectric layer in the prior art;

[0027] Figure 2 A schematic diagram showing the polishing to expose the pseudo gate polysilicon layer in the prior art;

[0028] Figure 3 A schematic diagram showing the formation of a metal gate layer in the prior art;

[0029] Figure 4 A schematic diagram showing the polishing of a metal gate layer in the prior art;

[0030] Figure 5 A schematic diagram showing the process flow of the present application;

[0031] Figure 6 A schematic diagram showing the formation of the first and second interlayer dielectric layers in the present application;

[0032] Figure 7 A schematic diagram showing the polishing to expose the pseudo gate polysilicon layer in the present application;

[0033] Figure 8 A schematic diagram showing the formation of a metal gate layer in the present application;

[0034] Figure 9 A schematic diagram showing the polishing of a metal gate layer in the present application. DETAILED DESCRIPTION

[0035] Following, the embodiments of the present application will be described in detail by specific examples. Other advantages and effects of the present application can be easily understood by those skilled in the art from this disclosure. The present application can also be implemented or applied by other different embodiments, and the details in this specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0036] Please refer to Figure 5 The present application provides a method for expanding the polishing window of a metal gate, comprising:

[0037] Step one, providing a substrate 201, forming pseudo-gate structures with different lengths on the long and short channel device regions on the substrate 201, the pseudo-gate structure comprising a pseudo-gate polysilicon layer 203 and a sidewall structure 204 on the pseudo-gate polysilicon layer 203, and forming an etching stop layer 205 covering the pseudo-gate structure;

[0038] In some embodiments, a pad oxide layer 202 is also formed on the substrate 201 in step one, and the pseudo-gate structure is formed on the pad oxide layer 202.

[0039] In some embodiments, the material of the etching stop layer 205 in step one is silicon nitride.

[0040] Step two, forming a first interlayer dielectric layer 206 with a preset thickness on the etching stop layer 205, and then forming a second interlayer dielectric layer 207 covering the pseudo-gate structure on the first interlayer dielectric layer 206, so that only the first interlayer dielectric layer 206 is filled in the narrow gap between part of the pseudo-gate structures, and the first and second interlayer dielectric layers are filled in the wide gap between part of the pseudo-gate structures, and the polishing rate of the second interlayer dielectric layer 207 relative to the first interlayer dielectric layer 206 is slower;

[0041] In some embodiments, the first interlayer dielectric layer 206 in step two is an oxide layer formed by sub-atmospheric pressure chemical vapor deposition.

[0042] In some embodiments, the second interlayer dielectric layer 207 in step two is an oxide layer formed by plasma-enhanced chemical vapor deposition, which is harder than the oxide layer formed by sub-atmospheric pressure chemical vapor deposition.

[0043] Step three, polishing the first and second interlayer dielectric layers to the pseudo-gate polysilicon layer 203, which needs to be polished until the pseudo-gate polysilicon layer 203 is completely exposed. Since the polishing rate of the second interlayer dielectric layer 207 relative to the first interlayer dielectric layer 206 is slower, the degree of disc-shaped defects after polishing of the second interlayer dielectric layer 207 in the wide gap can be reduced;

[0044] In some embodiments, the polishing method in step three is chemical mechanical planarization polishing.

[0045] Step four, remove the dummy gate polysilicon layer 203 to form a recess, form a metal gate layer 208 to fill the recess, and polish the metal gate layer 208 to a desired height. Since the degree of the dish-shaped defect is reduced in step three, less metal remains at this location, thereby increasing the process window for metal residue, reducing the over-polishing time, and improving the final metal polishing scratch defect. In addition, the polishing rate difference between the long channel device region and the short channel device region is reduced by polishing the second interlayer dielectric layer 207 in the long channel device region and the first interlayer dielectric layer 206 in the long channel device region, and the gate height difference between the long channel device region and the short channel device region is also improved.

[0046] In some embodiments, the dummy gate polysilicon layer 203 is removed in step four using a wet etching method.

[0047] In some embodiments, before forming the metal gate layer 208 in step four, the step of forming an interface layer, a high-k dielectric layer, a bottom isolation layer, a work function metal layer, and a top isolation layer in the recess is further included. This is a commonly used MOS structure in the prior art, and will not be described here.

[0048] The interface layer can include a dielectric material, such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SION). The interface layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.

[0049] The work function metal layer can include a work function metal to provide a suitable work function for the high-k / metal gate structure.

[0050] The bottom isolation layer and the top isolation layer can be titanium nitride or other suitable materials.

[0051] In some embodiments, the material of the metal gate layer 208 in step four is Al. In other embodiments, the material of the metal gate layer 208 can also be tungsten, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0052] In some embodiments, the polishing method in step four is chemical mechanical planarization polishing.

[0053] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The actual implementation of each component can be arbitrarily changed in terms of type, number, and proportion, and the component layout type can also be more complex.

[0054] In summary, the present application reduces the degree of dishing defects after polishing the second interlayer dielectric layer, so that the remaining metal gate layer is less, thereby increasing the process window of the remaining metal gate layer, reducing the over-polishing time, and improving the final metal gate layer polishing scratch defects. In addition, the long channel device area grinds the second interlayer dielectric layer, the long channel device area grinds the first interlayer dielectric layer, and the grinding rate difference between the long and short channel device areas is reduced, so that the gate height difference between the long and short channel device areas can also be improved. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0055] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of enlarging a metal gate layer polish window, characterized by, At least comprising: Step one, providing a substrate, forming pseudo-gate structures with different lengths on long and short channel device regions on the substrate, the pseudo-gate structure comprising a pseudo-gate polysilicon layer and a side wall structure on the pseudo-gate polysilicon layer, forming an etching stop layer covering the pseudo-gate structure; Step two, forming a first interlayer dielectric layer with a preset thickness on the etching stop layer, the first interlayer dielectric layer being an oxidation layer formed by sub-atmospheric pressure chemical vapor deposition, then forming a second interlayer dielectric layer covering the pseudo-gate structure on the first interlayer dielectric layer, the second interlayer dielectric layer being an oxidation layer formed by plasma enhanced chemical vapor deposition, so that only the first interlayer dielectric layer is filled in the narrow gap between part of the pseudo-gate structures, and the first and second interlayer dielectric layers are filled in the wide gap between part of the pseudo-gate structures, the second interlayer dielectric layer having a slower polishing rate relative to the first interlayer dielectric layer; Step three, polishing the first and second interlayer dielectric layers to the pseudo-gate polysilicon layer; Step four, removing the pseudo-gate polysilicon layer to form a groove, forming a metal gate layer filling the groove, and polishing the metal gate layer to a desired height.

2. The method of claim 1, wherein: The substrate in step one also has a pad oxide layer, and the pseudo-gate structure is formed on the pad oxide layer.

3. The method of claim 1, wherein: The material of the etching stop layer in step one is silicon nitride.

4. The method of claim 1, wherein: The polishing method in step three is chemical mechanical polishing.

5. The method of claim 1, wherein: The pseudo-gate polysilicon layer is removed by wet etching in step four.

6. The method of enlarging a metal gate layer polish window of claim 1, wherein: Before forming the metal gate layer in step four, it further includes the steps of forming an interface layer, a high-K dielectric layer, a bottom isolation layer, a work function metal layer, and a top isolation layer in the groove.

7. The method of enlarging a metal gate layer polish window of claim 1, wherein: The material of the metal gate layer in step four is Al.

8. The method of enlarging a metal gate layer polish window of claim 1, wherein: The polishing method in step four is chemical mechanical polishing.

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