Method and system for realizing integrated packaging of storage chip

Abstract

The invention relates to the technical field of chip packaging, and discloses an integrated packaging method and system for a storage chip, and the method comprises the steps: calculating the quality credibility corresponding to the storage chip; detecting surface damage scratches of the storage chips, calculating splitting strength threshold values corresponding to the storage chips based on the surface damage scratches, and screening out high-quality storage chips from the storage chips; planning a packaging sequence corresponding to the storage chip; calculating the pin coordination degree between the chips in the packaging sequence, performing mechanical behavior simulation processing on the storage chips, recording temperature simulation data and chip deformation data in the mechanical simulation processing process when the storage chips meet preset simulation conditions in the mechanical behavior simulation processing, and calculating thermal expansion coefficients corresponding to the storage chips; and performing sequence adjustment on the packaging sequence to obtain an optimal packaging sequence, and performing packaging processing on the storage chip to obtain a packaged chip. The invention mainly aims to solve the problem that the integrated packaging stability of the storage chip is reduced.

Description

Technical Field

[0001] The invention relates to a method and system for realizing integrated packaging of a storage chip, belonging to the technical field of chip packaging. Background Art

[0002] In today's era of rapid technological development, memory chips, as core components of various electronic devices, have seen explosive growth in market demand. As electronic products continue to move toward miniaturization, high performance, and high reliability, the integrated packaging technology of memory chips has become increasingly critical.

[0003] Existing memory chip integrated packaging methods mainly rely on traditional packaging processes and control systems. First, the basic functions and technical requirements of packaging are determined according to the type of memory chip, performance indicators, and application scenarios, and then suitable packaging equipment and materials are selected. Then, through the pre-set packaging process flow, automated equipment is used to perform chip mounting, wire bonding, injection molding and other operations. In this process, the control of the equipment is mostly based on fixed program logic. These programs are usually written based on past packaging experience and limited test data. During the packaging process, the control system collects sensor data such as temperature, pressure, and position according to the established program, and controls the action of the equipment according to preset thresholds and logical relationships. However, this traditional method relies heavily on fixed programs written based on historical experience data, and does not consider the impact of chip packaging in combination with multiple factors, resulting in reduced stability of the integrated packaging of memory chips. Summary of the invention

[0004] The present invention provides a method and system for realizing integrated packaging of memory chips, the main purpose of which is to solve the problem of reduced stability of integrated packaging of memory chips.

[0005] To achieve the above object, the present invention provides a method for implementing an integrated packaging of a memory chip, comprising:

[0006] Acquire a memory chip to be processed, collect chip test data corresponding to the memory chip, identify test indicators corresponding to the chip test data, and calculate the quality credibility corresponding to the memory chip by combining the test indicators and the chip test data;

[0007] Detecting surface damage scratches on the memory chip, calculating a cracking strength threshold corresponding to the memory chip based on the surface damage scratches, and selecting high-quality memory chips from the memory chips by combining the quality credibility and the cracking strength threshold;

[0008] Querying the design layout and signal transmission protocol corresponding to the memory chip, determining the chip pin layout corresponding to the memory chip based on the design layout, and planning the packaging sequence corresponding to the memory chip according to the signal transmission protocol;

[0009] According to the chip pin layout, the pin coordination degree between each chip in the packaging sequence is calculated, and the mechanical behavior simulation processing is performed on the memory chip. When the memory chip reaches a preset simulation condition in the mechanical behavior simulation processing, the temperature simulation data and the chip deformation data in the mechanical simulation processing are recorded, and the thermal expansion coefficient corresponding to the memory chip is calculated based on the temperature simulation data and the chip deformation data;

[0010] The packaging sequence is adjusted in combination with the thermal expansion coefficient and the pin coordination degree to obtain an optimal packaging sequence. Based on the optimal packaging sequence, the packaging process of the memory chip is performed to obtain a packaged chip.

[0011] Optionally, the combining the test index and the chip test data to calculate the quality credibility corresponding to the storage chip includes:

[0012] Calculating a data standard deviation and a data mean of the chip test data, and calculating a data coefficient of variation corresponding to the chip test data based on the data standard deviation and the data mean;

[0013] According to the data variation coefficient, performing data error correction processing on the chip test data to obtain target test data;

[0014] The quality credibility corresponding to the storage chip is calculated by combining the target test data and the test index.

[0015] Optionally, the combining the target test data and the test index to calculate the quality credibility corresponding to the storage chip includes:

[0016] Performing standardization processing on the target test data to obtain standard test data;

[0017] Calculate the grey correlation between each indicator in the test indicators;

[0018] Based on the grey correlation degree, weights are assigned to the test indicators to obtain indicator weights;

[0019] The quality credibility corresponding to the storage chip is calculated by combining the indicator weight and the standard test data.

[0020] Optionally, detecting surface damage and scratches on the memory chip includes:

[0021] Collecting a chip surface image corresponding to the storage chip, and performing a main body segmentation process on the chip surface image to obtain a chip main body surface image;

[0022] Performing grayscale processing on the chip main body appearance image to obtain a grayscale appearance image;

[0023] Calculating the pixel gradient intensity corresponding to each pixel in the grayscale apparent image, and extracting the apparent mutation area in the grayscale apparent image based on the pixel gradient intensity;

[0024] Extracting regional appearance features corresponding to the epigenetic mutation region based on the main epigenetic image of the chip;

[0025] Based on the regional surface features, surface damage and scratches of the memory chip are detected.

[0026] Optionally, the calculating the cracking intensity threshold corresponding to the memory chip based on the surface damage scratches includes:

[0027] Based on the surface damage scratches, determining a chip flaw detection position corresponding to the memory chip;

[0028] Using a preset flaw detection device to measure the flaw detection parameter information corresponding to the flaw detection position of the chip;

[0029] Based on the flaw detection parameter information, determining the damage depth and damage length corresponding to the surface damage scratch;

[0030] In combination with the damage depth and the damage length, the cracking intensity threshold corresponding to the memory chip can be calculated by the following formula:

[0031]

[0032] Among them, A represents the cracking strength threshold corresponding to the memory chip, α represents the stress intensity factor, β represents the crack geometry factor, B represents the damage depth, and D represents the damage length.

[0033] Optionally, planning a packaging sequence corresponding to the memory chip according to the signal transmission protocol includes:

[0034] Identifying a transmission protocol text in the signal transmission protocol, and analyzing a signal transmission function corresponding to the signal transmission protocol based on the transmission protocol text;

[0035] Mining the function description information corresponding to the signal transmission function, and extracting the function descriptor in the function description information;

[0036] Determining a transmission protocol element of the signal transmission function based on the functional descriptor;

[0037] Extracting protocol input elements and protocol output elements from the transmission protocol elements;

[0038] According to the protocol input elements and the protocol output elements, a packaging sequence corresponding to the storage chip is planned.

[0039] Optionally, extracting the function descriptor in the function description information includes:

[0040] Calculating information entropy corresponding to the function description information, and extracting key function description information from the function description information according to the information entropy;

[0041] Performing word segmentation processing on the key function description information to obtain description information word segmentation;

[0042] Calculate the quantitative feature value corresponding to the description information segmentation, and calculate the expected feature value corresponding to the description information segmentation;

[0043] Combining the quantitative feature value and the expected feature value, the segmentation association strength between the description information segmentations can be calculated by the following formula:

[0044]

[0045] Among them, R represents the strength of the word association between the description information words, Q a Indicates the quantitative feature value corresponding to the a-th word in the description information word. represents the expected feature value corresponding to the ath word in the description information segmentation, Q a+1 Indicates the quantitative feature value corresponding to the a+1th word in the description information word. represents the expected feature value corresponding to the a+1th word in the description information word, and a and a+1 both represent the sequence number of the description information word;

[0046] According to the segmentation association strength, the description information segmentation is filtered to obtain the target information segmentation;

[0047] Based on the target information segmentation, a function descriptor in the function description information is generated.

[0048] Optionally, the calculating the pin coordination degree between each chip in the packaging sequence according to the chip pin layout includes:

[0049] According to the chip pin layout, establishing a chip layout coordinate system corresponding to the packaging sequence;

[0050] Based on the chip layout coordinate system, determining the chip pin coordinates corresponding to each chip in the packaging sequence;

[0051] Based on the chip pin coordinates, calculating the pin distance between each chip in the packaging sequence;

[0052] In combination with the pin distance and the preset distance threshold, the pin coordination degree between each chip in the packaging sequence can be calculated by the following formula:

[0053]

[0054] Among them, H represents the pin coordination between each chip in the packaging sequence, e represents the natural constant, ω represents the sensitivity coefficient, and E b，d Indicates the pin distance between the bth chip and the dth chip in the packaging sequence, E , represents the preset distance threshold, and b and d represent the chip serial numbers in the packaging sequence.

[0055] Optionally, the calculating the thermal expansion coefficient corresponding to the memory chip based on the temperature simulation data and the chip deformation data includes:

[0056] Respectively extracting the simulation temperature value and the chip deformation amount in the temperature simulation data and the chip deformation data, and recording the initial deformation length corresponding to the chip deformation amount;

[0057] Aligning the simulation temperature value and the chip deformation amount to obtain an aligned temperature value and an aligned deformation amount;

[0058] In combination with the alignment temperature value, the alignment deformation amount and the initial length of the deformation, the thermal expansion coefficient corresponding to the memory chip can be calculated as follows:

[0059]

[0060] Among them, F represents the thermal expansion coefficient corresponding to the memory chip, △M n and △M n-1 They represent the chip deformation corresponding to the simulation temperature values ​​at time n and time n-1, respectively. n and n-1 both represent the time series number of the simulation temperature value. n and T n-1 Respectively represent the simulation temperature values ​​corresponding to time n and time n-1, M n-1 Indicates the initial deformation length when the simulation temperature value is n-1.

[0061] An integrated packaging system for implementing a memory chip, characterized in that the system comprises:

[0062] A quality credibility calculation module is used to obtain a memory chip to be processed, collect chip test data corresponding to the memory chip, identify a test index corresponding to the chip test data, and calculate the quality credibility corresponding to the memory chip by combining the test index and the chip test data;

[0063] A chip screening module, used to detect surface damage scratches of the memory chip, calculate a cracking strength threshold corresponding to the memory chip based on the surface damage scratches, and screen out high-quality memory chips from the memory chips by combining the quality credibility and the cracking strength threshold;

[0064] A sequence planning module, used to query the design layout and signal transmission protocol corresponding to the memory chip, determine the chip pin layout corresponding to the memory chip based on the design layout, and plan the packaging sequence corresponding to the memory chip according to the signal transmission protocol;

[0065] a thermal expansion coefficient calculation module, for calculating the pin coordination between each chip in the packaging sequence according to the chip pin layout, performing mechanical behavior simulation processing on the storage chip, recording temperature simulation data and chip deformation data during the mechanical simulation processing when the storage chip reaches a preset simulation condition, and calculating the thermal expansion coefficient corresponding to the storage chip based on the temperature simulation data and the chip deformation data;

[0066] The chip packaging module is used to adjust the packaging sequence in combination with the thermal expansion coefficient and the pin coordination degree to obtain an optimal packaging sequence, and based on the optimal packaging sequence, perform packaging processing on the memory chip to obtain a packaged chip.

[0067] Compared with the problems described in the background technology, the present invention calculates the quality credibility corresponding to the storage chip by combining the test index and the chip test data, and can understand the chip quality corresponding to the storage chip through the quality credibility, thereby providing a reliable basis for subsequently screening out high-quality storage chips from the storage chips. The present invention can timely discover the damage defects on the surface of the storage chip by detecting the surface damage scratches of the storage chip, thereby understanding the corresponding loss degree of the storage chip, laying a foundation for the subsequent calculation of the cracking strength threshold corresponding to the storage chip. The present invention determines the chip pin layout corresponding to the storage chip based on the design layout, and can obtain the position of each pin of the storage chip in the chip. The specific position distribution on the packaging sequence is convenient for calculating the pin coordination between each chip in the subsequent packaging sequence. According to the signal transmission protocol, the packaging sequence corresponding to the memory chip is planned, and the order of packaging processing corresponding to the memory chip can be obtained. The present invention calculates the pin coordination between each chip in the packaging sequence according to the chip pin layout. The degree of coordination between each chip in the packaging sequence can be understood through the pin coordination, thereby improving the accuracy of sequence adjustment of the packaging sequence. The present invention adjusts the packaging sequence by combining the thermal expansion coefficient and the pin coordination, and can obtain the optimal packaging sequence to improve the packaging stability of the subsequent memory chip. Therefore, the present invention proposes a method and system for realizing integrated packaging of memory chips, thereby improving the integrated packaging stability of memory chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 A schematic diagram of a flow chart of a method for implementing an integrated packaging of a memory chip provided by an embodiment of the present invention;

[0069] Figure 2 A functional module diagram of an integrated packaging system for implementing a memory chip provided in one embodiment of the present invention.

[0070] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0071] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0072] The embodiment of the present application provides a method for implementing an integrated packaging of a memory chip. The execution subject of the method for implementing the integrated packaging of a memory chip includes but is not limited to at least one of the electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiment of the present application. In other words, the method for implementing the integrated packaging of a memory chip can be executed by software or hardware installed on a terminal device or a server device. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0073] Embodiment 1:

[0074] Reference Figure 1 FIG. 1 is a flow chart of a method for implementing an integrated packaging of a memory chip according to an embodiment of the present invention. In this embodiment, the method for implementing an integrated packaging of a memory chip includes:

[0075] S1. Obtain a memory chip to be processed, collect chip test data corresponding to the memory chip, identify test indicators corresponding to the chip test data, and calculate the quality credibility corresponding to the memory chip by combining the test indicators and the chip test data.

[0076] The present invention calculates the quality credibility corresponding to the storage chip by combining the test indicators and the chip test data. The chip quality corresponding to the storage chip can be understood through the quality credibility, thereby providing a reliable basis for subsequently screening out high-quality storage chips from the storage chip. It should be explained that the storage chip is a specific storage chip product, the chip test data is the relevant data obtained by the storage chip in various tests, the test indicators are standards set based on the chip test data for measuring various aspects of chip performance and quality, and the quality credibility indicates the degree to which the storage chip can be trusted in terms of quality. Furthermore, the collection of chip test data corresponding to the storage chip can be achieved through automated testing equipment; the identification of the test indicators corresponding to the chip test data can be achieved through a recognition algorithm, such as a random forest algorithm.

[0077] In detail, the combining the test index and the chip test data to calculate the quality credibility corresponding to the memory chip includes:

[0078] Calculating a data standard deviation and a data mean of the chip test data, and calculating a data coefficient of variation corresponding to the chip test data based on the data standard deviation and the data mean;

[0079] According to the data variation coefficient, performing data error correction processing on the chip test data to obtain target test data;

[0080] The quality credibility corresponding to the storage chip is calculated by combining the target test data and the test index.

[0081] It should be explained that the data standard deviation and the data mean respectively represent the degree of discreteness and the data mean value of the chip test data, the data coefficient of variation represents the degree of discreteness corresponding to the chip test data, and the target test data is the data obtained after correcting the erroneous data in the chip test data.

[0082] Furthermore, the data standard deviation and data mean of the chip test data can be calculated respectively by the standard deviation formula and the average function; the ratio between the data standard deviation and the data mean is calculated to obtain the data variation coefficient corresponding to the chip test data; based on the data variation coefficient, the variant data in the chip test data is determined, and the data average value is used to perform data error correction processing on the variant data to obtain the target test data.

[0083] Further, as an optional embodiment of the present invention, the combining the target test data and the test index to calculate the quality credibility corresponding to the storage chip includes:

[0084] Performing standardization processing on the target test data to obtain standard test data;

[0085] Calculate the grey correlation between each indicator in the test indicators;

[0086] Based on the grey correlation degree, weights are assigned to the test indicators to obtain indicator weights;

[0087] The quality credibility corresponding to the storage chip is calculated by combining the indicator weight and the standard test data.

[0088] It should be explained that the standard test data is comparable data obtained after the differences between the target test data are eliminated, the grey correlation degree represents the degree of correlation between each indicator in the test indicators, and the indicator weight represents the corresponding importance of the test indicators.

[0089] Furthermore, the standardization processing of the target test data can be achieved through the Z-score standardization method; the calculation of the grey correlation between each indicator in the test indicator can be achieved through the generalized grey correlation method; each correlation in the grey correlation is divided by the sum of the correlations to obtain the indicator weight of the test indicator; the indicator weight is multiplied by the value corresponding to the standard test data and the sum is obtained to obtain the quality credibility corresponding to the storage chip.

[0090] S2. Detecting surface damage scratches on the memory chip, calculating a cracking strength threshold corresponding to the memory chip based on the surface damage scratches, and selecting high-quality memory chips from the memory chips by combining the quality credibility and the cracking strength threshold.

[0091] By detecting the surface damage scratches of the memory chip, the present invention can timely discover the damage defects on the surface of the memory chip, and then understand the corresponding loss degree of the memory chip, laying a foundation for the subsequent calculation of the cracking strength threshold corresponding to the memory chip. It should be explained that the surface damage scratches are the surface damage of the memory chip.

[0092] In detail, the detection of surface damage and scratches on the memory chip includes:

[0093] Collecting a chip surface image corresponding to the storage chip, and performing a main body segmentation process on the chip surface image to obtain a chip main body surface image;

[0094] Performing grayscale processing on the chip main body appearance image to obtain a grayscale appearance image;

[0095] Calculating the pixel gradient intensity corresponding to each pixel in the grayscale apparent image, and extracting the apparent mutation area in the grayscale apparent image based on the pixel gradient intensity;

[0096] Extracting regional appearance features corresponding to the epigenetic mutation region based on the main epigenetic image of the chip;

[0097] Based on the regional surface features, surface damage and scratches of the memory chip are detected.

[0098] It should be explained that the chip apparent image is a visualization image corresponding to the storage chip; the chip body apparent image is an image obtained by removing images irrelevant to the chip body from the chip apparent image; the grayscale apparent image is an image of the chip body apparent image expressed in grayscale; the pixel gradient intensity represents the degree of grayscale change corresponding to each pixel in the grayscale apparent image; the apparent mutation area is an area in the grayscale apparent image where the grayscale value suddenly changes; the regional apparent feature is a unique attribute corresponding to the apparent mutation area.

[0099] Furthermore, the collection of the chip apparent image corresponding to the storage chip can be achieved through a camera device; the main segmentation processing of the chip apparent image can be achieved through a threshold segmentation method; the grayscale processing of the chip main apparent image can be achieved through an average method; the calculation of the pixel gradient intensity corresponding to each pixel in the grayscale apparent image can be achieved through a Roberts operator; when the pixel gradient intensity is greater than a preset intensity, the apparent mutation area in the grayscale apparent image can be extracted through manual processing, and the preset intensity can be set according to the actual application scenario; image features corresponding to the apparent mutation area are extracted from the chip main body apparent image, such as texture features, color and other features, and regional apparent features are obtained based on the image features; the regional apparent features are compared with preset scratch features to detect surface damage scratches on the storage chip. If the regional features are highly consistent with the scratch features, it can be determined that the region has surface damage scratches, otherwise it indicates that there are no obvious scratches in this region.

[0100] The present invention calculates the cracking strength threshold corresponding to the memory chip based on the surface damage scratches, thereby understanding the ultimate strength that the memory chip can withstand, and then analyzing the chip stability corresponding to the memory chip, thereby improving the accuracy of subsequent high-quality memory chip screening. It should be explained that the cracking strength threshold represents the ultimate strength value of the memory chip corresponding to the external force.

[0101] Specifically, the calculating the cracking strength threshold corresponding to the memory chip based on the surface damage scratches includes:

[0102] Based on the surface damage scratches, determining a chip flaw detection position corresponding to the memory chip;

[0103] Using a preset flaw detection device to measure the flaw detection parameter information corresponding to the flaw detection position of the chip;

[0104] Based on the flaw detection parameter information, determining the damage depth and damage length corresponding to the surface damage scratch;

[0105] In combination with the damage depth and the damage length, the cracking intensity threshold corresponding to the memory chip can be calculated by the following formula:

[0106]

[0107] Among them, A represents the cracking strength threshold corresponding to the memory chip, α represents the stress intensity factor, β represents the crack geometry factor, B represents the damage depth, and D represents the damage length.

[0108] It should be explained that the chip flaw detection position is the position corresponding to the surface damage scratch in the storage chip, the flaw detection equipment is an instrument for detecting relevant parameters of surface damage of materials or workpieces, such as an ultrasonic flaw detector, and the flaw detection parameter information is the specific numerical information corresponding to the chip flaw detection position. The stress intensity factor represents a measure of the stress field strength near the crack tip, and the crack geometry factor represents a coefficient related to the crack geometry and size and used to correct the calculation of the stress intensity factor. Both can be obtained by looking up in the chip engineering manual. Many engineering fields have relevant manuals and standards, which contain calculation formulas, charts or data for stress intensity factors and crack geometry factors of various common components and crack conditions; further, the chip flaw detection position corresponding to the storage chip can be determined by the position corresponding to the surface damage scratch.

[0109] The present invention selects high-quality memory chips from the memory chips by combining the quality credibility and the cracking strength threshold, thereby obtaining the memory chips with the highest quality. Furthermore, by combining the quality credibility and the cracking strength threshold, high-quality memory chips are selected from the memory chips. For example, the quality credibility of the memory chip 1 is as high as 95%, and its cracking strength threshold is much higher than the industry standard, which indicates that the memory chip 1 is guaranteed in terms of structural strength and quality, and can be determined as a high-quality memory chip.

[0110] S3. Query the design layout and signal transmission protocol corresponding to the memory chip, determine the chip pin layout corresponding to the memory chip based on the design layout, and plan the packaging sequence corresponding to the memory chip according to the signal transmission protocol.

[0111] The present invention determines the chip pin layout corresponding to the memory chip based on the design layout, and can obtain the specific position distribution of each pin of the memory chip on the chip, thereby facilitating the calculation of the pin coordination between each chip in the subsequent packaging sequence. According to the signal transmission protocol, the packaging sequence corresponding to the memory chip is planned, and the order of packaging processing corresponding to the memory chip can be obtained. It should be explained that the design layout is the circuit design architecture corresponding to the memory chip, and the signal transmission protocol is a set of rules for the memory chip to specify the signal transmission mode, timing, level standard and data format, etc., which is used to ensure accurate and stable data communication between the chip and external devices. The chip pin layout is the position distribution of each pin corresponding to the memory chip on the chip surface. Furthermore, the query of the design layout and signal transmission protocol corresponding to the memory chip can be obtained from the Internet through manual interaction.

[0112] In detail, planning the packaging sequence corresponding to the memory chip according to the signal transmission protocol includes:

[0113] Identifying a transmission protocol text in the signal transmission protocol, and analyzing a signal transmission function corresponding to the signal transmission protocol based on the transmission protocol text;

[0114] Mining the function description information corresponding to the signal transmission function, and extracting the function descriptor in the function description information;

[0115] Determining a transmission protocol element of the signal transmission function based on the functional descriptor;

[0116] Extracting protocol input elements and protocol output elements from the transmission protocol elements;

[0117] According to the protocol input elements and the protocol output elements, a packaging sequence corresponding to the storage chip is planned.

[0118] It should be explained that the transmission protocol text is the descriptive text in the signal transmission protocol, the signal transmission function is the behavioral performance and capability embodiment of the specific implementation and execution of the signal transmission protocol, the functional description information is a comprehensive interpretation of various aspects corresponding to the signal transmission function, the functional descriptor is the information description feature in the functional description information, the transmission protocol element is the core factor of the signal transmission function, the protocol input element and the protocol output element are respectively the input element and output element in the transmission protocol element. For example, in the TCP / IP protocol, the protocol input element is the data packet, source address, destination address, etc. that the sender is ready to send, which are input into the protocol process, and the protocol output element is the correctly parsed information, confirmation receipt, and other related content received by the receiving end after being processed by the protocol.

[0119] Further, the transmission protocol text in the signal transmission protocol can be identified by OCR recognition technology; the transmission protocol text is semantically analyzed to obtain the protocol text semantics, and the signal transmission function corresponding to the signal transmission protocol is analyzed according to the protocol text semantics; the mining of the functional description information corresponding to the signal transmission function can be realized by a mining algorithm, such as a natural language processing algorithm; based on the functional descriptor, the transmission protocol elements of the signal transmission function are determined, such as a detailed analysis of the functional descriptor to sort out the key description contents related to the protocol such as communication rules, data formats, interaction mechanisms, etc., and then, based on these sorted out key contents, specific transmission protocol elements such as data transmission sequence, verification method, handshake mechanism, etc. are correspondingly extracted to clarify the protocol requirements in the signal transmission function; the protocol input elements and protocol output elements are extracted from the transmission protocol elements, which can be realized by text analysis of the transmission protocol elements, clarifying that the information specified therein to enter the protocol processing flow is the protocol input element, and determining the results and feedback generated after the protocol processing as the protocol output elements; according to the protocol input elements and the protocol output elements, the causal relationship between the storage chips is analyzed, and the packaging sequence corresponding to the storage chip is planned according to the causal relationship.

[0120] Further, as an optional embodiment of the present invention, the extracting the function descriptor in the function description information includes:

[0121] Calculating information entropy corresponding to the function description information, and extracting key function description information from the function description information according to the information entropy;

[0122] Performing word segmentation processing on the key function description information to obtain description information word segmentation;

[0123] Calculate the quantitative feature value corresponding to the description information segmentation, and calculate the expected feature value corresponding to the description information segmentation;

[0124] Combining the quantitative feature value and the expected feature value, the segmentation association strength between the description information segmentations can be calculated by the following formula:

[0125]

[0126] Among them, R represents the strength of the word association between the description information words, Q a Indicates the quantitative feature value corresponding to the a-th word in the description information word. represents the expected feature value corresponding to the ath word in the description information segmentation, Q a+1 Indicates the quantitative feature value corresponding to the a+1th word in the description information word. represents the expected feature value corresponding to the a+1th word in the description information word, and a and a+1 both represent the sequence number of the description information word;

[0127] According to the segmentation association strength, the description information segmentation is filtered to obtain the target information segmentation;

[0128] Based on the target information segmentation, a function descriptor in the function description information is generated.

[0129] It should be explained that the information entropy represents the degree of uncertainty corresponding to the function description information, and can represent the importance of the function description information. The key function description information is the important core content of the function description information. The description information segmentation is the splitting unit of the key function description information. The quantitative feature value is the quantifiable attribute value corresponding to the description information segmentation, such as word frequency. The expected feature value is the average quantitative attribute value corresponding to the description information segmentation. The target information segmentation is the segmentation with the highest segmentation association strength among the description information segmentations.

[0130] Furthermore, the information entropy corresponding to the function description information can be calculated by the Shannon entropy algorithm, and the key function description information in the function description information can be extracted according to the numerical value of the information entropy, and the information with the largest numerical value of the information entropy among the information of the same type is selected to obtain the key function description information; the word segmentation processing of the key function description information can be implemented by a word segmentation tool, such as the Jieba word segmentation tool; the calculation of the quantitative feature value corresponding to the description information word segmentation can be implemented by a word frequency statistics algorithm; the expected feature value corresponding to the description information word segmentation can be implemented by an average function; the word segmentation filtering of the description information word segmentation can be implemented by a filtering function, and the filtering function is compiled by a scripting language, such as the JS scripting language; based on the target information word segmentation, the function descriptor in the function description information is generated according to custom rules, and the custom rules can be set manually.

[0131] S4. According to the chip pin layout, the pin coordination between each chip in the packaging sequence is calculated, and the mechanical behavior simulation processing is performed on the storage chip. When the storage chip reaches the preset simulation conditions in the mechanical behavior simulation processing, the temperature simulation data and the mechanical simulation data in the mechanical simulation processing are recorded, and the thermal expansion coefficient corresponding to the storage chip is calculated based on the temperature simulation data, and the chip fatigue coefficient corresponding to the storage chip is calculated based on the mechanical simulation data.

[0132] The present invention calculates the pin coordination degree between each chip in the packaging sequence based on the chip pin layout, and the pin coordination degree can be used to understand the degree of coordination between each chip in the packaging sequence, thereby improving the accuracy of sequence adjustment of the packaging sequence. It should be explained that the pin coordination degree represents the degree of coordination between each chip in the packaging sequence.

[0133] In detail, the calculating the pin coordination degree between each chip in the packaging sequence according to the chip pin layout includes:

[0134] According to the chip pin layout, establishing a chip layout coordinate system corresponding to the packaging sequence;

[0135] Based on the chip layout coordinate system, determining the chip pin coordinates corresponding to each chip in the packaging sequence;

[0136] Based on the chip pin coordinates, calculating the pin distance between each chip in the packaging sequence;

[0137] In combination with the pin distance and the preset distance threshold, the pin coordination degree between each chip in the packaging sequence can be calculated by the following formula:

[0138]

[0139] Among them, H represents the pin coordination between each chip in the packaging sequence, e represents the natural constant, ω represents the sensitivity coefficient, and E b，d Indicates the pin distance between the bth chip and the dth chip in the packaging sequence, E , represents the preset distance threshold, and b and d represent the chip serial numbers in the packaging sequence.

[0140] It should be explained that the chip layout coordinate system is a reference system for determining the chip position in the package corresponding to the packaging sequence, the chip pin coordinates are a quantitative representation of the pin position of each chip in the packaging sequence in the chip layout coordinate system, the preset distance threshold is a reference distance value between chips, which can be obtained through industry general standards, the sensitivity coefficient represents the regulating effect of the sensitivity of the relationship between pin distance and position matching, and the sensitivity coefficient can be obtained through experimental research, such as conducting special experimental research, measuring the linear relationship between distance and position matching, and thereby obtaining the corresponding sensitivity coefficient. Furthermore, the chip layout coordinate system corresponding to the packaging sequence can be established through a coordinate tool, and the coordinate tool is compiled in JAVA language; based on the chip pin coordinates, the pin distance between each chip in the packaging sequence can be calculated through the Euclidean distance algorithm.

[0141] The present invention performs mechanical behavior simulation processing on the memory chip. When the memory chip reaches a preset simulation condition in the mechanical behavior simulation processing, the temperature simulation data and chip deformation data in the mechanical simulation processing are recorded, thereby obtaining detailed simulation record data of the memory chip. Based on the temperature simulation data and the chip deformation data, the thermal expansion coefficient corresponding to the memory chip is calculated, so that the mechanical elastic properties of the memory chip at different temperatures can be understood. It should be explained that the mechanical behavior simulation is a simulated behavior of heating the memory chip, the preset simulation condition is a mechanical simulation reference condition of the memory chip, the temperature simulation data is a data record related to the temperature applied to the chip during the mechanical behavior simulation processing, and the chip deformation data is a data record reflecting the change in chip shape during the mechanical behavior simulation processing.

[0142] Specifically, the calculating the thermal expansion coefficient corresponding to the memory chip based on the temperature simulation data and the chip deformation data includes:

[0143] Respectively extracting the simulation temperature value and the chip deformation amount in the temperature simulation data and the chip deformation data, and recording the initial deformation length corresponding to the chip deformation amount;

[0144] Aligning the simulation temperature value and the chip deformation amount to obtain an aligned temperature value and an aligned deformation amount;

[0145] In combination with the alignment temperature value, the alignment deformation amount and the initial length of the deformation, the thermal expansion coefficient corresponding to the memory chip can be calculated as follows:

[0146]

[0147] Among them, F represents the thermal expansion coefficient corresponding to the memory chip, △M n and △M n-1 They represent the chip deformation corresponding to the simulation temperature values ​​at time n and time n-1, respectively. n and n-1 both represent the time series number of the simulation temperature value. n and T n-1 Respectively represent the simulation temperature values ​​corresponding to time n and time n-1, M n-1 Indicates the initial deformation length when the simulation temperature value is n-1.

[0148] It should be explained that the simulated temperature value and the chip deformation variable are respectively the specific temperature value and the change in deformation in the temperature simulation data and the chip deformation data, the initial deformation length is the initial chip record length of the chip deformation variable, the aligned temperature value and the aligned deformation variable are the temperature value and the deformation variable obtained after the simulated temperature value and the chip deformation variable are aligned according to the time series. Furthermore, the simulated temperature value and the chip deformation variable in the temperature simulation data and the chip deformation data can be extracted respectively by an extraction algorithm, and the extraction algorithm is compiled by a programming language; alignment processing is performed according to the timestamps corresponding to the simulated temperature value and the chip deformation variable to obtain the aligned temperature value and the aligned deformation variable.

[0149] S5. Combining the thermal expansion coefficient and the pin coordination degree, adjusting the packaging sequence to obtain an optimal packaging sequence, and based on the optimal packaging sequence, performing packaging processing on the memory chip to obtain a packaged chip.

[0150] The present invention adjusts the packaging sequence in sequence by combining the thermal expansion coefficient and the pin coordination, and can obtain the best packaging sequence to improve the packaging stability of the subsequent memory chip. Further, the packaging sequence is adjusted in sequence by combining the thermal expansion coefficient and the pin coordination to obtain the best packaging sequence. For example, if the thermal expansion coefficient of chip 1 is large and the pin layout is dense, while chip 2 is the opposite, during packaging, according to the difference in thermal expansion coefficients and the pin coordination between the two, chip 1 is placed at a position with a better heat dissipation path and sufficient space to accommodate thermal expansion, and chip 2 is placed close to an area with lower space requirements. Through such sequence adjustment, when the temperature of the package changes, the stress generated by thermal expansion and contraction between the pins can be evenly dispersed, avoiding loosening or breaking of the pins due to excessive local stress, thereby obtaining the best packaging sequence and improving the overall packaging reliability and chip performance. The best packaging sequence can be input into the corresponding packaging process equipment control system to perform packaging processing on the memory chip. The packaging process equipment control system is a system that accurately controls and manages the operation, operation and related parameters of the packaging process equipment.

[0151] Compared with the problems described in the background technology, the present invention calculates the quality credibility corresponding to the storage chip by combining the test index and the chip test data, and can understand the chip quality corresponding to the storage chip through the quality credibility, thereby providing a reliable basis for subsequently screening out high-quality storage chips from the storage chips. The present invention can timely discover the damage defects on the surface of the storage chip by detecting the surface damage scratches of the storage chip, thereby understanding the corresponding loss degree of the storage chip, laying a foundation for the subsequent calculation of the cracking strength threshold corresponding to the storage chip. The present invention determines the chip pin layout corresponding to the storage chip based on the design layout, and can obtain the position of each pin of the storage chip in the chip. The specific position distribution on the packaging sequence is convenient for calculating the pin coordination between each chip in the subsequent packaging sequence. According to the signal transmission protocol, the packaging sequence corresponding to the memory chip is planned, and the order of packaging processing corresponding to the memory chip can be obtained. The present invention calculates the pin coordination between each chip in the packaging sequence according to the chip pin layout. The degree of coordination between each chip in the packaging sequence can be understood through the pin coordination, thereby improving the accuracy of sequence adjustment of the packaging sequence. The present invention adjusts the packaging sequence by combining the thermal expansion coefficient and the pin coordination, and can obtain the optimal packaging sequence to improve the packaging stability of the subsequent memory chip. Therefore, the present invention proposes a method for realizing integrated packaging of memory chips, thereby improving the integrated packaging stability of memory chips.

[0152] Embodiment 2:

[0153] like Figure 2 1 is a functional module diagram of an integrated packaging system for implementing a memory chip provided by an embodiment of the present invention.

[0154] The integrated packaging system 100 for implementing a memory chip described in the present invention can be installed in an electronic device. According to the functions implemented, the integrated packaging system 100 for implementing a memory chip can include a quality credibility calculation module 101, a chip screening module 102, a sequence planning module 103, a thermal expansion coefficient calculation module 104 and a chip packaging module 105. The module described in the present invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0155] In this embodiment, the functions of each module / unit are as follows:

[0156] The quality credibility calculation module 101 is used to obtain the memory chip to be processed, collect chip test data corresponding to the memory chip, identify the test index corresponding to the chip test data, and calculate the quality credibility corresponding to the memory chip by combining the test index and the chip test data;

[0157] The chip screening module 102 is used to detect surface damage scratches on the memory chip, calculate the cracking strength threshold corresponding to the memory chip based on the surface damage scratches, and screen out high-quality memory chips from the memory chips by combining the quality credibility and the cracking strength threshold;

[0158] The sequence planning module 103 is used to query the design layout and signal transmission protocol corresponding to the memory chip, determine the chip pin layout corresponding to the memory chip based on the design layout, and plan the packaging sequence corresponding to the memory chip according to the signal transmission protocol;

[0159] The thermal expansion coefficient calculation module 104 is used to calculate the pin coordination between each chip in the packaging sequence according to the chip pin layout, perform mechanical behavior simulation processing on the storage chip, and when the storage chip reaches a preset simulation condition in the mechanical behavior simulation processing, record the temperature simulation data and chip deformation data in the mechanical simulation processing process, and calculate the thermal expansion coefficient corresponding to the storage chip based on the temperature simulation data and the chip deformation data;

[0160] The chip packaging module 105 is used to adjust the packaging sequence in combination with the thermal expansion coefficient and the pin coordination degree to obtain an optimal packaging sequence, and based on the optimal packaging sequence, perform packaging processing on the memory chip to obtain a packaged chip.

[0161] In detail, each module described in the integrated packaging system 100 for implementing a memory chip described in the embodiment of the present application is used in the same manner as described above. Figure 1 The same technical means as described in the integrated packaging method for realizing the memory chip and can produce the same technical effect are not described here.

[0162] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0163] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for realizing integrated packaging of a memory chip, characterized in that: The method comprises: Acquire a memory chip to be processed, collect chip test data corresponding to the memory chip, identify test indicators corresponding to the chip test data, and calculate the quality credibility corresponding to the memory chip by combining the test indicators and the chip test data; Detecting surface damage scratches on the memory chip, calculating a cracking strength threshold corresponding to the memory chip based on the surface damage scratches, and selecting high-quality memory chips from the memory chips by combining the quality credibility and the cracking strength threshold; Querying the design layout and signal transmission protocol corresponding to the memory chip, determining the chip pin layout corresponding to the memory chip based on the design layout, and planning the packaging sequence corresponding to the memory chip according to the signal transmission protocol; According to the chip pin layout, the pin coordination degree between each chip in the packaging sequence is calculated, and the mechanical behavior simulation processing is performed on the memory chip. When the memory chip reaches a preset simulation condition in the mechanical behavior simulation processing, the temperature simulation data and the chip deformation data in the mechanical simulation processing are recorded, and the thermal expansion coefficient corresponding to the memory chip is calculated based on the temperature simulation data and the chip deformation data; The packaging sequence is adjusted in combination with the thermal expansion coefficient and the pin coordination degree to obtain an optimal packaging sequence. Based on the optimal packaging sequence, the packaging process of the memory chip is performed to obtain a packaged chip.

2. The method for implementing integrated packaging of a memory chip according to claim 1, characterized in that: The calculating the quality credibility corresponding to the memory chip by combining the test index and the chip test data includes: Calculating a data standard deviation and a data mean of the chip test data, and calculating a data coefficient of variation corresponding to the chip test data based on the data standard deviation and the data mean; According to the data variation coefficient, performing data error correction processing on the chip test data to obtain target test data; The quality credibility corresponding to the storage chip is calculated by combining the target test data and the test index.

3. The method for implementing integrated packaging of a memory chip according to claim 2, characterized in that: The step of calculating the quality credibility of the storage chip in combination with the target test data and the test index includes: Performing standardization processing on the target test data to obtain standard test data; Calculate the grey correlation between each indicator in the test indicators; Based on the grey relational degree, weights are assigned to the test indicators to obtain indicator weights; The quality credibility corresponding to the storage chip is calculated by combining the indicator weight and the standard test data.

4. The method for implementing integrated packaging of a memory chip according to claim 1, characterized in that: The detecting of surface damage and scratches on the memory chip comprises: Collecting a chip surface image corresponding to the storage chip, and performing a main body segmentation process on the chip surface image to obtain a chip main body surface image; Performing grayscale processing on the chip main body appearance image to obtain a grayscale appearance image; Calculating the pixel gradient intensity corresponding to each pixel in the grayscale apparent image, and extracting the apparent mutation area in the grayscale apparent image based on the pixel gradient intensity; Extracting regional appearance features corresponding to the epigenetic mutation region based on the main epigenetic image of the chip; Based on the regional surface features, surface damage and scratches of the memory chip are detected.

5. The method for implementing integrated packaging of a memory chip according to claim 1, characterized in that: The calculating the cracking intensity threshold corresponding to the memory chip based on the surface damage scratches includes: Based on the surface damage scratches, determining a chip flaw detection position corresponding to the memory chip; Using a preset flaw detection device to measure the flaw detection parameter information corresponding to the flaw detection position of the chip; Based on the flaw detection parameter information, determining the damage depth and damage length corresponding to the surface damage scratch; In combination with the damage depth and the damage length, the cracking intensity threshold corresponding to the memory chip can be calculated by the following formula: Among them, A represents the cracking strength threshold corresponding to the memory chip, α represents the stress intensity factor, β represents the crack geometry factor, B represents the damage depth, and D represents the damage length.

6. The method for implementing integrated packaging of a memory chip according to claim 1, characterized in that: The step of planning a packaging sequence corresponding to the memory chip according to the signal transmission protocol includes: Identifying a transmission protocol text in the signal transmission protocol, and analyzing a signal transmission function corresponding to the signal transmission protocol based on the transmission protocol text; Mining the function description information corresponding to the signal transmission function, and extracting the function descriptor in the function description information; Determining a transmission protocol element of the signal transmission function based on the functional descriptor; Extracting protocol input elements and protocol output elements from the transmission protocol elements; According to the protocol input elements and the protocol output elements, a packaging sequence corresponding to the storage chip is planned.

7. The method for implementing integrated packaging of a memory chip according to claim 6, characterized in that: The extracting the function descriptor from the function description information comprises: Calculating information entropy corresponding to the function description information, and extracting key function description information from the function description information according to the information entropy; Performing word segmentation processing on the key function description information to obtain description information word segmentation; Calculate the quantitative feature value corresponding to the description information segmentation, and calculate the expected feature value corresponding to the description information segmentation; Combining the quantitative feature value and the expected feature value, the segmentation association strength between the description information segmentations can be calculated by the following formula: Among them, R represents the strength of the word association between the description information words, Q a Indicates the quantitative feature value corresponding to the a-th word in the description information word. represents the expected feature value corresponding to the ath word in the description information segmentation, Q a+1 Indicates the quantitative feature value corresponding to the a+1th word in the description information word. represents the expected feature value corresponding to the a+1th word in the description information word, and a and a+1 both represent the sequence number of the description information word; According to the segmentation association strength, the description information segmentation is filtered to obtain the target information segmentation; Based on the target information segmentation, a function descriptor in the function description information is generated.

8. The method for implementing integrated packaging of a memory chip according to claim 1, characterized in that: The step of calculating the pin coordination degree between each chip in the packaging sequence according to the chip pin layout includes: According to the chip pin layout, establishing a chip layout coordinate system corresponding to the packaging sequence; Based on the chip layout coordinate system, determining the chip pin coordinates corresponding to each chip in the packaging sequence; Based on the chip pin coordinates, calculating the pin distance between each chip in the packaging sequence; In combination with the pin distance and the preset distance threshold, the pin coordination degree between each chip in the packaging sequence can be calculated by the following formula: Among them, H represents the pin coordination between each chip in the packaging sequence, e represents the natural constant, ω represents the sensitivity coefficient, and E b，d represents the pin distance between the bth chip and the dth chip in the packaging sequence, E , represents the preset distance threshold, and b and d represent the chip serial numbers in the packaging sequence.

9. The method for implementing integrated packaging of a memory chip according to claim 1, characterized in that: The calculating the thermal expansion coefficient corresponding to the memory chip based on the temperature simulation data and the chip deformation data includes: Respectively extracting the simulation temperature value and the chip deformation amount in the temperature simulation data and the chip deformation data, and recording the initial deformation length corresponding to the chip deformation amount; Aligning the simulation temperature value and the chip deformation amount to obtain an alignment temperature value and an alignment deformation amount; In combination with the alignment temperature value, the alignment deformation amount and the initial length of the deformation, the thermal expansion coefficient corresponding to the memory chip can be calculated as follows: Among them, F represents the thermal expansion coefficient corresponding to the memory chip, △M n and △M n-1 They represent the chip deformation corresponding to the simulation temperature values ​​at time n and time n-1, respectively. n and n-1 both represent the time series number of the simulation temperature value. n and T n-1 Respectively represent the simulation temperature values ​​corresponding to time n and time n-1, M n-1 Indicates the initial deformation length when the simulation temperature value is n-1.

10. An integrated packaging system for implementing a memory chip, characterized in that: The system comprises: A quality credibility calculation module is used to obtain a memory chip to be processed, collect chip test data corresponding to the memory chip, identify a test index corresponding to the chip test data, and calculate the quality credibility corresponding to the memory chip by combining the test index and the chip test data; A chip screening module, used to detect surface damage scratches of the memory chip, calculate a cracking strength threshold corresponding to the memory chip based on the surface damage scratches, and screen out high-quality memory chips from the memory chips by combining the quality credibility and the cracking strength threshold; A sequence planning module, used to query the design layout and signal transmission protocol corresponding to the memory chip, determine the chip pin layout corresponding to the memory chip based on the design layout, and plan the packaging sequence corresponding to the memory chip according to the signal transmission protocol; a thermal expansion coefficient calculation module, for calculating the pin coordination between each chip in the packaging sequence according to the chip pin layout, performing mechanical behavior simulation processing on the storage chip, recording temperature simulation data and chip deformation data during the mechanical simulation processing when the storage chip reaches a preset simulation condition, and calculating the thermal expansion coefficient corresponding to the storage chip based on the temperature simulation data and the chip deformation data; The chip packaging module is used to adjust the packaging sequence in combination with the thermal expansion coefficient and the pin coordination degree to obtain an optimal packaging sequence, and based on the optimal packaging sequence, perform packaging processing on the memory chip to obtain a packaged chip.

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