Integrated circuit, system on chip and electronic equipment

Abstract

The invention provides an integrated circuit, a system on chip and electronic equipment, which are applied to the technical field of computers, the integrated circuit comprises at least one first bare chip, one second bare chip and one third bare chip, the first bare chip, the second bare chip and the third bare chip are sequentially stacked in the vertical direction, the second bare chip is located on the second top layer, and the third bare chip is located on the second top layer. The first bare chip is located on the top layer, the second bare chip is located on the bottom layer, the third bare chip is located on the top layer, the first bare chips, the second bare chips and the third bare chips are sequentially cascaded, further, any first bare chip is further connected with another bare chip spaced by one bare chip, and the circuit can directly cross an abnormal bare chip to communicate with another bare chip spaced by the abnormal bare chip under the condition that any first bare chip or the second bare chip is abnormal. Therefore, under the condition that the abnormal bare chip is cut off, normal communication among the other bare chips is ensured, all the bare chips located at the downstream of the abnormal bare chip in the signal transmission direction can continue to operate, and the reliability and robustness of the chip are effectively improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an integrated circuit, a system on a chip, and an electronic device. Background Art

[0002] With the advent of the post-Moore era, 3D chip technology has become one of the important directions for continuing to improve chip performance. By integrating multiple dies inside the chip, the dies are interconnected through TSV (Through Silicon Via) to make the chip a whole, thereby achieving more powerful functions.

[0003] However, in existing applications, communication signals are transmitted layer by layer in the bare chips at each level. This transmission method results in that when any bare chip becomes abnormal or the operating temperature is too high and needs to be powered off and exited, all bare chips downstream of the bare chip in the signal transmission direction will not be able to continue to operate, and may even affect the normal operation of the entire chip, resulting in poor chip reliability and robustness. Summary of the invention

[0004] In view of this, the present application is dedicated to providing an integrated circuit, a system on chip and an electronic device to solve the problem of poor chip reliability and robustness in the prior art.

[0005] In a first aspect, the present application provides an integrated circuit, comprising: at least one first die, a second die, and a third die, wherein:

[0006] The first die, the second die and the third die are stacked in sequence in a vertical direction, and the second die is located at the second top layer, and the third die is located at the top layer;

[0007] The first die, the second die and the third die are cascaded in sequence;

[0008] Any of the first dies is also connected to another die that is spaced one die apart.

[0009] In an optional embodiment, the first bare chip includes a first communication module, wherein:

[0010] The input end of the first communication module is used to receive a communication signal;

[0011] The first output end of the first communication module is used for cascading with an adjacent die, and the second output end of the first communication module is used for connecting with another die separated by one die;

[0012] The first communication module provides a communication signal to the first output terminal or the second output terminal in response to a selection signal.

[0013] In an optional implementation, the strobe signal includes a first strobe signal and a second strobe signal, wherein:

[0014] The first communication module provides a communication signal to the first output terminal in response to the first selection signal, wherein the first selection signal is generated when the die connected to the first output terminal is in an operating state;

[0015] The first communication module provides a communication signal to the second output terminal in response to the second selection signal, and the second selection signal is generated when the die connected to the first output terminal is in a power-off state.

[0016] In an optional implementation, for the first first bare chip in the sequentially cascaded first bare chips, the first first bare chip further includes a signal generating module;

[0017] The signal generating module is connected to the input end of the first communication module of the first first bare chip;

[0018] The signal generating module is used for providing a communication signal.

[0019] In an optional implementation, the first communication module includes a gating module, a first through silicon via TSV and a second TSV, wherein:

[0020] One end of the first TSV serves as the first output end, and the other end of the first TSV is connected to the first gating output end of the gating module;

[0021] One end of the second TSV serves as the second output end, and the other end of the second TSV is connected to the second selection output end of the selection module;

[0022] The gating input terminal of the gating module is used to receive a communication signal;

[0023] The control end of the gating module is used to receive the gating signal;

[0024] The gating module connects the gating input terminal and the first gating output terminal, or connects the gating input terminal and the second gating output terminal in response to the gating signal.

[0025] In an optional implementation, for any first die, the first TSV and the second TSV are disposed on different sides of the first die.

[0026] In an optional implementation, the first dies are stacked in sequence in the vertical direction, and the first dies in even-numbered layers are rotated 180° along the central axis in the vertical direction.

[0027] In an optional implementation, for any first die, the first TSV and the second TSV are disposed on the same side of the first die.

[0028] In an optional implementation, the integrated circuit provided in the first aspect of the present application further includes: a controller, wherein:

[0029] The controller is respectively connected to the first communication modules of the first bare chips to provide the selection signal to the first communication modules.

[0030] In an optional embodiment, the second bare chip includes a second communication module, wherein:

[0031] The input end of the second communication module is used to receive a communication signal of a first die adjacent to the second die;

[0032] An output terminal of the second communication module is connected to the third bare chip.

[0033] In a second aspect, the present application provides a system on chip, comprising an integrated circuit as described in any one of the first aspect of the present application.

[0034] In a third aspect, the present application provides an electronic device, comprising the system on chip as described in the second aspect of the present application.

[0035] Based on the above content, the integrated circuit provided by the present application includes at least one first die, a second die and a third die. The first die, the second die and the third die are stacked in sequence in the vertical direction, and the second die is located at the second top layer, and the third die is located at the top layer. The first die, the second die and the third die are cascaded in sequence. Furthermore, any first die is also connected to another die separated by one die. It can be seen that the integrated circuit provided by the present application can directly cross the abnormal die and communicate with the other die separated by the abnormal die in the case that any first die or the second die is abnormal, so as to achieve normal communication between the remaining die when the abnormal die is removed, and all the die located downstream of the abnormal die in the signal transmission direction can continue to operate, effectively improving the reliability and robustness of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1It is a schematic diagram of the internal bare die interconnection of a 3D chip in the prior art.

[0038] Figure 2 It is a structural schematic diagram of an integrated circuit provided by this application.

[0039] Figure 3 It is a schematic diagram of the structure of another integrated circuit provided by the present application.

[0040] Figure 4 It is a structural diagram of the first communication module provided in this application.

[0041] Figure 5 It is a schematic diagram of the changing trend of the number of TSVs used in the integrated circuit provided by the present application and the integrated circuit in the prior art.

[0042] Figure 6 It is a planar schematic diagram of an application scenario of an integrated circuit provided in this application.

[0043] Figure 7 It is a three-dimensional schematic diagram of an application scenario of an integrated circuit provided in this application.

[0044] Figure 8 It is a schematic diagram of a three-dimensional structure of an integrated circuit provided by the present application.

[0045] Fig. 9 It is a schematic diagram of the process of rotating a die in the present application.

[0046] Fig.10 It is a schematic diagram of the three-dimensional structure of another integrated circuit provided by the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] With the development of integrated circuits, the scale of chips is getting larger and larger, and the speed of chip development has entered the post-Moore era. The 3D chip technology based on TSV (Through Silicon Via) has become one of the important directions for continuing to improve chip performance. 3D chip technology integrates multiple dies inside the chip, and the dies are interconnected through TSV communication to make the chip a whole, thereby achieving more powerful functions.

[0049] However, in existing applications, communication signals are transmitted layer by layer in the bare chips at each level. Figure 1As shown, the 3D chip includes six dies, namely die0 to die5. Each die is stacked and arranged, and the communication signal is transmitted layer by layer between the dies. Taking the communication signal transmission between die0 and die5 as an example, die0 first transmits the communication signal to die1 through TSV, and then die1 transmits the communication signal to die2, and so on, until it is transmitted to die5. This process requires the setting of 5 TSV channels. Correspondingly, the communication between other dies adopts this TSV setting method. It can be understood that this transmission method causes that when any die is abnormal or the operating temperature is too high and needs to be powered off and exited, all the dies downstream of the die in the signal transmission direction will not be able to continue to operate, and even affect the normal operation of the chip as a whole, and the chip reliability and robustness are poor.

[0050] To solve the above problems, the present application provides an integrated circuit, which, in the event that any first die or second die is abnormal, can directly cross the abnormal die and communicate with another die separated from the abnormal die, thereby ensuring normal communication between the remaining die when the abnormal die is removed, and all the die downstream of the abnormal die in the signal transmission direction can continue to operate, effectively improving the reliability and robustness of the chip.

[0051] Specifically, the integrated circuit provided by the present application includes at least one first die, a second die and a third die, each of which is stacked in the vertical direction, and the second die is located at the second top layer of each of the stacked dies, and the third die is located at the top layer of each of the stacked dies. In the integrated circuit provided by the present application, the connection relationship between the dies can be seen in Figure 2 as well as Figure 3 shown.

[0052] exist Figure 2 The integrated circuit provided in the embodiment shown includes a first die die0, a second die die1 and a third die die2. Figure 3 The integrated circuit provided in the illustrated embodiment includes a third die die5, a second die die4 and four first die, namely die0 to die3.

[0053] Combination Figure 2 as well as Figure 3 As shown, in the integrated circuit provided by the present application, each first die, second die and third die are cascaded in sequence through a first interconnection path (indicated by dotted arrows in the figure), and on this basis, any first die is also connected to another die separated by one die through a second interconnection path (indicated by a realization arrow in the figure).

[0054] by Figure 3Taking the integrated circuit shown as an example, die0, die1, die2, die3, die4 and die5 are cascaded in sequence through the first interconnection path indicated by the dotted arrow, and die0 is also connected to another die (i.e., die2) separated by one die (i.e., die1) through the second interconnection path. Correspondingly, die1 is also connected to another die (i.e., die3) separated by one die (i.e., die2) through the second interconnection path, and so on. Finally, die3 is connected to die5 through the second interconnection path.

[0055] When all the bare chips in the integrated circuit are in normal operation, each bare chip transmits communication signals in turn through the first interconnection path. When any of the first bare chip or the second bare chip is abnormal, such as operating failure, downtime, or the need to be powered off to reduce the operating temperature, the second interconnection path can be used to directly cross the abnormal bare chip and communicate with another bare chip separated from the abnormal bare chip, thereby ensuring the normal transmission of the communication signal.

[0056] Combination Figure 2 As shown, under normal circumstances, die0, die1 and die2 communicate in cascade sequence. When die1 abnormally exits operation, die0 is directly connected to die2 through the second interconnection path, so that the communication signal can be directly transmitted to die2 across die1, thereby ensuring that the communication process is not affected.

[0057] It should be noted that, compared with the integrated circuit including the same number (3) of bare chips in the prior art, Figure 2 The number of interconnection paths required for connecting the dies in the integrated circuit provided by the embodiment shown is the same as that in the prior art. In the prior art, when die1 is abnormal, the communication between the dies in the entire integrated circuit will be completely interrupted. Figure 2 In the integrated circuit provided by the illustrated embodiment, die0 can bypass die1 and directly communicate with die2, and the communication process is not affected by the abnormal bare chip die1.

[0058] Further, combined with Figure 3 As shown, under normal circumstances, die0 to die5 communicate in cascade order, and the communication signal is transmitted layer by layer through the first interconnection path shown by the dotted line. In the case that die1 abnormally exits operation, die0 is directly connected to die2 through the second interconnection path, so that the communication signal can be directly transmitted to die2 across die1, thereby ensuring that all the dies downstream of the abnormal die in the signal transmission direction can continue to communicate normally. Correspondingly, when any of the dies from die0 to die4 is abnormal, the communication signal transmission can be realized by referring to the above process, which will not be repeated here one by one.

[0059] Furthermore, by comparing Figure 1The prior art provides an integrated circuit, and Figure 3 As shown in the integrated circuit provided by the present application, it can be seen that the number of interconnection paths between bare chips in the integrated circuit provided by the present application can be significantly reduced, which is of great significance for reducing the overall cost of the integrated circuit.

[0060] To summarize, the integrated circuit provided by the present application can directly cross the abnormal die and communicate with another die separated from the abnormal die when any of the first die or the second die is abnormal, thereby ensuring normal communication between the remaining die when the abnormal die is removed, and all the die located downstream of the abnormal die in the signal transmission direction can continue to operate, effectively improving the reliability and robustness of the chip.

[0061] Furthermore, in the case of including two or more first bare chips, the number of interconnection channels required for interconnection between bare chips can be effectively reduced, which helps to reduce the overall cost and design difficulty of the integrated circuit.

[0062] Based on the above content, it can be seen that the connection method between the first bare chip and other bare chips is different from the connection method between the second bare chip and other bare chips. In order to realize the above integrated circuit architecture, the present application configures a first communication module in the first bare chip, and correspondingly, configures a second communication module in the second bare chip.

[0063] Specifically, the first communication module includes an input end, a first output end and a second output end, wherein the input end of the first communication module is used to receive a communication signal that needs to be transmitted between the bare chips, the first output end of the first communication module is cascaded with the adjacent bare chips, and the second output end of the first communication module is used to connect to another bare chip that is separated by one bare chip. Figure 3 In the example shown, the first output end of the first communication module set in die0 is used as a first interconnection path, connected to the input end of the first communication module configured in die1. Correspondingly, the second output end of the first communication module set in die0 is used as a second interconnection path, connected to the input end of the first communication module configured in die2. The remaining first bare chips are connected to other bare chips in the same way, which will not be repeated here one by one.

[0064] The first communication module responds to the selection signal and provides the communication signal to the first output terminal or the second output terminal. In practical applications, the selection signal can be subdivided into a first selection signal and a second selection signal, wherein the first selection signal is generated when the bare chip connected to the first output terminal of the first communication module is in a running state, and correspondingly, the second selection signal is generated when the bare chip connected to the first output terminal of the first communication module is in a power-off state, based on which, the first communication module responds to the first selection signal and provides the communication signal to the first output terminal, so that the first bare chip transmits the communication signal through the first interconnection path, and correspondingly, the first communication module responds to the second selection signal and provides the communication signal to the second output terminal, that is, transmits the communication signal through the second interconnection path.

[0065] In an optional implementation, the integrated circuit provided by the present application is further provided with a controller, which is respectively connected to the first communication modules in each first bare chip, and provides the first selection signal or the second selection signal to the first communication module in each first bare chip according to the operation status of each bare chip. It should be noted that the controller described in this embodiment can be a controller that is separately provided in the integrated circuit and is specifically used to control the selection state of the first communication module, or it can be a functional unit existing on any bare chip in the integrated circuit, such as a system controller, etc., which will not be described in detail here one by one, and it also belongs to the scope of protection of this application without exceeding the core idea of ​​this application.

[0066] Furthermore, the present application provides an optional implementation of a first communication module, Figure 4 As shown, the first communication module provided in this embodiment includes a gating module, a first TSV and a second TSV, wherein one end of the first TSV serves as the first output end of the first communication module, and is used to connect adjacent bare chips, and the other end of the first TSV is connected to the first gating output end of the gating module, and the first TSV serves as the aforementioned first interconnection path. Correspondingly, one end of the second TSV serves as the second output end of the first communication module, and is used to connect another bare chip separated by one bare chip, and the other end of the second TSV is connected to the second gating output end of the gating module.

[0067] The gating module further includes a gating input terminal In and a control terminal Ctrl, wherein the gating input terminal In is used as the input terminal of the first communication module for receiving a communication signal, and the control terminal Ctrl of the gating module is used to receive the aforementioned gating signals, i.e., the first gating signal and the second gating signal. The gating module responds to the first gating signal, connects the gating input terminal and the first gating output terminal, thereby transmitting the communication signal to the first output terminal of the first communication module, i.e., to the adjacent bare chip, and the gating module responds to the second gating signal, connects the gating input terminal and the second gating output terminal, thereby transmitting the communication signal to the second output terminal of the first communication module, i.e., to the next bare chip separated by one bare chip. As for the specific implementation of the gating function of the gating module, reference can be made to the relevant technology, which will not be described in detail here.

[0068] Combination Figure 2 as well as Figure 3 As shown, in the signal transmission direction, the second die only needs to transmit the communication signal to the adjacent third die, that is, for the second die, there is no other die separated by one die, therefore, the second communication module configured in the second die is slightly different from the aforementioned first communication module, as an optional implementation, the second communication module includes an input end and an output end, the input end of the second communication module is used to receive the communication signal of the first die adjacent to the second die, and the output end of the second communication module is connected to the third die, and is used to provide the communication signal to the third die. It can be understood that for the third die, the communication signal obtained may come from the second die, or from the first die adjacent to the second die.

[0069] In an optional embodiment, the second communication module can also be provided with a control terminal for receiving a control signal. Unlike the aforementioned selection signal used to select different interconnection paths, the control signal obtained by the second communication module is mainly used to control the connection state between the input terminal and the output terminal of the second communication module. Referring to the configuration of the aforementioned selection signal, the control signal described in this embodiment includes a first control signal and a second control signal. The second communication module responds to the first control signal to connect the input terminal and the output terminal and provide a communication signal to the third bare chip. Correspondingly, the second communication module responds to the second control signal to disconnect the input terminal and the output terminal and stop providing a communication signal to the third bare chip. Further, as an optional embodiment, the control signal corresponding to the second communication module can also be provided by the aforementioned controller.

[0070] In another optional implementation, for the first first die in each first die sequentially cascaded in the integrated circuit, Figure 2 as well as Figure 3Taking the illustrated embodiment as an example, i.e., die0 shown in the figure, a signal generation module may also be configured in the first first bare chip, and the signal generation module is connected to the input end of the first communication module in the first first bare chip, and provides a communication signal to the first communication module, and then transmits the communication signal according to the aforementioned integrated circuit architecture. In practical applications, the communication signals mentioned in this application may be global signals such as clock signals, interrupt signals, and reset signals. Of course, they may also be other signals that need to be transmitted between different bare chips, which will not be described in detail here. By integrating the signal generation module in the first first bare chip, it is possible to provide a communication signal at the upstream of the signal transmission path, which can ensure the smoothness and efficiency of the signal transmission path within the entire integrated circuit.

[0071] In summary, the integrated circuit provided by the present embodiment configures a first communication module in each first bare chip, and realizes connection between different first bare chips and adjacent bare chips and another bare chip separated by one bare chip through the first communication module, thereby constructing the aforementioned first interconnection path and second interconnection path. In the case that any first bare chip or second bare chip is abnormal, the first interconnection path can be disconnected to directly cross the abnormal bare chip, and at the same time, the second interconnection path can be connected to communicate with another bare chip separated by the abnormal bare chip, so that when the abnormal bare chip is removed, normal communication between the remaining bare chips is ensured, and all bare chips located downstream of the abnormal bare chip in the signal transmission direction can continue to operate, effectively improving the reliability and robustness of the chip.

[0072] Furthermore, when the first output terminal and the second output terminal of the first communication module are implemented based on TSV, in the integrated circuit provided by the present application, any first die only needs to be configured with two TSVs, and the second die only needs to be configured with one TSV. Especially when the integrated circuit includes two or more first dies, compared with the prior art, the present application can effectively reduce the number of TSV settings. Figure 5 As shown, as the number of layers of vertically stacked dies inside the integrated circuit increases, the number of TSVs required by the prior art shows a clear increasing trend, while the application provides an integrated circuit, and the growth of TSV usage is obviously slower than that of the prior art, that is, the number of TSVs required is significantly less. It can be understood that the reduction in the number of TSVs inside the integrated circuit can not only reduce the overall cost of the integrated circuit, but more importantly, the reduction in the number of TSVs and the increase in the distance between TSVs can reduce the capacitance of the coupling capacitor, thereby effectively reducing the impact of signal crosstalk between TSVs, and is conducive to timing optimization during communication signal transmission. The clock signal delay between modules or components that are interconnected between adjacent dies is minimized, which helps to improve the reliability and stability of communication signal transmission.

[0073] Combine the following Figure 6 and Figure 7, the communication signal transmission process of the integrated circuit provided in the present application when any first bare chip is powered off and operated is described in detail.

[0074] Combination Figure 6 As shown, the integrated circuit includes 6 bare chips, namely die0 to die5, first bare chips die0 to die3, each of which is provided with a first communication module, the control end of the selection module in each first communication module is used to receive the selection signal, and the input end In of the selection module in the first communication module in die0 receives the communication signal. The connection relationship between the remaining bare chips can refer to the aforementioned content and will not be repeated here.

[0075] Assume that die2 needs to stop running because of the high operating temperature. In this case, the control terminal Ctrl2 of the gating module of the first communication module in die2 receives the second gating signal, and in response to the second gating signal, connects the gating input terminal and the second gating output terminal, and transmits the communication signal of die1 to the input terminal of the first communication module in die3 through the second interconnection path, that is, the second TSV in the first communication module. In this way, the communication signal of die1 can be directly transmitted to die3 and other bare chips subsequent to die3, bypassing die2 that has stopped running for some reason. The transmission path of the communication signal in the integrated circuit is Figure 6 As shown by the dotted line, it can be seen that the entire integrated circuit can still operate normally, and the exit of die2 does not affect the operation of the entire integrated circuit.

[0076] For further information, see Figure 7 As shown, in Figure 7 In the illustrated embodiment, a signal generation module is provided in the first first die die0 in the integrated circuit, and the signal generation module is connected to the input end of the first communication module in the first die to provide communication signals for each related die. Figure 7 In the illustrated embodiment, the gating module in the first communication module is not shown, only the corresponding first TSV and second TSV are shown, and the transmission path of the communication signal is also shown with a dotted line. It should also be noted that in actual applications, the gating module in the first communication module can be connected to the first TSV and the second TSV through the on-chip network of the corresponding bare die. Of course, it can also be connected in other ways. Any way that can realize the function of the aforementioned first communication module is optional, and it also belongs to the scope of protection of this application without exceeding the core idea of ​​this application.

[0077] As mentioned above, increasing the distance between TSVs can effectively reduce the impact of signal crosstalk during signal transmission. Based on this, in order to further increase the distance between TSVs, the integrated circuit provided in the present application places the TSVs of each bare chip at staggered intervals to maximize the distance between the TSVs that actually transmit communication signals.

[0078] Combination Figure 8 As shown, when each die is operating normally (which is also the application scenario with the highest probability in the actual application of integrated circuits), the communication signal is transmitted through the first interconnection path, and the first TSV in each first die and the TSV in the second die are used to actually transmit the communication signal. In order to maximize the distance between the first TSVs of different dies, Figure 8 The example shown rotates the die in the even-numbered layers by 180° along the central axis in the vertical direction, and for any first die, the first TSV and the second TSV on the first die are arranged on different sides of the first die. Based on this, after the first die in the even-numbered layers is rotated by 180° along the central axis in the vertical direction (shown as R180° in the figure), the first TSV in the connected die for transmitting communication signals is located on both sides, effectively increasing the distance between the two and minimizing the impact of signal crosstalk.

[0079] It can be understood that when any of the first die or the second die exits operation, the second TSV continues to transmit the communication signal. In this case, only a portion of the TSVs on the signal transmission path are close, and the impact of signal crosstalk has little effect on the overall signal transmission quality. Compared with the existing technology, the stability and reliability of signal transmission are still significantly improved.

[0080] Further, in Figure 8 In the example shown, in order to more clearly show the positional relationship between the dies on different layers, multiple functional units for implementing preset functions contained in each die are also shown. In actual applications, these functional units can be related functional units required to constitute the die, such as processor cores, system controllers, and peripheral controllers. Combined with the arrangement of the functional units on each die, it can be seen that the first die on the even layer is rotated 180°.

[0081] It should be noted that, based on the above content, the overall layout of the second die and the third die, especially the layout of TSV, is different from that of the first die. For the second die, its own TSV can be arranged based on the TSV layout of the adjacent first die, with the layout principle of maximizing the spacing between adjacent TSVs. For the third die, reference can be made to Figure 8 The arrangement shown is rotated 180°, but it can, of course, not be rotated.

[0082] Combination Fig. 9As shown, the first TSV of die0 is arranged on the front side and the second TSV is arranged on the back side. Correspondingly, after rotating 180°, the first TSV of die0 is arranged on the back side and the second TSV is arranged on the front side. With this arrangement, when die0 and die1 are vertically stacked, the first TSV used to transmit communication signals will be located on both sides of the integrated circuit, and the distance between the two will be enlarged as much as possible to fully reduce the influence of signal crosstalk on communication signal transmission.

[0083] It is understandable that before die1 is rotated 180°, the structural layout of die0 and die1 is exactly the same. Especially when the two implement the same function, only one first die needs to be designed during the design process to achieve the reuse of the first die, thereby saving a lot of human resources and time costs, which is of great significance for improving the overall design efficiency of the integrated circuit. Furthermore, in the integrated circuit provided by the present application, each die corresponds to an independent and complete function, and the timing detection can be completed separately in each die, and there is no need to perform timing detection between the dies, which helps to improve the overall design efficiency of the integrated circuit.

[0084] Combination Fig.10 As shown, in another optional embodiment, for any first die, the first TSV and the second TSV are arranged on the same side of the first die. Referring to the above content, the second die can also arrange its own TSV and the TSV of the adjacent first die on the same side, thereby obtaining Fig.10 The settings shown here have an effect. Combined with Fig.10 As shown in the figure, the TSVs of adjacent dies are also arranged in an alternating manner so that the arrangement positions of the TSVs of the dies will not conflict.

[0085] It should be noted that in Fig.10 In the illustrated embodiment, the TSV layout of the first die in the odd-numbered layers is consistent, and the same die design can be reused. Correspondingly, the TSV layout of the first die in the even-numbered layers is consistent, and the same die design can be reused. When packaging the integrated circuit, each TSV can also be packaged on the same side.

[0086] Furthermore, the present application also provides a system on chip, including the integrated circuit provided by any of the above embodiments of the present application.

[0087] The present application also provides an electronic device, comprising the system on chip provided by the above embodiment.

[0088] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0089] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0090] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0091] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0092] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0093] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. An integrated circuit, characterized in that: include: at least one first die, one second die and one third die, wherein: The first die, the second die and the third die are stacked in sequence in a vertical direction, and the second die is located at the second top layer, and the third die is located at the top layer; The first die, the second die and the third die are cascaded in sequence; Any of the first dies is also connected to another die that is spaced one die apart.

2. The integrated circuit according to claim 1, characterized in that The first bare die includes a first communication module, wherein The input end of the first communication module is used to receive a communication signal; The first output end of the first communication module is used for cascading with an adjacent die, and the second output end of the first communication module is used for connecting with another die separated by one die; The first communication module provides a communication signal to the first output terminal or the second output terminal in response to a selection signal.

3. The integrated circuit according to claim 2, characterized in that The strobe signal includes a first strobe signal and a second strobe signal, wherein: The first communication module provides a communication signal to the first output terminal in response to the first selection signal, wherein the first selection signal is generated when the die connected to the first output terminal is in an operating state; The first communication module provides a communication signal to the second output terminal in response to the second selection signal, and the second selection signal is generated when the die connected to the first output terminal is in a power-off state.

4. The integrated circuit according to claim 2, characterized in that For a first first bare chip among the first bare chips cascaded in sequence, the first first bare chip further includes a signal generating module; The signal generating module is connected to the input end of the first communication module of the first first bare chip; The signal generating module is used for providing a communication signal.

5. The integrated circuit according to claim 2, characterized in that: The first communication module includes a gating module, a first through silicon via TSV and a second TSV, wherein: One end of the first TSV serves as the first output end, and the other end of the first TSV is connected to the first gating output end of the gating module; One end of the second TSV serves as the second output end, and the other end of the second TSV is connected to the second selection output end of the selection module; The gating input terminal of the gating module is used to receive a communication signal; The control end of the gating module is used to receive the gating signal; The gating module connects the gating input terminal and the first gating output terminal, or connects the gating input terminal and the second gating output terminal in response to the gating signal.

6. The integrated circuit according to claim 5, characterized in that For any of the first dies, the first TSV and the second TSV are disposed on different sides of the first die.

7. The integrated circuit according to claim 6, characterized in that The first dies in the even-numbered layers among the first dies are rotated 180° along the central axis in the vertical direction.

8. The integrated circuit according to claim 5, characterized in that For any of the first dies, the first TSV and the second TSV are disposed on a same side of the first die.

9. The integrated circuit according to claim 2, characterized in that: Also includes: controller, where The controller is respectively connected to the first communication modules of the first bare chips to provide the selection signal to the first communication modules.

10. The integrated circuit according to any one of claims 1 to 9, characterized in that: The second bare chip includes a second communication module, wherein The input end of the second communication module is used to receive a communication signal of a first die adjacent to the second die; An output terminal of the second communication module is connected to the third bare chip.

11. A system on chip, characterized in that: Comprising an integrated circuit as claimed in any one of claims 1 to 10.

12. An electronic device, characterized in that: Comprising the system on chip as claimed in claim 11.

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