Low-power-consumption low-voltage-drop one-way conduction circuit and circuit power consumption optimization method

Abstract

The invention provides a low-power-consumption low-voltage-drop one-way conduction circuit and a circuit power consumption optimization method, and the circuit comprises a power tube array, an ultra-low-power-consumption current source, an ultra-low-power-consumption error amplifier, and an ultra-low-power-consumption comparator. The power tube array is used for forming a conduction circuit in a conduction state; the ultra-low power consumption current source is used for providing bias current for the ultra-low power consumption error amplifier and the ultra-low power consumption comparator; the ultra-low power consumption error amplifier is used for adjusting the grid voltage of the power tube array so as to adjust the voltage drop value between the circuit input and the circuit output of the conduction circuit; the ultra-low power consumption comparator is used for monitoring the voltage drop value and adjusting the conduction state of the power tube array based on the voltage drop value and a target threshold value. By the adoption of the circuit, one-way conduction of the circuit is achieved, and meanwhile power loss is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of battery power supply, and in particular to a low-power, low-voltage-drop unidirectional conduction circuit and a circuit power consumption optimization method. Background Art

[0002] In the fields of smart meters, building automation, main batteries and backup batteries, there is a combination of battery power supply and external power supply. Under normal circumstances, circuit designers will use multiple diode cathode short-circuited methods to power the circuit load. In this way, the load can be powered by a single circuit, and the various power supply branches do not affect each other. At the same time, when the load has abnormal fluctuations, it will not affect the power supply in turn, thus forming a unidirectional power supply solution.

[0003] As the power supply voltage decreases, the power loss of the diode, which is an indispensable link in the path, becomes increasingly important. For example, if a 3.3V power supply is connected to a low voltage drop (0.4V) Schottky diode, when the load current flows through the diode, it can be estimated that at least 10% of the loss is eaten by the diode. Under lower power supply voltage input, or when ordinary diodes are used in the above scheme, the power loss in the path will be more significant. Especially when the battery is used as the power supply, due to the limited amount of stored charge, the circuit load must be low power or even ultra-low power, otherwise the overall working time of the system will be greatly reduced. If there is a device with extremely low conduction voltage drop and power consumption on the path, and the function is the same as the diode and can be turned on in one direction, it will be beneficial to promote the multi-way power supply scheme under low voltage input power supply, especially in the field of multi-way power supply involving batteries.

[0004] Under the existing technology, there are two possible solutions. The first is to use a low-voltage drop diode, which can reduce the power loss on the diode as much as possible. The second is to use the general power supply side ideal diode technology, but the current power supply side ideal diode technology is mainly achieved by charge pump boost. For the first method, due to the device process factors, the forward voltage drop of the diode cannot be too low. The forward voltage drop (Vford) of the Schottky diode of about 300mV made by special process is already difficult to further reduce; in the second method, the charge pump boost will use oscillator and other technologies. Whether it is a charge pump or an oscillator, it is impossible to achieve extremely low current consumption (Iwork). Therefore, under the above two methods, whether it is the first method or the second method, it is difficult to reduce the power loss of this link. Therefore, how to reduce power loss while achieving unidirectional conduction of the circuit has become an urgent problem to be solved. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a low-power, low-voltage-drop unidirectional conduction circuit and a circuit power consumption optimization method, so as to achieve unidirectional conduction of the circuit and reduce power loss at the same time.

[0006] In a first aspect, an embodiment of the present application provides a low-power, low-voltage-drop unidirectional conduction circuit, the circuit comprising a power tube array 1, an ultra-low-power current source 2, an ultra-low-power error amplifier 3, and an ultra-low-power comparator 4;

[0007] The power tube array 1 is used to form a conducting circuit in a conducting state;

[0008] The ultra-low power consumption current source 2 is used to provide bias current for the ultra-low power consumption error amplifier 3 and the ultra-low power consumption comparator 4;

[0009] The ultra-low power consumption error amplifier 3 is used to adjust the gate voltage of the power tube array 1 to adjust the voltage drop value between the circuit input and the circuit output of the conduction circuit;

[0010] The ultra-low power consumption comparator 4 is used to monitor the voltage drop value and adjust the conduction state of the power tube array 1 based on the voltage drop value and the target threshold.

[0011] Optionally, adjusting the conduction state of the power tube array 1 based on the voltage drop value and the target threshold value includes:

[0012] determining whether the pressure drop value exceeds the target threshold;

[0013] If the voltage drop value does not exceed the target threshold, the output control signal controls the power tube array 1 to be turned off to disconnect the conduction circuit.

[0014] Optionally, after determining whether the voltage drop value exceeds the target threshold, if the voltage drop value exceeds the target threshold, the power tube array 1 is kept in a conducting state to form the conducting circuit.

[0015] Optionally, the current value of the bias current is 10nA, and the target threshold is -30mV.

[0016] Optionally, the power tube array 1 includes a plurality of PMOS tubes, and the PMOS tubes are connected in parallel.

[0017] Optionally, the ultra-low power consumption current source 2 includes a first PMOS tube 201, a second PMOS tube 202, a third PMOS tube 203, a fourth PMOS tube 204, a first NMOS tube 205, a second NMOS tube 206 and a first resistor 207;

[0018] The source of the first PMOS tube 201, the source of the second PMOS tube 202, the source of the third PMOS tube 203, and the source of the fourth PMOS tube 204 are respectively connected to the circuit input of the conduction circuit and the source of the power tube array 1; the gate of the first PMOS tube 201, the gate of the second PMOS tube 202, the gate of the third PMOS tube 203, and the gate of the fourth PMOS tube 204 are connected to each other; the drain of the first PMOS tube 201 is respectively connected to the drain of the first NMOS tube 205, the drain of the first NMOS The gate of the first NMOS tube 205 is connected; the gate of the first NMOS tube 205 is connected to the gate of the second NMOS tube 206; the drain of the second NMOS tube 206 is connected to the drain of the fourth PMOS tube 204 and the gate of the fourth PMOS tube 204 respectively; the source of the first NMOS tube 205 is grounded; the source of the second NMOS tube 206 is grounded through the first resistor 207; the drain of the second PMOS tube 202 is connected to the ultra-low power consumption error amplifier 3; the drain of the third PMOS tube 203 is connected to the ultra-low power consumption comparator 4.

[0019] Optionally, the bias current I bias for:

[0020]

[0021] Among them, μ n is the electron mobility of the NMOS tube, C ox is the gate capacitance per unit area of ​​the NMOS tube, R is the resistance value of the first resistor 207 , and K is the ratio of the number of the second NMOS tubes 206 to the number of the first NMOS tubes 205 .

[0022] Optionally, the ultra-low power consumption error amplifier 3 includes a fifth PMOS tube 301, a sixth PMOS tube 302, a seventh PMOS tube 303, a third NMOS tube 304, a fourth NMOS tube 305, a fifth NMOS tube 306, a sixth NMOS tube 307, a seventh NMOS tube 308, a first voltage source 309 and a first capacitor 310;

[0023] The source of the fifth PMOS tube 301, the source of the sixth PMOS tube 302, and the source of the seventh PMOS tube 303 are respectively connected to the circuit input of the conduction circuit; the gate of the fifth PMOS tube 301 is respectively connected to the gate of the sixth PMOS tube 302 and the drain of the sixth PMOS tube 302; the drain of the fifth PMOS tube 301 is respectively connected to the drain of the third NMOS tube 304, the first end of the first capacitor 310, and the gate of the seventh PMOS tube 303; the drain of the seventh PMOS tube 303 is respectively connected to the second end of the first capacitor 310 and the gate of the power tube array 1; the drain of the sixth PMOS tube 302 is connected to the drain of the fourth NMOS tube 305; the source of the third NMOS tube 304 is connected to the drain of the fourth NMOS tube 305; the drain ... They are respectively connected to the source of the fourth NMOS tube 305 and the drain of the sixth NMOS tube 307; the gate of the third NMOS tube 304 is connected to the positive electrode of the first voltage source 309, and the negative electrode of the first voltage source 309 is connected to the circuit output of the conduction circuit; the drain of the fifth NMOS tube 306 is respectively connected to the ultra-low power consumption current source 2 and the gate of the fifth NMOS tube 306; the gate of the fifth NMOS tube 306, the gate of the sixth NMOS tube 307, and the gate of the seventh NMOS tube 308 are connected to each other; the drain of the seventh NMOS tube 308 is connected to the circuit output of the conduction circuit; the source of the fifth NMOS tube 306, the source of the sixth NMOS tube 307, and the source of the seventh NMOS tube 308 are all grounded.

[0024] Optionally, the ultra-low power comparator 4 includes an eighth PMOS tube 401, a ninth PMOS tube 402, a tenth PMOS tube 403, an eleventh PMOS tube 404, a twelfth PMOS tube 405, a thirteenth PMOS tube 406, a fourteenth PMOS tube 407, an eighth NMOS tube 408, a ninth NMOS tube 409, a tenth NMOS tube 410, an eleventh NMOS tube 411, a twelfth NMOS tube 412, a thirteenth NMOS tube 413, a fourteenth NMOS tube 414, a fifteenth NMOS tube 415, a sixteenth NMOS tube 416, and a second voltage source 417;

[0025] The source of the eighth PMOS tube 401, the source of the ninth PMOS tube 402, the source of the tenth PMOS tube 403, the source of the eleventh PMOS tube 404, and the source of the fourteenth PMOS tube 407 are respectively connected to the circuit input of the conduction circuit; the gate of the eighth PMOS tube 401, the gate of the ninth PMOS tube 402, the gate of the tenth PMOS tube 403, and the gate of the eleventh PMOS tube 404 are connected to each other; the drain of the eighth PMOS tube 401 is respectively connected to the gate of the eighth PMOS tube 401 and the drain of the eleventh NMOS tube 411; the drain of the ninth PMOS tube 402 is respectively connected to the gate of the twelfth PMOS tube 411; The source of the eighth NMOS tube 408 is connected to the source of the twelfth PMOS tube 405, the gate of the thirteenth PMOS tube 406, the source of the ninth NMOS tube 409, and the drain of the twelfth NMOS tube 412; the drain of the ninth NMOS tube 409 is connected to the drain of the tenth PMOS tube 403 and the source of the thirteenth PMOS tube 406; the gate of the ninth NMOS tube 409 is connected to the positive electrode of the second voltage source 417, and the negative electrode of the second voltage source 417 is connected to the circuit input of the conduction circuit; the source of the eighth NMOS tube 408 is respectively connected to the gate of the twelfth PMOS tube 405, the gate of the thirteenth PMOS tube 406, the source of the ninth NMOS tube 409, and the drain of the twelfth NMOS tube 412; the drain of the ninth NMOS tube 409 is respectively connected to the drain of the tenth PMOS tube 403 and the source of the thirteenth PMOS tube 406; the gate of the ninth NMOS tube 409 is connected to the gate of the conduction circuit. The output connection of the circuit; the gate of the eleventh NMOS tube 411, the gate of the tenth NMOS tube 410, the gate of the twelfth NMOS tube 412, and the gate of the sixteenth NMOS tube 416 are connected to each other; the drain of the tenth NMOS tube 410 is respectively connected to the gate of the tenth NMOS tube 410 and the ultra-low power consumption current source 2; the drain of the twelfth PMOS tube 405 is respectively connected to the drain of the thirteenth NMOS tube 413 and the gate of the fifteenth NMOS tube 415; the drain of the thirteenth PMOS tube 406 is respectively connected to the drain of the fourteenth NMOS tube 414 and the gate of the fourteenth NMOS tube 414; the thirteenth NMOS tube 413 is respectively connected to the drain of the thirteenth NMOS tube 414 and the gate of the thirteenth NMOS tube 414; The gate of the power transistor array 1 is connected to the gate of the fourteenth NMOS tube 414; the drain of the eleventh PMOS tube 404 is respectively connected to the gate of the fourteenth PMOS tube 407 and the drain of the fifteenth NMOS tube 415; the drain of the fourteenth PMOS tube 407 is respectively connected to the gate of the power transistor array 1 and the drain of the sixteenth NMOS tube 416; the source of the tenth NMOS tube 410, the source of the eleventh NMOS tube 411, the source of the twelfth NMOS tube 412, the source of the thirteenth NMOS tube 413, the source of the fourteenth NMOS tube 414, the source of the fifteenth NMOS tube 415, and the source of the sixteenth NMOS tube 416 are all grounded.

[0026] In a second aspect, an embodiment of the present application provides a circuit power consumption optimization method, which is applied to a low-power unidirectional conduction circuit, wherein the circuit includes a power tube array, an ultra-low power current source, an ultra-low power error amplifier, and an ultra-low power comparator, and the method includes:

[0027] The power tube array forms a conducting circuit in a conducting state;

[0028] The ultra-low power consumption current source provides bias current for the ultra-low power consumption error amplifier and the ultra-low power consumption comparator;

[0029] The ultra-low power consumption error amplifier adjusts the gate voltage of the power tube array to adjust the voltage drop value between the circuit input and the circuit output of the conduction circuit;

[0030] The ultra-low power consumption comparator monitors the voltage drop value, and adjusts the conduction state of the power tube array based on the voltage drop value and a target threshold.

[0031] The technical solution provided by this application includes but is not limited to the following beneficial effects:

[0032] The present application uses an ultra-low power error amplifier to perform negative feedback adjustment on the power tube array to ensure that the forward voltage drop is maintained at a very low level, thereby reducing the power loss in the circuit. At the same time, an ultra-low power comparator is used to detect the input and output voltages to ensure that the current flows in a unidirectional direction from the input to the output. Once the voltage is reversed, the comparator will quickly shut down the power tube array to ensure unidirectional conduction of the circuit, thereby achieving unidirectional conduction of the circuit with low power loss.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 It shows a structural schematic diagram of a low-power, low-voltage-drop unidirectional conduction circuit provided by the first embodiment of the present invention;

[0036] Figure 2 A schematic diagram of the structure of an ultra-low power consumption current source provided by the first embodiment of the present invention is shown;

[0037] Figure 3 A schematic diagram of the structure of an ultra-low power consumption error amplifier provided by the first embodiment of the present invention is shown;

[0038] Figure 4 A schematic diagram of the structure of an ultra-low power consumption comparator provided by the first embodiment of the present invention is shown;

[0039] Figure 5 A schematic diagram showing the structure of a differential pair asymmetry circuit provided by the first embodiment of the present invention;

[0040] Figure 6 A flow chart of a circuit power consumption optimization method provided by the second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0042] Embodiment 1

[0043] To facilitate understanding of this application, Figure 1 The contents described in the structural schematic diagram of a low-power, low-voltage-drop unidirectional conduction circuit provided by the first embodiment of the present invention are described in detail for the first embodiment of the present application.

[0044] See also Figure 1 As shown, Figure 1 The structure schematic diagram of a low-power, low-voltage-drop unidirectional conduction circuit provided in the first embodiment of the present invention is shown, wherein the circuit comprises a power tube array 1, an ultra-low-power current source 2, an ultra-low-power error amplifier 3 and an ultra-low-power comparator 4;

[0045] The power tube array 1 is used to form a conducting circuit in a conducting state.

[0046] Specifically, the power tube array is composed of a PMOS tube array, and the number of power PMOS tubes is designed according to the maximum load current value.

[0047] The ultra-low power consumption current source 2 is used to provide bias current for the ultra-low power consumption error amplifier 3 and the ultra-low power consumption comparator 4 .

[0048] Specifically, the ultra-low power current source provides a bias current I for the ultra-low power error amplifier 3. bias1 , provides bias current I for ultra-low power comparator 4 bias2 The ultra-low power current source is used to reduce the current value of the bias current as much as possible for the power consumption level of the entire circuit, so that the ultra-low power error amplifier and the ultra-low power comparator are in a suitable bias state, which is crucial to maintaining low power consumption and reliable operation of the entire circuit.

[0049] The ultra-low power consumption error amplifier 3 is used to adjust the gate voltage of the power tube array 1 to adjust the voltage drop value between the circuit input and the circuit output of the conduction circuit.

[0050] Specifically, when the load current changes, the ultra-low power error amplifier adjusts the state of the power tube array so that the circuit input (voltage value is recorded as V in ) and the circuit output (voltage value is recorded as V out ) between the voltage drop value ΔV (ΔV = V in -V out ) has been maintained at a very low level. In this application, ΔV≈30mV. As the load current increases, the output drive voltage of the ultra-low power error amplifier also reaches the maximum, and the power tube array is in a linear resistance state. If the load current increases further, the voltage drop value can be expressed as ΔV≈I load *R on To estimate, I load is the current value of the load current, R on is the resistance value of the channel on-resistance of the PMOS power tube array.

[0051] The ultra-low power consumption comparator 4 is used to monitor the voltage drop value and adjust the conduction state of the power tube array 1 based on the voltage drop value and the target threshold.

[0052] Specifically, an ultra-low power comparator is used to detect the input and output voltages to ensure that the current flows in one direction from the input V in Flow to output V out Once the voltage reverses, the ultra-low power comparator will quickly shut down the power PMOS in the power tube array to ensure the unidirectional conduction of the circuit.

[0053] In a feasible implementation, adjusting the conduction state of the power tube array 1 based on the voltage drop value and the target threshold value includes:

[0054] It is determined whether the voltage drop value exceeds the target threshold value; if the voltage drop value does not exceed the target threshold value, a control signal is output to control the power tube array 1 to be turned off to disconnect the conduction circuit.

[0055] Specifically, once the ultra-low power comparator detects that ΔV does not exceed the target threshold (the target threshold is -30mV in this application), that is, V in -V out <-30mV, that is, V out -V in >30mV, the output control signal will turn off the power PMOS tube in the power tube array, and the input and output are in an open circuit state.

[0056] In a feasible implementation, after determining whether the voltage drop value exceeds the target threshold, if the voltage drop value does not exceed the target threshold, the power tube array 1 is kept in a conducting state to form the conducting circuit.

[0057] Specifically, if the ΔV detected by the ultra-low power comparator exceeds the target threshold value all the time, the ultra-low power error amplifier will adjust and control the state of the power PMOS tube.

[0058] In a feasible implementation manner, the current value of the bias current is 10 nA, and the target threshold is -30 mV.

[0059] In a feasible implementation, the power tube array 1 includes a plurality of PMOS tubes, and the PMOS tubes are connected in parallel.

[0060] Specifically, the number of PMOS tubes is designed according to the maximum load current value, and is queried from a PMOS tube number comparison table.

[0061] In one possible embodiment, see Figure 2 As shown, Figure 2 The structure diagram of an ultra-low power consumption current source provided by the first embodiment of the present invention is shown, wherein the ultra-low power consumption current source 2 comprises a first PMOS tube 201, a second PMOS tube 202, a third PMOS tube 203, a fourth PMOS tube 204, a first NMOS tube 205, a second NMOS tube 206 and a first resistor 207;

[0062] The source of the first PMOS tube 201, the source of the second PMOS tube 202, the source of the third PMOS tube 203, and the source of the fourth PMOS tube 204 are respectively connected to the circuit input of the conduction circuit and the source of the power tube array 1; the gate of the first PMOS tube 201, the gate of the second PMOS tube 202, the gate of the third PMOS tube 203, and the gate of the fourth PMOS tube 204 are connected to each other; the drain of the first PMOS tube 201 is respectively connected to the drain of the first NMOS tube 205, the drain of the first NMOS The gate of the first NMOS tube 205 is connected; the gate of the first NMOS tube 205 is connected to the gate of the second NMOS tube 206; the drain of the second NMOS tube 206 is connected to the drain of the fourth PMOS tube 204 and the gate of the fourth PMOS tube 204 respectively; the source of the first NMOS tube 205 is grounded; the source of the second NMOS tube 206 is grounded through the first resistor 207; the drain of the second PMOS tube 202 is connected to the ultra-low power consumption error amplifier 3; the drain of the third PMOS tube 203 is connected to the ultra-low power consumption comparator 4.

[0063] Specifically, the topology of the ultra-low power consumption current source is realized by a general self-biased current source, including a current mirror structure composed of a P-type MOS, including a first PMOS tube 201 and a fourth PMOS tube 204, and the second PMOS tube 202 outputs I bias1 , the third PMOS tube 203 outputs I bias2 The current mirror structure composed of N-type MOS includes a first NMOS tube 205 and a second NMOS tube 206, wherein the size of the first NMOS tube 205 is W / L, and the size of the second NMOS tube 206 is (W / L)*K, wherein W is the transistor width of the NMOS tube, L is the channel length, and K is the number of transistors of the NMOS tube. Since the current value of the first NMOS tube 205 and the second NMOS tube 206 is the same, the driving voltage U gs There are differences.

[0064] In a feasible embodiment, the bias current I bias for:

[0065]

[0066] Among them, μ n is the electron mobility of the NMOS tube, C ox is the gate capacitance per unit area of ​​the NMOS tube, R is the resistance value of the first resistor 207 , and K is the ratio of the number of the second NMOS tubes 206 to the number of the first NMOS tubes 205 .

[0067] Specifically, it can be seen from the above expression that increasing the resistance value R of the first resistor 207 can significantly reduce the bias current I bias In this application, I bias Preferably 10nA.

[0068] In one possible embodiment, see Figure 3 As shown, Figure 3 The structure diagram of an ultra-low power consumption error amplifier provided in the first embodiment of the present invention is shown, wherein the ultra-low power consumption error amplifier 3 includes a fifth PMOS tube 301, a sixth PMOS tube 302, a seventh PMOS tube 303, a third NMOS tube 304, a fourth NMOS tube 305, a fifth NMOS tube 306, a sixth NMOS tube 307, a seventh NMOS tube 308, a first voltage source 309 and a first capacitor 310;

[0069] The source of the fifth PMOS tube 301, the source of the sixth PMOS tube 302, and the source of the seventh PMOS tube 303 are respectively connected to the circuit input of the conduction circuit; the gate of the fifth PMOS tube 301 is respectively connected to the gate of the sixth PMOS tube 302 and the drain of the sixth PMOS tube 302; the drain of the fifth PMOS tube 301 is respectively connected to the drain of the third NMOS tube 304, the first end of the first capacitor 310, and the gate of the seventh PMOS tube 303; the drain of the seventh PMOS tube 303 is respectively connected to the second end of the first capacitor 310 and the gate of the power tube array 1; the drain of the sixth PMOS tube 302 is connected to the drain of the fourth NMOS tube 305; the source of the third NMOS tube 304 is connected to the drain of the fourth NMOS tube 305; the drain ... They are respectively connected to the source of the fourth NMOS tube 305 and the drain of the sixth NMOS tube 307; the gate of the third NMOS tube 304 is connected to the positive electrode of the first voltage source 309, and the negative electrode of the first voltage source 309 is connected to the circuit output of the conduction circuit; the drain of the fifth NMOS tube 306 is respectively connected to the ultra-low power consumption current source 2 and the gate of the fifth NMOS tube 306; the gate of the fifth NMOS tube 306, the gate of the sixth NMOS tube 307, and the gate of the seventh NMOS tube 308 are connected to each other; the drain of the seventh NMOS tube 308 is connected to the circuit output of the conduction circuit; the source of the fifth NMOS tube 306, the source of the sixth NMOS tube 307, and the source of the seventh NMOS tube 308 are all grounded.

[0070] Specifically, the ultra-low power error amplifier is a classic two-stage amplifier structure, in which the receiving bias current I bias1The third NMOS tube 304 and the fourth NMOS tube 305 constitute the differential input stage of the amplifier, the fifth PMOS tube 301 and the sixth PMOS tube 302 constitute the current mirror load of the amplifier, the seventh PMOS tube 303 constitutes the second stage amplifier circuit, and the fifth NMOS tube 306, the sixth NMOS tube 307, and the seventh NMOS tube 308 are used as current bias. The differential input stage has a certain fixed offset ΔV on the side of the third NMOS tube 304 at the non-inverting input end. offset , this fixed offset can make the amplifier output gate voltage V gate Continuously adjust the gate of the power PMOS, V in With V out There is a ΔV offset The voltage drop is the forward voltage drop between the input and output. Considering the stability of the loop, we need to perform frequency compensation on the amplifier. The capacitor in the figure above can achieve the purpose of frequency compensation.

[0071] In one possible embodiment, see Figure 4 As shown, Figure 4 A schematic diagram of the structure of an ultra-low power consumption comparator provided in the first embodiment of the present invention is shown, wherein the ultra-low power consumption comparator 4 includes an eighth PMOS tube 401, a ninth PMOS tube 402, a tenth PMOS tube 403, an eleventh PMOS tube 404, a twelfth PMOS tube 405, a thirteenth PMOS tube 406, a fourteenth PMOS tube 407, an eighth NMOS tube 408, a ninth NMOS tube 409, a tenth NMOS tube 410, an eleventh NMOS tube 411, a twelfth NMOS tube 412, a thirteenth NMOS tube 413, a fourteenth NMOS tube 414, a fifteenth NMOS tube 415, a sixteenth NMOS tube 416, and a second voltage source 417;

[0072] The source of the eighth PMOS tube 401, the source of the ninth PMOS tube 402, the source of the tenth PMOS tube 403, the source of the eleventh PMOS tube 404, and the source of the fourteenth PMOS tube 407 are respectively connected to the circuit input of the conduction circuit; the gate of the eighth PMOS tube 401, the gate of the ninth PMOS tube 402, the gate of the tenth PMOS tube 403, and the gate of the eleventh PMOS tube 404 are connected to each other; the drain of the eighth PMOS tube 401 is respectively connected to the gate of the eighth PMOS tube 401 and the drain of the eleventh NMOS tube 411; the drain of the ninth PMOS tube 402 is respectively connected to the gate of the twelfth PMOS tube 411; The source of the eighth NMOS tube 408 is connected to the source of the twelfth PMOS tube 405, the gate of the thirteenth PMOS tube 406, the source of the ninth NMOS tube 409, and the drain of the twelfth NMOS tube 412; the drain of the ninth NMOS tube 409 is connected to the drain of the tenth PMOS tube 403 and the source of the thirteenth PMOS tube 406; the gate of the ninth NMOS tube 409 is connected to the positive electrode of the second voltage source 417, and the negative electrode of the second voltage source 417 is connected to the circuit input of the conduction circuit; the source of the eighth NMOS tube 408 is respectively connected to the gate of the twelfth PMOS tube 405, the gate of the thirteenth PMOS tube 406, the source of the ninth NMOS tube 409, and the drain of the twelfth NMOS tube 412; the drain of the ninth NMOS tube 409 is respectively connected to the drain of the tenth PMOS tube 403 and the source of the thirteenth PMOS tube 406; the gate of the ninth NMOS tube 409 is connected to the gate of the conduction circuit. The output connection of the circuit; the gate of the eleventh NMOS tube 411, the gate of the tenth NMOS tube 410, the gate of the twelfth NMOS tube 412, and the gate of the sixteenth NMOS tube 416 are connected to each other; the drain of the tenth NMOS tube 410 is respectively connected to the gate of the tenth NMOS tube 410 and the ultra-low power consumption current source 2; the drain of the twelfth PMOS tube 405 is respectively connected to the drain of the thirteenth NMOS tube 413 and the gate of the fifteenth NMOS tube 415; the drain of the thirteenth PMOS tube 406 is respectively connected to the drain of the fourteenth NMOS tube 414 and the gate of the fourteenth NMOS tube 414; the thirteenth NMOS tube 413 is respectively connected to the drain of the thirteenth NMOS tube 414 and the gate of the thirteenth NMOS tube 414; The gate of the power transistor array 1 is connected to the gate of the fourteenth NMOS tube 414; the drain of the eleventh PMOS tube 404 is respectively connected to the gate of the fourteenth PMOS tube 407 and the drain of the fifteenth NMOS tube 415; the drain of the fourteenth PMOS tube 407 is respectively connected to the gate of the power transistor array 1 and the drain of the sixteenth NMOS tube 416; the source of the tenth NMOS tube 410, the source of the eleventh NMOS tube 411, the source of the twelfth NMOS tube 412, the source of the thirteenth NMOS tube 413, the source of the fourteenth NMOS tube 414, the source of the fifteenth NMOS tube 415, and the source of the sixteenth NMOS tube 416 are all grounded.

[0073] Specifically, the ultra-low power comparator is composed of a classic folded common source and common gate + two-stage common source amplifier stage, wherein the receiving bias current I bias2 , the eighth NMOS tube 408 and the ninth NMOS tube 409 constitute the differential input stage of the comparator, the thirteenth NMOS tube 413 and the fourteenth NMOS tube 414 constitute the current mirror load of the amplifier, the fifteenth NMOS tube 415 and the fourteenth PMOS tube 407 constitute the second and third stage amplifier circuits, and the tenth NMOS tube 410, the eleventh NMOS tube 411, the twelfth NMOS tube 412 and the sixteenth NMOS tube 416 serve as current bias. The differential input stage has a certain fixed offset ΔV on the inverting input side of the eighth NMOS tube 408. offset , the fixed offset can make the comparator appear V out >V in During this period, there is a ΔV between the output and the input offset When the output V gate Pull it high quickly to turn off the power PMOS.

[0074] In the above circuit diagram, a voltage source Voffset with a specific direction is placed on the gate of one side of the MOS differential pair to indicate the asymmetry between the two ends of the differential pair. Figure 5 As shown, Figure 5 FIG. 1 shows a schematic diagram of a differential pair asymmetry circuit provided by an embodiment of the present invention, wherein I a is the current value of the current passing through the left branch of the asymmetric differential pair, I b is the current value of the current passing through the right branch of the asymmetric differential pair, I bias Indicates the current value of the bias current, V S is the potential at the junction of the asymmetric differential pair sources, ΔV offset is the offset voltage, W / L is the aspect ratio of the transistor, W is the transistor width of the NMOS tube, L is the channel length, V out Indicates the voltage value of the circuit output, V in It represents the voltage value of the circuit input, K is the number of transistors in the NMOS tube, and is any number greater than 1. The circuit after placing a voltage source in a specific direction is equivalent to setting up an NMOS tube containing K transistors.

[0075] according to Figure 5 The direction of the voltage source in the circuit on the left is expressed as:

[0076]

[0077] If: I a =I b , let: V in-V out =ΔV offset

[0078] The actual circuit implementation is based on Figure 5 The right side can also be expressed as:

[0079]

[0080] If: I a =I b ,but:

[0081]

[0082] From the above formula we can get:

[0083]

[0084] Among them, Δ drive is the driving voltage value of the asymmetric differential pair (the voltage difference between the gate and the source).

[0085] Through the above differential pair asymmetric design, a specific offset voltage ΔV can be constructed at the input end. offset , this voltage depends only on the differential pair ratio on both sides and the driving voltage, and has nothing to do with other factors. This voltage is equivalent to placing a voltage source at the input.

[0086] This application uses an ultra-low power error amplifier to perform negative feedback adjustment on the power PMOS to ensure that the forward voltage drop is maintained at a very low ΔV = V in -V out (about 30mV) level, using ultra-low power comparator to detect input and output voltage, ensuring that the current flows in one direction from the input V in Flow to output V out , once the voltage reverses V out -V in >30mV, the comparator will quickly shut down the power PMOS. In this application, an ultra-low power current source provides current bias for the above two important structures. Whether it is the current source part, the amplifier, or the comparator, the current bias of their single branches is biased in multiples of 10nA. The total power consumption of these three parts is designed to be around 200nA, that is to say: the power loss generated on the path can be reduced from the original mW to several hundred mW (current flowing through mA to A level under the diode voltage drop) to about 200nA*30mV=6nW, while continuing to maintain the diode's anti-reverse pressure and unidirectional conduction characteristics, which can greatly improve the performance of this link.

[0087] Embodiment 2

[0088] See also Figure 6 As shown, Figure 6 A flow chart of a circuit power consumption optimization method provided by the second embodiment of the present invention is shown, wherein the method is applied to a low-power unidirectional conduction circuit, the circuit includes a power tube array, an ultra-low power current source, an ultra-low power error amplifier and an ultra-low power comparator, and the method includes steps S601 to S604;

[0089] S601: the power tube array forms a conducting circuit in a conducting state;

[0090] S602: The ultra-low power consumption current source provides a bias current for the ultra-low power consumption error amplifier and the ultra-low power consumption comparator;

[0091] S603: The ultra-low power consumption error amplifier adjusts the gate voltage of the power tube array to adjust the voltage drop value between the circuit input and the circuit output of the conduction circuit;

[0092] S604: The ultra-low power consumption comparator monitors the voltage drop value, and adjusts the conduction state of the power tube array based on the voltage drop value and the target threshold.

[0093] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific process of the method described above can refer to the corresponding process in the aforementioned circuit embodiment, and will not be repeated here.

[0094] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0095] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0096] In addition, each functional unit in the embodiment provided by the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0097] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0098] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0099] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can still modify the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or perform equivalent replacements on some of the technical features thereof; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. They should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A low power consumption, low voltage drop, unidirectional conduction circuit, characterized in that: The circuit comprises a power tube array (1), an ultra-low power consumption current source (2), an ultra-low power consumption error amplifier (3) and an ultra-low power consumption comparator (4); The power tube array (1) is used to form a conducting circuit in a conducting state; The ultra-low power consumption current source (2) is used to provide a bias current for the ultra-low power consumption error amplifier (3) and the ultra-low power consumption comparator (4); The ultra-low power consumption error amplifier (3) is used to adjust the gate voltage of the power tube array (1) so as to adjust the voltage drop value between the circuit input and the circuit output of the conduction circuit; The ultra-low power consumption comparator (4) is used to monitor the voltage drop value and adjust the conduction state of the power tube array (1) based on the voltage drop value and the target threshold.

2. The circuit according to claim 1, characterized in that The step of adjusting the conduction state of the power tube array (1) based on the voltage drop value and the target threshold value comprises: determining whether the pressure drop value exceeds the target threshold; If the voltage drop value does not exceed the target threshold value, the output control signal controls the power tube array (1) to be turned off, so as to disconnect the conduction circuit.

3. The circuit according to claim 2, characterized in that After determining whether the voltage drop value exceeds the target threshold, if the voltage drop value exceeds the target threshold, the power tube array (1) is kept in a conducting state to form the conducting circuit.

4. The circuit according to claim 1, characterized in that The current value of the bias current is 10 nA, and the target threshold is -30 mV.

5. The circuit according to claim 1, characterized in that The power tube array (1) comprises a plurality of PMOS tubes, and the PMOS tubes are connected in parallel.

6. The circuit according to claim 1, characterized in that The ultra-low power consumption current source (2) comprises a first PMOS tube (201), a second PMOS tube (202), a third PMOS tube (203), a fourth PMOS tube (204), a first NMOS tube (205), a second NMOS tube (206) and a first resistor (207); The source of the first PMOS tube (201), the source of the second PMOS tube (202), the source of the third PMOS tube (203), and the source of the fourth PMOS tube (204) are respectively connected to the circuit input of the conduction circuit and the source of the power tube array (1); the gate of the first PMOS tube (201), the gate of the second PMOS tube (202), the gate of the third PMOS tube (203), and the gate of the fourth PMOS tube (204) are connected to each other; the drain of the first PMOS tube (201) is respectively connected to the drain of the first NMOS tube (205), the drain of the first NMOS tube (206), and the drain of the first NMOS tube (207). The gate of the first NMOS tube (205) is connected to the gate of the second NMOS tube (206); the drain of the second NMOS tube (206) is connected to the drain of the fourth PMOS tube (204) and the gate of the fourth PMOS tube (204) respectively; the source of the first NMOS tube (205) is grounded; the source of the second NMOS tube (206) is grounded through the first resistor (207); the drain of the second PMOS tube (202) is connected to the ultra-low power consumption error amplifier (3); and the drain of the third PMOS tube (203) is connected to the ultra-low power consumption comparator (4).

7. The circuit according to claim 6, characterized in that The bias current is: Among them, is the electron mobility of the NMOS tube, is the unit area gate capacitance of the NMOS tube, is the resistance value of the first resistor (207), and is the ratio of the number of the second NMOS tube (206) to the number of the first NMOS tube (205).

8. The circuit according to claim 1, characterized in that The ultra-low power consumption error amplifier (3) comprises a fifth PMOS tube (301), a sixth PMOS tube (302), a seventh PMOS tube (303), a third NMOS tube (304), a fourth NMOS tube (305), a fifth NMOS tube (306), a sixth NMOS tube (307), a seventh NMOS tube (308), a first voltage source (309) and a first capacitor (310); The source of the fifth PMOS tube (301), the source of the sixth PMOS tube (302), and the source of the seventh PMOS tube (303) are respectively connected to the circuit input of the conduction circuit; the gate of the fifth PMOS tube (301) is respectively connected to the gate of the sixth PMOS tube (302) and the drain of the sixth PMOS tube (302); the drain of the fifth PMOS tube (301) is respectively connected to the drain of the third NMOS tube (304), the first end of the first capacitor (310), and the gate of the seventh PMOS tube (303); the drain of the seventh PMOS tube (303) is respectively connected to the second end of the first capacitor (310) and the gate of the power tube array (1); the drain of the sixth PMOS tube (302) is connected to the drain of the fourth NMOS tube (305); the source of the third NMOS tube (304) is respectively connected to the drain of the fourth NMOS tube (305); the drain of the third NMOS tube (304) is respectively connected to the drain of the fourth NMOS tube (305); the drain of the third NMOS tube (304) is respectively connected to the drain of the fourth NMOS tube (305); the drain of the third NMOS tube (304) is respectively connected to the drain of the fourth NMOS tube (305); the drain of the third NMOS tube (304) is respectively connected to the drain of the third NMOS tube (304). The gate of the third NMOS tube (304) is connected to the positive electrode of the first voltage source (309), and the negative electrode of the first voltage source (309) is connected to the circuit output of the conduction circuit; the drain of the fifth NMOS tube (306) is connected to the ultra-low power consumption current source (2) and the gate of the fifth NMOS tube (306) respectively; the gate of the fifth NMOS tube (306), the gate of the sixth NMOS tube (307), and the gate of the seventh NMOS tube (308) are connected to each other; the drain of the seventh NMOS tube (308) is connected to the circuit output of the conduction circuit; the source of the fifth NMOS tube (306), the source of the sixth NMOS tube (307), and the source of the seventh NMOS tube (308) are all grounded.

9. The circuit according to claim 1, characterized in that The ultra-low power consumption comparator (4) comprises an eighth PMOS tube (401), a ninth PMOS tube (402), a tenth PMOS tube (403), an eleventh PMOS tube (404), a twelfth PMOS tube (405), a thirteenth PMOS tube (406), a fourteenth PMOS tube (407), an eighth NMOS tube (408), a ninth NMOS tube (409), a tenth NMOS tube (410), an eleventh NMOS tube (411), a twelfth NMOS tube (412), a thirteenth NMOS tube (413), a fourteenth NMOS tube (414), a fifteenth NMOS tube (415), a sixteenth NMOS tube (416) and a second voltage source (417); The source of the eighth PMOS tube (401), the source of the ninth PMOS tube (402), the source of the tenth PMOS tube (403), the source of the eleventh PMOS tube (404), and the source of the fourteenth PMOS tube (407) are respectively connected to the circuit input of the conduction circuit; the gate of the eighth PMOS tube (401), the gate of the ninth PMOS tube (402), the gate of the tenth PMOS tube (403), and the gate of the eleventh PMOS tube (404) are connected to each other; the drain of the eighth PMOS tube (401) is respectively connected to the gate of the eighth PMOS tube (401), the drain of the eleventh NMOS tube (411), and the gate of the eleventh NMOS tube (411). The drain of the ninth PMOS tube (402) is respectively connected to the source of the twelfth PMOS tube (405) and the drain of the eighth NMOS tube (408); the gate of the eighth NMOS tube (408) is connected to the positive electrode of the second voltage source (417), and the negative electrode of the second voltage source (417) is connected to the circuit input of the conduction circuit; the source of the eighth NMOS tube (408) is respectively connected to the gate of the twelfth PMOS tube (405), the gate of the thirteenth PMOS tube (406), the source of the ninth NMOS tube (409), and the drain of the twelfth NMOS tube (412); the drain of the ninth NMOS tube (409 ... The gate electrode of the ninth NMOS tube (409) is connected to the circuit output of the conduction circuit; the gate electrode of the eleventh NMOS tube (411), the gate electrode of the tenth NMOS tube (410), the gate electrode of the twelfth NMOS tube (412), and the gate electrode of the sixteenth NMOS tube (416) are connected to each other; the drain electrode of the tenth NMOS tube (410) is connected to the gate electrode of the tenth NMOS tube (410) and the ultra-low power consumption current source (2); the drain electrode of the twelfth PMOS tube (405) is connected to the gate electrode of the thirteenth NMOS tube (413) and the gate electrode of the twelfth PMOS tube (405). The drain of the power tube array (1) is connected to the gate of the fifteenth NMOS tube (415); the drain of the thirteenth PMOS tube (406) is connected to the drain of the fourteenth NMOS tube (414) and the gate of the fourteenth NMOS tube (414); the gate of the thirteenth NMOS tube (413) is connected to the gate of the fourteenth NMOS tube (414); the drain of the eleventh PMOS tube (404) is connected to the gate of the fourteenth PMOS tube (407) and the drain of the fifteenth NMOS tube (415); the drain of the fourteenth PMOS tube (407) is connected to the gate of the power tube array (1) and the drain of the sixteenth NMOS tube (416);The source of the tenth NMOS tube (410), the source of the eleventh NMOS tube (411), the source of the twelfth NMOS tube (412), the source of the thirteenth NMOS tube (413), the source of the fourteenth NMOS tube (414), the source of the fifteenth NMOS tube (415), and the source of the sixteenth NMOS tube (416) are all grounded. ; 10. A circuit power consumption optimization method, characterized in that: Applied to a low-power unidirectional conduction circuit, the circuit includes a power tube array, an ultra-low power current source, an ultra-low power error amplifier and an ultra-low power comparator, and the method includes: The power tube array forms a conducting circuit in a conducting state; The ultra-low power consumption current source provides bias current for the ultra-low power consumption error amplifier and the ultra-low power consumption comparator; The ultra-low power consumption error amplifier adjusts the gate voltage of the power tube array to adjust the voltage drop value between the circuit input and the circuit output of the conduction circuit; The ultra-low power consumption comparator monitors the voltage drop value, and adjusts the conduction state of the power tube array based on the voltage drop value and a target threshold.

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