A satellite short message radio frequency circuit and frequency conversion method thereof

Abstract

The present application relates to a satellite short message radio frequency circuit and a frequency conversion method thereof, including a single phase-locked loop circuit; the phase-locked loop circuit is coupled with an oscillator module; a local oscillator frequency division circuit is coupled with the phase-locked loop circuit, the local oscillator frequency division circuit divides the VCO signal output by the oscillator module into a receiving local oscillator signal by two and sends it to a receiving down-conversion circuit; the local oscillator frequency division circuit divides the VCO signal output by the oscillator module into a transmitting local oscillator signal by three and sends it to a transmitting up-conversion circuit; the receiving down-conversion circuit mixes the receiving local oscillator signal and the signal output by the receiving radio frequency circuit to generate a receiving radio frequency signal, and sends the receiving radio frequency signal to the receiving baseband circuit; the transmitting up-conversion circuit mixes the transmitting local oscillator signal and the signal output by the transmitting baseband circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit. The present application has the effect of reducing the area and power consumption of the phase-locked loop in the radio frequency circuit.

Description

Technical Field

[0001] The present application relates to the field of RDSS radio frequency technology, and in particular to a satellite short message radio frequency circuit and a frequency conversion method thereof. Background Art

[0002] With the growing demand for satellite short messages, the most challenging difficulty in integrating this function into portable terminal devices such as mobile phones, children's watches, and elderly monitoring equipment is the large area and power consumption of the existing satellite short message (RDSS) RF chip. According to the satellite communication frequency defined by the Radio Determination Satellite System RDSS, the satellite downlink and terminal receiving frequency range is 2483.5~2500MHz, while the satellite uplink and terminal transmitting frequency range is 1610~1626.5MHz, which is quite far apart. The RDSS satellite communication service requires uninterrupted terminal reception, and the terminal RF chip needs to have the ability to receive and transmit simultaneously, that is, full-duplex operation capability. Both reception and transmission require the use of a local oscillator signal close to the wireless signal frequency to complete the frequency conversion operation of the RF signal and the baseband signal. The local oscillator signal needs to be accurate and stable, and is generally provided by the phase-locked loop inside the chip.

[0003] Since the receiving and transmitting frequencies are far apart and there is no simple integer multiple relationship, independent phase-locked loops are usually required to run at integer multiples of the local oscillator frequency. Frequency division is then used to provide at least four phases of receiving local oscillator signals for generating I and Q orthogonal baseband signals. The transmitting phase-locked loop also provides multiple phases of transmitting local oscillator signals for up-conversion through frequency division.

[0004] Therefore, conventional RDSS RF chips require independently operated receive phase-locked loops and transmit phase-locked loops. If the baseband processing unit requires a working clock that has special requirements and cannot have a compatible integer multiple relationship with the receive local oscillator and transmit local oscillator signal frequencies, a third phase-locked loop must be provided separately. A fully integrated phase-locked loop usually occupies more than 1 / 3 of the entire receive or transmit circuit because it needs to include circuits with huge area consumption such as resonant inductors, loop filter resistors and capacitors. Therefore, the area and power consumption of the RF chip are large and need to be improved. Summary of the invention

[0005] In order to reduce the area and power consumption of the phase-locked loop in the radio frequency circuit and thus reduce the area and power consumption of the entire RDSS radio frequency chip, the present application provides a satellite short message radio frequency circuit and a frequency conversion method thereof.

[0006] The above-mentioned invention objective of the present application is achieved through the following technical solutions:

[0007] A satellite short message radio frequency circuit, comprising a single phase-locked loop circuit, a local oscillator frequency division circuit, a receiving down-conversion circuit, a transmitting up-conversion circuit, a receiving baseband circuit, a receiving radio frequency circuit, a transmitting baseband circuit and a transmitting radio frequency circuit;

[0008] The phase-locked loop circuit is coupled to an oscillator module;

[0009] The local oscillator frequency division circuit is coupled to the phase-locked loop circuit, and is used to divide the VCO signal output by the oscillator module into two frequencies to obtain a receiving local oscillator signal and send it to the receiving down-conversion circuit; the local oscillator frequency division circuit is also used to divide the VCO signal output by the oscillator module into three frequencies to obtain a transmitting local oscillator signal and send it to the transmitting up-conversion circuit;

[0010] The receiving down-conversion circuit is coupled to the receiving baseband circuit; the receiving down-conversion circuit mixes the receiving local oscillator signal and the signal output by the receiving radio frequency circuit to generate a receiving radio frequency signal, and sends the receiving radio frequency signal to the receiving baseband circuit;

[0011] The transmit up-conversion circuit is coupled to the transmit RF circuit; the transmit up-conversion circuit mixes the transmit local oscillator signal and the signal output by the transmit baseband circuit to generate a transmit RF signal, and sends the transmit RF signal to the transmit RF circuit.

[0012] Furthermore, the oscillator module presets an operating frequency numerical range according to the frequencies of the received RF signal and the transmitted RF signal, and the operating frequency numerical range is 1.8-2.2 times the frequency of the received RF signal and 2.8-3.2 times the frequency of the transmitted RF signal, or is equal to 3 times the center frequency value of the transmitted RF signal.

[0013] Further, the local oscillator frequency division circuit includes a receiving local oscillator two-frequency division circuit;

[0014] The input end of the receiving local oscillator frequency division circuit is coupled to the phase-locked loop circuit; the receiving local oscillator frequency division circuit is used to divide the VCO signal output by the oscillator module into a first receiving local oscillator signal and send it to the receiving down-conversion circuit;

[0015] The receiving down-conversion circuit includes a first mixer; the first mixer is coupled to the receiving RF circuit, and mixes the signal output by the receiving RF circuit with the first receiving local oscillator signal to generate a first receiving RF signal, and sends the first receiving RF signal to the receiving baseband circuit.

[0016] Furthermore, the receiving local oscillator binary frequency division circuit includes a receiving local oscillator LO1 generating circuit; the receiving local oscillator LO1 generating circuit includes two latches, the CK and CKb pins of the first latch and the second latch are both coupled to the phase-locked loop circuit to input the vco signal, the Y and Yb pins of the first latch are coupled to the D and Db pins of the second latch, and the Y and Yb pins of the second latch are coupled to the Db and D pins of the first latch.

[0017] Further, the local oscillator frequency division circuit includes a receiving local oscillator frequency division circuit by two and a receiving local oscillator frequency division circuit by N; wherein N is a positive integer;

[0018] The input end of the receiving local oscillator frequency division circuit is coupled to the phase-locked loop circuit; the receiving local oscillator frequency division circuit is used to divide the VCO signal output by the oscillator module into a first receiving local oscillator signal and send it to the receiving down-conversion circuit;

[0019] The input end of the receiving local oscillator N-frequency division circuit is coupled to the phase-locked loop circuit, and the receiving local oscillator N-frequency division circuit is used to divide the vco signal output by the oscillator module into a second receiving local oscillator signal by N and send it to the receiving down-conversion circuit;

[0020] The receiving down-conversion circuit comprises a first mixer and a second mixer;

[0021] The first mixer is coupled to the receiving RF circuit, and the first mixer mixes the signal output by the receiving RF circuit with the first receiving local oscillator signal to generate a first receiving RF signal, and sends the first receiving RF signal to the second mixer;

[0022] The second mixer is coupled to the first mixer, and the second mixer mixes the first received RF signal output by the first mixer with the second received local oscillator signal to generate a second received RF signal, and sends the second received RF signal to the receiving baseband circuit.

[0023] Further, the receiving local oscillator N-division circuit includes a third latch, a fourth latch and a pre-div_by_N / 2 circuit, the div_by_N / 2 circuit generates N / 2-divided signals pre_p and pre_n according to the input vco signal, the CK and CKb pins of the third latch and the fourth latch are coupled to the N / 2 divider, the Y and Yb pins of the third latch are coupled to the D and Db pins of the fourth latch, and the Y and Yb pins of the fourth latch are coupled to the Db and D pins of the third latch;

[0024] The value of N satisfies:

[0025] ;

[0026] or:

[0027] ;

[0028] Wherein, Fref represents the received RF signal, Fvco represents the oscillation frequency synthesized by the phase-locked loop circuit, and Fadc represents the working clock of the ADC module; when it is necessary to generate an orthogonal RF signal output, N is an even number.

[0029] Furthermore, the local oscillator frequency division circuit also includes a transmitting local oscillator frequency division circuit; the transmitting local oscillator frequency division circuit is used to divide the VCO signal output by the oscillator module into a transmitting local oscillator signal;

[0030] The transmitting local oscillator three-frequency circuit includes a first half-phase inverter, a second half-phase inverter and a third half-phase inverter; the clk pins of the first half-phase inverter, the second half-phase inverter and the third half-phase inverter are all coupled to the phase-locked PLL; the out pin of the first half-phase inverter is coupled to the in pin of the second half-phase inverter, the out pin of the second half-phase inverter is coupled to the in pin of the third half-phase inverter, the out pin of the third half-phase inverter is coupled to the in pin of the first half-phase inverter, and the out pin of the third half-phase inverter outputs the three-frequency local oscillator signal TxL0 of the vco signal.

[0031] Further, the first half-phase inverter includes a first pmos tube, a second pmos tube, a first nmos tube and a second nmos tube; the gates of the first pmos tube and the second nmos tube are both coupled to the clk pin, the gate of the second pmos tube and the gate of the first nmos tube are both coupled to the in pin, the drain of the first pmos tube is coupled to the vdd pin, the drain of the second pmos tube is coupled to the source of the first pmos tube, the source of the second pmos tube and the drain of the first nmos tube are both coupled to the out pin, the drain of the second nmos tube is coupled to the source of the first nmos tube, and the source of the second nmos tube is coupled to the vss pin.

[0032] Furthermore, the phase-locked loop circuit includes a frequency division module, a frequency detection and phase detection module, a charge pump module, a loop filter module, and an oscillator module; the frequency division module divides the output signal of the oscillator module to obtain an Fdiv signal; the frequency detection and phase detection module is connected to a reference clock signal Fref and a frequency division signal Fdiv, and the output end of the frequency detection and phase detection module is coupled to the input end of the charge pump module; the output end of the charge pump module is coupled to the input end of the loop filter module, and the output end of the loop filter module is coupled to the input end of the oscillator module; the output end of the oscillator module is used as the output end of the phase-locked loop circuit to output the vco signal.

[0033] In addition, the present application also provides a frequency conversion method based on the above-mentioned satellite short message radio frequency circuit, including:

[0034] The local oscillator frequency division circuit divides the VCO signal output by the oscillator module into two frequencies to obtain a receiving local oscillator signal and sends it to the receiving down-conversion circuit;

[0035] The local oscillator frequency division circuit divides the VCO signal output by the oscillator module into a transmission local oscillator signal by three frequencies and sends it to the transmission up-conversion circuit;

[0036] The receiving down-conversion circuit mixes the receiving local oscillator signal and the signal output by the receiving radio frequency circuit to generate a receiving radio frequency signal, and sends the receiving radio frequency signal to the receiving baseband circuit; and

[0037] The transmitting up-conversion circuit mixes the transmitting local oscillator signal and the signal output by the transmitting baseband circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit.

[0038] In summary, the present application includes at least one of the following beneficial technical effects:

[0039] 1. Only one phase-locked loop circuit is used, and a special division-by-3 circuit is used to obtain a transmit local oscillator with a 50% duty cycle to complete the transmit up-conversion; the VCO signal is divided by 2 to obtain a receive primary local oscillator, and the input RF signal is converted for the first time to generate a first receive RF signal, and then the VCO signal is divided by N to obtain a secondary local oscillator, and the first receive RF signal is mixed for the second time to obtain a second receive RF signal. In addition, the signal of the operating frequency required by the ADC can also be obtained by frequency division, and its value is specifically reflected in the following aspects: overcoming the large difference in RDSS receive and transmit RF frequencies, providing complete up- and down-conversion functions; by reducing the number of required phase-locked loop circuits, the RF chip area and power consumption are greatly reduced; a single phase-locked loop circuit meets the reception and transmission work at the same time, avoiding the adverse effects of multiple phase-locked loop circuits pulling each other inside the same die, and reducing interference factors.

[0040] 2. The key points include special frequency planning, appropriate frequency division method, and reasonable frequency conversion scheme so that a phase-locked loop circuit can provide all receiving and transmitting local oscillator signals, realize the frequency conversion function required for RDSS reception and transmission, and form the RDSS terminal RF transceiver circuit.

[0041] 3. A single phase-locked loop circuit obtains the receiving local oscillator signal and the transmitting local oscillator signal by dividing by 2 and 3 respectively, which cannot guarantee the accuracy of the receiving local oscillator and the transmitting local oscillator at the same time. It can only take care of the accuracy of one of them. The one with the difference can be eliminated by the second frequency conversion scheme, and still obtain sufficient accuracy. Specifically for the RDSS RF transceiver system here, it is best to select the transmission frequency conversion once, that is, the accurate frequency planning scheme of the transmitting local oscillator, so that the phase-locked loop circuit phase-locked frequency is aligned with the 3 times frequency point of the transmitting RF frequency, and the reception relies on two frequency conversions to complete the frequency conversion from the RF to the required receiving RF. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of the internal circuit structure of a conventional RDSS radio frequency chip in the background technology of this application;

[0043] Figure 2 This is a schematic diagram of the circuit structure of a satellite short message radio frequency circuit of the present application;

[0044] Figure 3 It is a structural schematic diagram of a phase-locked loop circuit in an embodiment of a satellite short message radio frequency circuit of the present application;

[0045] Figure 4 It is a circuit structure diagram of a receiving local oscillator two-frequency division circuit in an embodiment of a satellite short message radio frequency circuit of the present application;

[0046] Figure 5 It is a circuit structure diagram of a receiving local oscillator N-frequency division circuit in an embodiment of a satellite short message radio frequency circuit of the present application;

[0047] Figure 6 It is a circuit structure diagram of a transmitting local oscillator three-frequency division circuit in an embodiment of a satellite short message radio frequency circuit of the present application;

[0048] Figure 7 It is an internal circuit diagram of a half-phase inverter in an embodiment of a satellite short message radio frequency circuit of the present application. DETAILED DESCRIPTION

[0049] The following is combined with Figure 1-Figure 7 This application is described in further detail.

[0050] According to the satellite communication frequency defined by the radio determination satellite system, the terminal receiving frequency range is 2483.5~2500MHz, while the (terminal transmitting) frequency range is 1610~1626.5MHz, and the two are 873.5M apart. The RDSS satellite communication service requires that the terminal receive continuously, and the transmission timing can be selected independently. For the terminal RF chip, it is necessary to have the ability to receive and transmit simultaneously, that is, full-duplex operation capability. Both reception and transmission need to use a local oscillator signal close to the frequency of the wireless signal to complete the frequency conversion operation of the RF signal and the baseband signal. The local oscillator signal needs to be accurate and stable, and is generally provided by the phase-locked loop in the chip. Since the receiving and transmitting frequencies are far apart and there is no simple integer multiple relationship, independent phase-locked loops are usually required to run at integer multiples of the local oscillator frequency, and then use frequency division to provide at least four phases of receiving local oscillator signals to generate I and Q two-way orthogonal baseband signals. The transmitting phase-locked loop also provides multiple phases of transmitting local oscillator signals for up-conversion through frequency division.

[0051] Reference Figure 1 Therefore, conventional RDSS RF chips require independently operated receiving phase-locked loops and transmitting phase-locked loops. If the working clock required by the baseband processing unit has special requirements and cannot have a compatible integer multiple relationship with the receiving local oscillator and transmitting local oscillator signal frequencies, a third phase-locked loop needs to be provided separately. Since a fully integrated phase-locked loop needs to include circuits with huge area consumption such as resonant inductors, loop filter resistors and capacitors, it usually occupies a large area, such as more than 1 / 3 of the entire receiving or transmitting circuit. The present invention hopes to reduce the area and power consumption of the entire RDSS RF chip by reducing the area and power consumption of the phase-locked loop.

[0052] In some embodiments, Figure 2 As shown, the present application discloses a satellite short message radio frequency circuit, including a single phase-locked loop circuit, a local oscillator frequency division circuit, a receiving down-conversion circuit, a transmitting up-conversion circuit, a receiving baseband circuit, a receiving radio frequency circuit, a transmitting baseband circuit and a transmitting radio frequency circuit;

[0053] The phase-locked loop circuit is coupled to an oscillator module;

[0054] The local oscillator frequency division circuit is coupled to the phase-locked loop circuit, and is used to divide the VCO signal output by the oscillator module into two frequencies to obtain a receiving local oscillator signal and send it to the receiving down-conversion circuit; the local oscillator frequency division circuit is also used to divide the VCO signal output by the oscillator module into three frequencies to obtain a transmitting local oscillator signal and send it to the transmitting up-conversion circuit;

[0055] The receiving down-conversion circuit is coupled to the receiving baseband circuit; the receiving down-conversion circuit mixes the receiving local oscillator signal and the signal output by the receiving RF circuit to generate a receiving RF signal, and sends the receiving RF signal to the receiving baseband circuit; the receiving RF signal is specifically a receiving RF signal.

[0056] The transmit up-conversion circuit is coupled to the transmit RF circuit; the transmit up-conversion circuit mixes the transmit local oscillator signal and the signal output by the transmit baseband circuit to generate a transmit RF signal, and sends the transmit RF signal to the transmit RF circuit.

[0057] Furthermore, the oscillator module presets an operating frequency numerical range according to the frequencies of the received RF signal and the transmitted RF signal, and the operating frequency numerical range is 1.8-2.2 times the frequency of the received RF signal and 2.8-3.2 times the frequency of the transmitted RF signal, or is equal to 3 times the center frequency value of the transmitted RF signal.

[0058] In some embodiments, the local oscillator frequency division circuit includes a receiving local oscillator frequency division circuit;

[0059] The input end of the receiving local oscillator frequency division circuit is coupled to the phase-locked loop circuit; the receiving local oscillator frequency division circuit is used to divide the VCO signal output by the oscillator module into a first receiving local oscillator signal and send it to the receiving down-conversion circuit;

[0060] The receiving down-conversion circuit includes a first mixer; the first mixer is coupled to the receiving RF circuit, and mixes the signal output by the receiving RF circuit with the first receiving local oscillator signal to generate a first receiving RF signal, and sends the first receiving RF signal to the receiving baseband circuit.

[0061] In some embodiments, the receiving local oscillator binary frequency division circuit includes a receiving local oscillator LO1 generation circuit; the receiving local oscillator LO1 generation circuit includes two latches, the CK and CKb pins of the first latch and the second latch are both coupled to the phase-locked loop circuit to input the vco signal, the Y and Yb pins of the first latch are coupled to the D and Db pins of the second latch, and the Y and Yb pins of the second latch are coupled to the Db and D pins of the first latch.

[0062] In some embodiments, the local oscillator frequency division circuit includes a receiving local oscillator frequency division circuit by two and a receiving local oscillator frequency division circuit by N; wherein N is a positive integer;

[0063] The input end of the receiving local oscillator frequency division circuit is coupled to the phase-locked loop circuit; the receiving local oscillator frequency division circuit is used to divide the VCO signal output by the oscillator module into a first receiving local oscillator signal and send it to the receiving down-conversion circuit;

[0064] The input end of the receiving local oscillator N-frequency division circuit is coupled to the phase-locked loop circuit, and the receiving local oscillator N-frequency division circuit is used to divide the vco signal output by the oscillator module into a second receiving local oscillator signal by N and send it to the receiving down-conversion circuit;

[0065] The receiving down-conversion circuit comprises a first mixer and a second mixer;

[0066] The first mixer is coupled to the receiving RF circuit, and the first mixer mixes the signal output by the receiving RF circuit with the first receiving local oscillator signal to generate a first receiving RF signal, and sends the first receiving RF signal to the second mixer;

[0067] The second mixer is coupled to the first mixer, and the second mixer mixes the first received RF signal output by the first mixer with the second received local oscillator signal to generate a second received RF signal, and sends the second received RF signal to the receiving baseband circuit.

[0068] In some embodiments, the receiving local oscillator N-division circuit includes a third latch, a fourth latch and a pre-div_by_N / 2 circuit, the div_by_N / 2 circuit generates N / 2-divided signals pre_p and pre_n according to the input vco signal, the CK and CKb pins of the third latch and the fourth latch are coupled to the N / 2 divider, the Y and Yb pins of the third latch are coupled to the D and Db pins of the fourth latch, and the Y and Yb pins of the fourth latch are coupled to the Db and D pins of the third latch;

[0069] The value of N satisfies:

[0070] ;

[0071] or:

[0072] ;

[0073] Wherein, Fref represents the received RF signal, Fvco represents the oscillation frequency synthesized by the phase-locked loop circuit, and Fadc represents the working clock of the ADC module; when it is necessary to generate an orthogonal RF signal output, N is an even number.

[0074] In some embodiments, the local oscillator frequency division circuit further includes a transmitting local oscillator frequency division circuit; the transmitting local oscillator frequency division circuit is used to divide the vco signal output by the oscillator module into a transmitting local oscillator signal;

[0075] The transmitting local oscillator three-frequency circuit includes a first half-phase inverter, a second half-phase inverter and a third half-phase inverter; the clk pins of the first half-phase inverter, the second half-phase inverter and the third half-phase inverter are all coupled to the phase-locked PLL; the out pin of the first half-phase inverter is coupled to the in pin of the second half-phase inverter, the out pin of the second half-phase inverter is coupled to the in pin of the third half-phase inverter, the out pin of the third half-phase inverter is coupled to the in pin of the first half-phase inverter, and the out pin of the third half-phase inverter outputs the three-frequency local oscillator signal TxL0 of the vco signal.

[0076] In some embodiments, the first half-phase inverter includes a first pmos tube, a second pmos tube, a first nmos tube and a second nmos tube; the gates of the first pmos tube and the second nmos tube are both coupled to the clk pin, the gate of the second pmos tube and the gate of the first nmos tube are both coupled to the in pin, the drain of the first pmos tube is coupled to the vdd pin, the drain of the second pmos tube is coupled to the source of the first pmos tube, the source of the second pmos tube and the drain of the first nmos tube are both coupled to the out pin, the drain of the second nmos tube is coupled to the source of the first nmos tube, and the source of the second nmos tube is coupled to the vss pin.

[0077] In some embodiments, the phase-locked loop circuit includes a frequency division module, a frequency detection and phase detection module, a charge pump module, a loop filter module, and an oscillator module; the frequency division module divides the output signal of the oscillator module to obtain an Fdiv signal; the frequency detection and phase detection module is connected to a reference clock signal Fref and a frequency division signal Fdiv, and the output end of the frequency detection and phase detection module is coupled to the input end of the charge pump module; the output end of the charge pump module is coupled to the input end of the loop filter module, and the output end of the loop filter module is coupled to the input end of the oscillator module; the output end of the oscillator module is used as the output end of the phase-locked loop circuit to output the vco signal.

[0078] Specifically, Figure 2 As shown, the receiving radio frequency (RxRF) circuit 11 of the present application uses a low noise amplifier to amplify the input radio frequency signal RxANT under the premise of ensuring a sufficient signal-to-noise ratio.

[0079] The phase-locked loop circuit 12 includes a frequency detection and phase detection module and a loop filter module. The frequency detection and phase detection module is connected to a reference clock signal Fref13. The output end of the frequency detection and phase detection module is coupled to the input end of the loop filter module. The output end of the loop filter module is coupled to the input end of the phase-locked loop circuit. The output end of the phase-locked loop circuit outputs a vco signal with a frequency of Fvco. The local oscillator frequency division circuit is coupled to the frequency detection and phase detection circuit. Figure 3 shown.

[0080] The local oscillator frequency division circuit 14 includes a receiving local oscillator frequency division circuit and a receiving local oscillator N frequency division circuit. The receiving local oscillator frequency division circuit includes a frequency divider div and a mixer MIX1. The input end of the frequency divider div is coupled to the phase-locked loop circuit to receive the vco signal, and outputs a frequency division frequency of Flo1 to the mixer MIX1. The mixer MIX1 performs a first frequency conversion and outputs a first radio frequency frequency Fif1 to the first radio frequency signal filtering and amplification (RxIF1) processing circuit 15 to filter out the high-frequency mixing components generated by the first mixing, and also suppress out-of-band interference to a certain extent; the receiving local oscillator N frequency division circuit includes an N frequency divider divN mixer MIX2. The input end of the N frequency divider divN is coupled to the phase-locked loop circuit to receive the vco signal, and outputs a preset frequency division frequency. The N-divided vco signal after frequency division is sent to the mixer MIX2 with a frequency of Flo2. The input end of the mixer MIX2 is coupled to the filtering and amplifying (RxIF1) processing circuit of the first RF signal to mix Fif1 and Flo2. The output end of the mixer MIX2 is connected in series with the receiving RF (RxIF2) circuit 16, and then outputs the RF vco signal to the receiving baseband circuit. The receiving baseband circuit (RxBB) 17 performs analog-to-digital conversion on the RF, i.e. ADC and digital RF processing. The receiving RF (RxIF2) circuit 16 amplifies, filters and gain controls the final RF signal obtained by the frequency conversion so as to provide a signal with a suitable amplitude to the subsequent ADC, filter out the additional mixing components generated by the filtering, and also filter out unnecessary out-of-band signals to reduce interference.

[0081] The local oscillator frequency division circuit also includes a transmitting local oscillator three-way frequency division circuit, which is used to generate the three-way frequency division of the vco signal. The transmitting local oscillator (TxLO) is generated from the three-way frequency division of the VCO signal, that is, the RDSS system transmitting carrier frequency 1614.26MHz and 1618.34MHz are selected near three times. As an implementation example of this embodiment, 4842.78MHz and 4,855.02MHz are selected respectively. The local oscillator three-way frequency division circuit includes a three-way frequency divider div and a mixer MIX3. The three-way frequency divider div is coupled to the phase-locked loop circuit to receive the vco signal of the Fvco frequency, and the output end of the three-way frequency divider div is coupled to the mixer MIX3.

[0082] The output end of the mixer MIX3 is coupled to the transmit radio frequency (TxRF) circuit 18, and the input end of the mixer MIX3 is coupled to the transmit radio frequency (TxIF) circuit 19, and the analog radio frequency is appropriately filtered and amplified before being sent to the transmit up-conversion processing; the output end of the mixer MIX3 is coupled to the transmit radio frequency (TxRF) circuit 18, and undergoes appropriate differential signal and single-ended signal processing to meet the needs of the off-chip power amplifier (PA); the input end of the transmit radio frequency (TxIF) circuit 19 is coupled to the transmit baseband circuit (TxBB) 20, and the RDSS uplink information to be transmitted is digitally processed, and BPSK can be generated and handed over to the transmit radio frequency (TxIF) circuit 19 for processing, or it can be handed over to the transmit radio frequency (TxIF) circuit 19 for processing after digital-to-analog conversion.

[0083] like Figure 4 As shown, the divider div of the receiving local oscillator divider circuit includes a receiving local oscillator lo1 generating circuit with a frequency of Flo1, and two latches latch of the receiving local oscillator lo1 generating circuit. The CK pins of the first latch and the second latch are both coupled to the phase-locked loop circuit to receive the vco signal, the D pin of the first latch is coupled to the Qb pin of the second latch, the Q pin of the first latch is coupled to the D pin of the second latch, and the Q pin of the second latch outputs the receiving local oscillator lo1.

[0084] like Figure 5 As shown, the receiving local oscillator N-division circuit includes a third latch and a fourth latch, the CK pins of the third latch and the fourth latch are coupled to the N-divider divN to receive the N-divided vco signal, the D pin of the third latch is coupled to the Qb pin of the fourth latch, the Q pin of the third latch is coupled to the D pin of the fourth latch, and the Q pin of the fourth latch outputs the receiving local oscillator lo2, and the value of N satisfies the following formula:

[0085] ; Wherein, Fref represents the received RF input signal, and the RDSS center frequency is 2491.75 MHz; Fvco represents the oscillation frequency synthesized by the PLL, and as an example of this embodiment, it is 4855.02 MHz; Fadc represents the working clock of the ADC module, and as an example of this embodiment, it is 76 MHz. As an example of this embodiment, N=96 can be taken here.

[0086] like Figure 6As shown, the transmitting local oscillator three-frequency division circuit includes three half-phase inverters, the clk pins of the first half-phase inverter, the second half-phase inverter and the third half-phase inverter are all coupled to the phase-locked PLL, the in pin of the first half-phase inverter is coupled to the out pin of the third half-phase inverter, the out pin of the first half-phase inverter is coupled to the in pin of the second half-phase inverter, the in pin of the second half-phase inverter is coupled to the out pin of the third half-phase inverter, and the out pin of the third half-phase inverter outputs the three-frequency division TxL0 of the vco signal. The use of three half-phase inverters realizes that the TxLO signal has a 50% duty cycle.

[0087] like Figure 7 As shown, the half-phase inverter includes a first pmos tube, a second pmos tube, a first nmos tube and a second nmos tube, the gates of the first pmos tube and the second nmos tube are both coupled to the clk pin, the gate of the second pmos tube and the gate of the first nmos tube are both coupled to the in pin, the drain of the first pmos tube is coupled to the vdd pin, the drain of the second pmos tube is coupled to the source of the first pmos tube, the source of the second pmos tube and the drain of the first nmos tube are both coupled to the out pin, the drain of the second nmos tube is coupled to the source of the first nmos tube, and the source of the second nmos tube is coupled to the vss pin.

[0088] In some embodiments, the present application further provides a frequency conversion method based on the above-mentioned satellite short message radio frequency circuit, including:

[0089] The local oscillator frequency division circuit divides the VCO signal output by the oscillator module into two frequencies to obtain a receiving local oscillator signal and sends it to the receiving down-conversion circuit;

[0090] The local oscillator frequency division circuit divides the VCO signal output by the oscillator module into a transmission local oscillator signal by three frequencies and sends it to the transmission up-conversion circuit;

[0091] The receiving down-conversion circuit mixes the receiving local oscillator signal and the signal output by the receiving radio frequency circuit to generate a receiving radio frequency signal, and sends the receiving radio frequency signal to the receiving baseband circuit; and

[0092] The transmitting up-conversion circuit mixes the transmitting local oscillator signal and the signal output by the transmitting baseband circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit.

[0093] The following is an explanation of some circuits involved in this application:

[0094] 1) A phase-locked loop circuit, in addition to the oscillator module, also includes an input reference clock signal, a main frequency divider, a phase frequency detector, a charge pump and a loop filter circuit, to implement a frequency synthesizer with the input reference clock as a reference, and to provide a stable high-frequency clock signal of the required target frequency. Other implementation schemes may also be a digital phase-locked loop, in which the phase frequency detector, the charge pump and the loop filter circuits are replaced by a time-to-digital converter, a digital filter and a digital frequency controlled oscillator module to implement the same frequency synthesizer and provide the required stable high-frequency clock signal;

[0095] 2) Receive RF (RxRF) circuit, which uses a low-noise amplifier to amplify the input RF signal while ensuring a sufficient signal-to-noise ratio;

[0096] 3) The filtering and amplification processing circuit (RxIF1) of the first RF signal between the two frequency conversions is mainly used to filter out the high-frequency mixing components generated by the first mixing, and also to suppress out-of-band interference to a certain extent;

[0097] 4) The receiving RF (RxIF2) circuit amplifies, filters and gain controls the final RF signal obtained by frequency conversion to provide a signal with appropriate amplitude to the subsequent ADC, filter out the additional mixing components generated by filtering, and also filter out unnecessary out-of-band signals to reduce interference;

[0098] 5) Receive baseband circuit (RxBB), which performs analog-to-digital conversion (ADC) and digital RF processing on the RF;

[0099] 6) Transmitting baseband circuit (TxBB), which digitally processes the RDSS uplink information to be transmitted, can generate BPSK and hand it over to TxIF for processing, or can go through digital-to-analog conversion (DAC) and then hand it over to TxIF for processing;

[0100] 7) Transmit RF circuit (TxIF), which performs appropriate filtering and amplitude amplification on the analog RF and sends it to the transmit up-conversion processing;

[0101] 8) The RF signal after transmission up-conversion needs to pass through the transmit RF (TxRF) circuit and undergo appropriate differential signal and single-ended signal processing to meet the needs of the off-chip power amplifier (PA).

[0102] The main functions and inventive concepts of this application are:

[0103] 1. Oscillator module that oscillates near a specific frequency

[0104] The operating frequency of the oscillator module needs to take into account both the receiving RF signal frequency and the transmitting RF signal frequency, and be locked by the phase-locked loop for frequency and stable phase. In view of the current characteristics of the RDSS RF signal receiving frequency of about 2491MHz and 1614MHz, a frequency close to 2 times the former and 3 times the latter is selected, such as Fvco=4842MHz.

[0105] 2. Appropriate frequency division method

[0106] Fvco uses a simple 2-way frequency division to get the receiving local oscillator frequency Frxlo = 2421MHz, and the transmitting local oscillator uses a 3-way frequency division to get Ftxlo = 1614. Three-way frequency division is not a conventional frequency division method. If you want to achieve a 3-way frequency division signal with equal phase division, a special design is required.

[0107] 3. The aforementioned single phase-locked loop obtains the receiving local oscillator and transmitting local oscillator signals respectively by dividing by 2 and 3, and cannot guarantee that the divided receiving local oscillator and transmitting local oscillator are accurate at the same time. It can only take care of one of them to be accurate, and the one with the difference relies on the second frequency conversion scheme to eliminate the difference. Taking into account the cost of two frequency conversions for receiving and transmitting, it is preferred to use a single frequency conversion for transmitting, that is, an accurate frequency planning scheme for the local oscillator, so that the phase-locked loop phase-locked frequency is aligned with the 3 times frequency point of the transmitting RF frequency, and the receiving relies on two frequency conversions to complete the frequency conversion from the RF to the required receiving RF.

[0108] 4. Receiving secondary frequency conversion solution

[0109] After the first frequency conversion, the first RF frequency is Fif1=2491-2421=70MHz. Then use Fvco / 96 (about 50M) to get the second local oscillator, and mix it with Fif1 to get the second RF Fif2 of Fif1-Fvco / 96 (about 20MHz). This frequency can be handed over to digital baseband processing. Other frequency division ratios other than 96 can also be considered here, as long as Fif2 is suitable for baseband processing.

[0110] 5. Other circuit modules

[0111] It is implemented according to conventional circuits to meet the RDSS reception and transmission needs.

[0112] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A satellite short message radio frequency circuit, characterized in that: It includes a single phase-locked loop circuit, a local oscillator frequency division circuit, a receiving down-conversion circuit, a transmitting up-conversion circuit, a receiving baseband circuit, a receiving radio frequency circuit, a transmitting baseband circuit and a transmitting radio frequency circuit; The phase-locked loop circuit is coupled to an oscillator module; The local oscillator frequency division circuit is coupled to the phase-locked loop circuit, and is used to divide the VCO signal output by the oscillator module into two frequencies to obtain a receiving local oscillator signal and send it to the receiving down-conversion circuit; the local oscillator frequency division circuit is also used to divide the VCO signal output by the oscillator module into three frequencies to obtain a transmitting local oscillator signal and send it to the transmitting up-conversion circuit; The receiving down-conversion circuit is coupled to the receiving baseband circuit; the receiving down-conversion circuit mixes the receiving local oscillator signal and the signal output by the receiving radio frequency circuit to generate a receiving radio frequency signal, and sends the receiving radio frequency signal to the receiving baseband circuit; The transmitting up-conversion circuit is coupled to the transmitting radio frequency circuit; the transmitting up-conversion circuit mixes the transmitting local oscillator signal and the signal output by the transmitting baseband circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit; The local oscillator frequency division circuit includes a receiving local oscillator frequency division circuit and a receiving local oscillator frequency division circuit; Where N is a positive integer; The input end of the receiving local oscillator frequency division circuit is coupled to the phase-locked loop circuit; the receiving local oscillator frequency division circuit is used to divide the VCO signal output by the oscillator module into a first receiving local oscillator signal and send it to the receiving down-conversion circuit; The input end of the receiving local oscillator N-frequency division circuit is coupled to the phase-locked loop circuit, and the receiving local oscillator N-frequency division circuit is used to divide the vco signal output by the oscillator module into a second receiving local oscillator signal by N and send it to the receiving down-conversion circuit; The receiving down-conversion circuit comprises a first mixer and a second mixer; The first mixer is coupled to the receiving RF circuit, and the first mixer mixes the signal output by the receiving RF circuit with the first receiving local oscillator signal to generate a first receiving RF signal, and sends the first receiving RF signal to the second mixer; The second mixer is coupled to the first mixer, and mixes the first received RF signal output by the first mixer with the second received local oscillator signal to generate a second received RF signal, and sends the second received RF signal to the receiving baseband circuit.

2. A satellite short message radio frequency circuit according to claim 1, characterized in that: The oscillator module presets an operating frequency numerical range according to the frequencies of the received RF signal and the transmitted RF signal, and the operating frequency numerical range is 1.8-2.2 times the frequency of the received RF signal and 2.8-3.2 times the frequency of the transmitted RF signal, or is equal to 3 times the center frequency value of the transmitted RF signal.

3. A satellite short message radio frequency circuit according to claim 1, characterized in that: The receiving local oscillator N-dividing circuit includes a third latch, a fourth latch and a pre-div_by_N / 2 circuit, the div_by_N / 2 circuit generates N / 2-divided signals pre_p and pre_n according to the input vco signal, the CK and CKb pins of the third latch and the fourth latch are coupled to the N / 2 divider, the Y and Yb pins of the third latch are coupled to the D and Db pins of the fourth latch, and the Y and Yb pins of the fourth latch are coupled to the Db and D pins of the third latch; The value of N satisfies: ； or: ； Wherein, Fref represents the received RF signal, Fvco represents the oscillation frequency synthesized by the phase-locked loop circuit, and Fadc represents the working clock of the ADC module; when it is necessary to generate an orthogonal RF signal output, N is an even number.

4. A satellite short message radio frequency circuit according to claim 1, characterized in that: The local oscillator frequency division circuit also includes a transmitting local oscillator frequency division circuit; the transmitting local oscillator frequency division circuit is used to divide the VCO signal output by the oscillator module into a transmitting local oscillator signal; The transmitting local oscillator three-frequency circuit includes a first half-phase inverter, a second half-phase inverter and a third half-phase inverter; the clk pins of the first half-phase inverter, the second half-phase inverter and the third half-phase inverter are all coupled to the phase-locked PLL; the out pin of the first half-phase inverter is coupled to the in pin of the second half-phase inverter, the out pin of the second half-phase inverter is coupled to the in pin of the third half-phase inverter, the out pin of the third half-phase inverter is coupled to the in pin of the first half-phase inverter, and the out pin of the third half-phase inverter outputs the three-frequency local oscillator signal TxL0 of the vco signal.

5. A satellite short message radio frequency circuit according to claim 4, characterized in that: The first half-phase inverter includes a first pmos tube, a second pmos tube, a first nmos tube and a second nmos tube; the gates of the first pmos tube and the second nmos tube are both coupled to the clk pin, the gate of the second pmos tube and the gate of the first nmos tube are both coupled to the in pin, the drain of the first pmos tube is coupled to the vdd pin, the drain of the second pmos tube is coupled to the source of the first pmos tube, the source of the second pmos tube and the drain of the first nmos tube are both coupled to the out pin, the drain of the second nmos tube is coupled to the source of the first nmos tube, and the source of the second nmos tube is coupled to the vss pin.

6. A satellite short message radio frequency circuit according to claim 1, characterized in that: The phase-locked loop circuit includes a frequency division module, a frequency detection and phase detection module, a charge pump module, a loop filter module, and an oscillator module; the frequency division module divides the output signal of the oscillator module to obtain an Fdiv signal; the frequency detection and phase detection module is connected to a reference clock signal Fref and a frequency division signal Fdiv, and the output end of the frequency detection and phase detection module is coupled to the input end of the charge pump module; the output end of the charge pump module is coupled to the input end of the loop filter module, and the output end of the loop filter module is coupled to the input end of the oscillator module; the output end of the oscillator module is used as the output end of the phase-locked loop circuit to output the vco signal.

7. A frequency conversion method for a satellite short message radio frequency circuit according to any one of claims 1 to 6, characterized in that: include: The local oscillator frequency division circuit divides the VCO signal output by the oscillator module into two frequencies to obtain a receiving local oscillator signal and sends it to the receiving down-conversion circuit; The local oscillator frequency division circuit divides the VCO signal output by the oscillator module into a transmission local oscillator signal by three frequencies and sends it to the transmission up-conversion circuit; The receiving down-conversion circuit mixes the receiving local oscillator signal and the signal output by the receiving radio frequency circuit to generate a receiving radio frequency signal, and sends the receiving radio frequency signal to the receiving baseband circuit; as well as The transmitting up-conversion circuit mixes the transmitting local oscillator signal and the signal output by the transmitting baseband circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit.

Images