High-speed and high-precision phase locking method

Abstract

The invention discloses a high-speed and high-precision phase locking method, which can accurately grasp the noise level, phase deviation and attenuation coefficient of a channel through quantum channel estimation, and provides important information for subsequent processing. Signal decomposition allows accurate representation of the signal on a quantum base, laying a foundation for noise suppression (S3) and signal reconstruction. And noise suppression utilizes a quantum mechanism, so that the efficiency and accuracy of signal processing are improved. Adaptive link establishment and time-sharing signal transmission aim at different transmission requirements, and the efficiency of communication link establishment and data transmission is optimized. And link monitoring ensures the stability and reliability of communication. On the whole, the method can improve the security, stability and efficiency of quantum communication, reduces the complexity of quantum signal processing, and provides powerful technical support for practicability and commercialization of quantum communication.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a high-speed and high-precision phase-locking method. Background Art

[0002] In modern communication and electronic systems, accurate time synchronization and frequency synchronization are crucial. Traditional phase-locked loop (PLL) technology is widely used in these fields to achieve phase and frequency synchronization of signals. However, with the development of technology and the increasing requirements for synchronization accuracy, the existing technology shows the following defects: 1. Insufficient synchronization accuracy: Traditional PLL systems often cannot provide sufficient synchronization accuracy in the face of high-speed data transmission and complex electromagnetic environments, resulting in large signal synchronization errors.

[0003] 2. Slow response: In a rapidly changing signal environment, the response speed of a traditional PLL is not fast enough to quickly lock the phase, resulting in synchronization delays and data transmission errors.

[0004] 3. Low algorithm efficiency: In a multi-node synchronous network, the existing optimal clock selection algorithm is inefficient and cannot quickly and accurately select the best clock node, affecting the synchronization performance of the entire network.

[0005] Therefore, it is necessary to develop a high-speed and high-precision phase-locking method to overcome the above defects and meet the strict requirements of modern communication and electronic systems for synchronization accuracy and stability. Summary of the invention

[0006] The present invention aims to provide a high-speed and high-precision phase-locking method to solve the above-mentioned problems.

[0007] The present invention is achieved through the following technical solutions: A high-speed and high-precision phase-locking method comprises the following steps: S1: System initialization and configuration Configure the DPLL system, including the digital phase detector (DPD), digital loop filter (DLF), and digital voltage-controlled oscillator (DCO); Configure the relevant parameters of the time mode, including synchronous Ethernet and clock synchronization cascade; S2: extracting a phase reference from the input signal through a phase reference extraction circuit; S3: Use a digital phase detector to compare the phase of the input signal with the DCO output signal to generate a phase error signal; S4: Send the phase error signal to the digital loop filter to filter out high-frequency noise and generate a control voltage; S5: Control voltage to adjust the frequency of DCO to synchronize it with the frequency of input signal; S6: Use synchronous Ethernet technology to recover the clock through the physical link to achieve frequency synchronization, use the BMC algorithm to achieve time synchronization, and use SSM (synchronization status message) messages to build a synchronous network and select the optimal clock source; S7: DPLL locks the phase and frequency of the input signal through closed-loop control to achieve stable frequency tracking S8: According to the system performance requirements, adjust the DPLL parameters, including phase detector sensitivity, loop filter cutoff frequency, digital voltage-controlled oscillator gain, and integral and proportional gains of the loop filter to optimize the system performance.

[0008] The present invention realizes fast and accurate locking of the phase and frequency of the input signal through the steps of system initialization and configuration, phase reference extraction, digital phase discrimination, loop filtering, frequency synchronization adjustment, application of synchronous Ethernet technology, and time synchronization through the BMC algorithm. This method significantly improves the synchronization accuracy and response speed of the system, enhances the anti-interference ability of the system, and realizes stable frequency tracking through closed-loop control, thereby optimizing system performance. In addition, by adjusting the DPLL parameters, the method can flexibly adapt to different system performance requirements, providing an efficient and reliable synchronization solution; Preferably, in S5, the DCO adjusts its oscillation frequency according to the output signal of the phase detector to track the frequency of the input signal. At the same time, through the feedback mechanism, the output signal of the DCO is phase-synchronized with the input signal, i.e., phase-locked. The frequency adjustment of the DCO is achieved by the following formula: in, Indicates the frequency value of DCO at the current time n; is the frequency of DCO at the previous moment; represents the total gain of the loop filter; Indicates the integral value of the previous moment; is the frequency control sensitivity of the DCO; is the phase of the reference signal; is the phase of the DCO output signal.

[0009] In the present invention, the DCO adjusts its oscillation frequency according to the output signal of the phase detector, thereby achieving accurate tracking of the input signal frequency. At the same time, the phase synchronization of the DCO output signal and the input signal, i.e., phase locking, is achieved through a feedback mechanism. This frequency adjustment method improves the phase locking speed and accuracy, enhances the stability and reliability of the system, and enables the system to quickly respond to changes in the input signal, thereby maintaining signal synchronization under high-speed data transmission and complex electromagnetic environments.

[0010] Preferably, in S6, the synchronous Ethernet technology (Sync) uses a high-precision clock to send data through the Ethernet source interface, and the clock is recovered and extracted at the receiving end and used as a reference for the data code stream sent by the receiving end, wherein the link round-trip delay calculation formula is as follows: in, It is the time when the Sync message is sent from the Master and is carried in the Sync message. It is the time when the Slave receives the Sync message; It is the time when Delay_Req is sent from the Slave; It is the time point when the Master receives the Delay_Req, and is carried in the Delay_Resp message and sent back to the Slave.

[0011] The present invention provides a high-precision clock transmission and recovery method through synchronous Ethernet technology. The method accurately recovers the clock by calculating the link round-trip delay and uses it as the reference of the data code stream, thereby realizing frequency synchronization. This method improves the accuracy and stability of clock synchronization, reduces data transmission errors caused by clock errors, and enhances the reliability and efficiency of the network.

[0012] Preferably, the steps of the BMC algorithm in S6 are as follows: S6.1: Receive and authenticate Announce messages. Each clock node extracts clock source attributes by exchanging Announce messages. S6.2: Select the best message, compare the first priority, time level, time accuracy and time source of the clock in sequence, and select the best message; S6.3: Compare the best message with its own attributes to calculate the final state, which includes comparing the data sets carried in the Announce messages exchanged between the clock nodes to select the best clock and determine the state of each PTP port; S6.4: Update the port data set according to the port recommended state, where the port data set includes local clock data and information related to clock synchronization; S6.5: Determine the actual state of the port according to the port state machine to establish a clock synchronization network.

[0013] The present invention realizes the selection of the best message between clock nodes and the establishment of a clock synchronization network through the steps of the BMC algorithm. This method selects the best message by comparing the attributes of the clock nodes, thereby improving the accuracy of clock synchronization and the efficiency of the network. At the same time, by updating the port data set and determining the actual state of the port, the method optimizes the construction of the clock synchronization network and improves the stability and reliability of the network.

[0014] Preferably, in S6.2, the priority comparison rule is: If the priority (Priority 1) of clock node A is higher than that of clock node B, then A is the better clock. The time quality level comparison rule is as follows: if two clock nodes have the same priority, their time quality levels are compared, and the clock with the higher quality level is the better clock; The time precision comparison rule is: if the time levels are the same, then compare the time precision (Time Precision), and the clock with higher precision is the better clock; The rule for comparing time sources is: if all the above attributes are the same, then compare the time sources (TimeSource), and external time sources take precedence over internal time sources.

[0015] The present invention provides a fair and effective clock node comparison method by clarifying the comparison rules of priority, time level, time accuracy and time source. This method ensures that the best clock node can be selected in a multi-node synchronization network, thereby improving the synchronization accuracy and efficiency of the entire network.

[0016] Preferably, the sensitivity of the phase detector is adjusted in S8 by the following formula: in is the output voltage of the phase detector; is the phase difference; is the sensitivity of the phase detector, in V / rad; The adjustment method of the present invention enables the phase detector to respond to the phase difference more accurately, improves the synchronization accuracy and response speed of the phase-locked loop, and enhances the adaptability of the system when facing rapidly changing signals.

[0017] Preferably, the adjustment of the cutoff frequency of the loop filter in S8 is achieved by changing the resistance and capacitance values ​​of the filter, wherein the transfer function of the loop filter is: Where R and C are the resistance and capacitance values ​​of the loop filter respectively, S is a complex variable, ,in is the real part, representing the time constant, It is the imaginary part, representing the frequency. Adjusting R and C can change the cutoff frequency of the filter, thereby affecting the dynamic performance of the loop.

[0018] The present invention adjusts the cut-off frequency of the loop filter by adjusting the resistance and capacitance values ​​of the loop filter. This method optimizes the dynamic performance of the loop, improves the stability and response speed of the system, and enables the system to better adapt to different working conditions.

[0019] Preferably, the gain of the digital voltage-controlled oscillator NCO is adjusted in S8 by the following formula: in, is the gain constant of the NCO; is the frequency of the NCO; is the sampling period; is the output of the loop filter; Adjustment The frequency adjustment speed of the NCO can be changed.

[0020] The present invention provides a method for optimizing the frequency adjustment speed of a digital voltage-controlled oscillator (NCO) by adjusting the gain of the NCO. This adjustment method enables the NCO to respond to the output of the loop filter more quickly, improves the synchronization speed and accuracy of the phase-locked loop, and enhances the system's adaptability when facing rapidly changing signals. Preferably, the integral and proportional gains of the loop filter are adjusted specifically by the following formula: in, The loop filter is The output voltage at each sampling moment; is the integral gain, is the proportional gain, is the phase error; is the integral term of the phase error, which represents the cumulative sum of all phase errors from the past to the present, where Is a virtual index used to traverse from 0 to All sampling points; Adjustment and The dynamic response and steady-state error of the loop can be optimized.

[0021] The present invention optimizes the dynamic response and steady-state error of the loop by adjusting the integral and proportional gain of the loop filter. This method improves the synchronization accuracy and stability of the system, reduces data transmission errors caused by phase errors, and enhances the reliability and efficiency of the network.

[0022] Preferably, in S1, a digital phase detector (DPD) is used to compare the phases of a reference signal and a controlled signal and output a phase difference signal, a digital loop filter (DLF) is used to convert the phase difference signal into a delay signal for controlling the DCO, a digital voltage-controlled oscillator (DCO) is used to control the delay of an internal loop according to an input delay control signal to output different frequencies, the synchronous Ethernet configuration includes configuring a PTP domain, selecting or configuring a master clock (Grandmaster), and configuring a slave clock (Slave) device to receive and apply time correction, and the clock synchronization cascade configuration includes configuring cascaded PTP devices to ensure that the clock signal remains synchronized when it is passed from one device to another.

[0023] The present invention provides a comprehensive synchronization solution by configuring a digital phase detector, a digital loop filter and a digital voltage-controlled oscillator, as well as synchronous Ethernet and clock synchronization cascade. This method not only improves the synchronization accuracy and response speed, but also enhances the anti-interference ability and flexibility of the system, so that the system can adapt to different synchronization requirements and environmental conditions.

[0024] Compared with the prior art, the present invention has the following advantages and beneficial effects: The high-speed and high-precision phase-locking method proposed in the present invention significantly improves the accuracy, response speed and stability of the synchronization system. First, the system initialization and configuration phase ensures that the core components of the DPLL system - the digital phase detector DPD, the digital loop filter DLF and the digital voltage-controlled oscillator DCO - can work together efficiently, and configures the relevant parameters of the time mode, providing a solid foundation for synchronous Ethernet and clock synchronization cascade. The implementation of this method not only improves the synchronization accuracy and response speed of the system, but also enhances the anti-interference ability of the system, realizes stable frequency tracking through closed-loop control, and optimizes system performance.

[0025] In the frequency synchronization adjustment stage, the DCO adjusts its oscillation frequency according to the output signal of the phase detector, realizes accurate tracking of the input signal frequency, and realizes phase synchronization between the DCO output signal and the input signal through the feedback mechanism, that is, phase locking. This frequency adjustment method improves the phase locking speed and accuracy, enhances the stability and reliability of the system, and enables the system to quickly respond to changes in the input signal, thereby maintaining signal synchronization in high-speed data transmission and complex electromagnetic environments.

[0026] The introduction of synchronous Ethernet technology achieves frequency synchronization by calculating the round-trip delay of the link, accurately recovering the clock, and using it as the benchmark for the data stream. This method improves the accuracy and stability of clock synchronization, reduces data transmission errors caused by clock errors, and enhances the reliability and efficiency of the network.

[0027] The steps of the BMC algorithm further optimize the selection of the best message between clock nodes and the establishment of the clock synchronization network. By comparing the attributes of the clock nodes and selecting the best message, the accuracy of clock synchronization and the efficiency of the network are improved. At the same time, by updating the port data set and determining the actual status of the port, the construction of the clock synchronization network is optimized and the stability and reliability of the network are improved.

[0028] In a multi-node synchronous network, the comparison rules of priority, time level, time accuracy and time source are clarified to ensure the selection of the best clock node and improve the synchronization accuracy and efficiency of the entire network. Adjusting the phase detector sensitivity and loop filter cutoff frequency optimizes the output voltage of the phase detector and the dynamic performance of the loop, improves the synchronization accuracy and response speed of the system, and enhances the system's adaptability to rapidly changing signals.

[0029] The adjustment of the digital voltage-controlled oscillator NCO gain provides a method to optimize the NCO frequency adjustment speed, so that the NCO can respond to the output of the loop filter more quickly, improving the synchronization speed and accuracy of the phase-locked loop. Finally, by adjusting the integral and proportional gains of the loop filter, the dynamic response and steady-state error of the loop are optimized, the synchronization accuracy and stability of the system are improved, the data transmission errors caused by phase errors are reduced, and the reliability and efficiency of the network are enhanced.

[0030] In summary, the high-speed and high-precision phase-locking method of the present invention provides a comprehensive, efficient and reliable synchronization solution by comprehensively considering multiple aspects such as system initialization, frequency tracking, clock recovery, optimal clock selection, sensitivity adjustment, filter optimization and gain adjustment. This method not only improves the synchronization accuracy and response speed, but also enhances the anti-interference ability and flexibility of the system, so that the system can adapt to different synchronization requirements and environmental conditions, and provides strong technical support for the high-speed and high-precision synchronization requirements in modern communication and electronic systems. DETAILED DESCRIPTION

[0031] The technical solution of the present invention is further described in detail below, but the protection scope of the present invention is not limited to the following.

[0032] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments.

[0033] Therefore, the following detailed description of the embodiments of the present invention is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention. It should be noted that relational terms such as the terms "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0034] Moreover, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a list of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus. In the absence of more restrictions, an element defined by the phrase "comprises a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0035] The features and performance of the present invention are further described in detail below in conjunction with the embodiments.

[0036] Embodiment: A high-speed and high-precision phase-locking method comprises the following steps: S1: System initialization and configuration Configure the DPLL system, including the digital phase detector (DPD), digital loop filter (DLF), and digital voltage-controlled oscillator (DCO); Configure the relevant parameters of the time mode, including synchronous Ethernet and clock synchronization cascade; S2: extracting a phase reference from the input signal through a phase reference extraction circuit; S3: Use a digital phase detector to compare the phase of the input signal with the DCO output signal to generate a phase error signal; S4: Send the phase error signal to the digital loop filter to filter out high-frequency noise and generate a control voltage; S5: Control voltage to adjust the frequency of DCO to synchronize it with the frequency of input signal; S6: Use synchronous Ethernet technology to recover the clock through the physical link to achieve frequency synchronization, use the BMC algorithm to achieve time synchronization, and use SSM (synchronization status message) messages to build a synchronous network and select the optimal clock source; S7: DPLL locks the phase and frequency of the input signal through closed-loop control to achieve stable frequency tracking; S8: According to the system performance requirements, adjust the DPLL parameters, including phase detector sensitivity, loop filter cutoff frequency, digital voltage-controlled oscillator gain, and integral and proportional gains of the loop filter to optimize the system performance.

[0037] In this embodiment, the DPD uses a phase difference detection algorithm, specifically a cross-correlation method or a phase-locked loop method, to compare the phase of the input signal with the DCO output signal, and output a phase difference signal; In this embodiment, the DLF is designed as a low-pass filter to filter out high-frequency noise and smooth the phase error signal to generate a control voltage.

[0038] The present invention realizes fast and accurate locking of the phase and frequency of the input signal through the steps of system initialization and configuration, phase reference extraction, digital phase discrimination, loop filtering, frequency synchronization adjustment, application of synchronous Ethernet technology, and time synchronization through the BMC algorithm. This method significantly improves the synchronization accuracy and response speed of the system, enhances the anti-interference ability of the system, and realizes stable frequency tracking through closed-loop control, thereby optimizing system performance. In addition, by adjusting the DPLL parameters, the method can flexibly adapt to different system performance requirements, providing an efficient and reliable synchronization solution; Preferably, in S5, the DCO adjusts its oscillation frequency according to the output signal of the phase detector to track the frequency of the input signal. At the same time, through the feedback mechanism, the output signal of the DCO is phase-synchronized with the input signal, i.e., phase-locked. The frequency adjustment of the DCO is achieved by the following formula: in, Indicates the frequency value of DCO at the current time n; is the frequency of DCO at the previous moment; represents the total gain of the loop filter; Indicates the integral value of the previous moment; is the frequency control sensitivity of the DCO; is the phase of the reference signal; is the phase of the DCO output signal.

[0039] In the present invention, the DCO adjusts its oscillation frequency according to the output signal of the phase detector, thereby achieving accurate tracking of the input signal frequency. At the same time, the phase synchronization of the DCO output signal and the input signal, i.e., phase locking, is achieved through a feedback mechanism. This frequency adjustment method improves the phase locking speed and accuracy, enhances the stability and reliability of the system, and enables the system to quickly respond to changes in the input signal, thereby maintaining signal synchronization under high-speed data transmission and complex electromagnetic environments.

[0040] Preferably, in S6, the synchronous Ethernet technology (Sync) uses a high-precision clock to send data through the Ethernet source interface, and the clock is recovered and extracted at the receiving end and used as a reference for the data code stream sent by the receiving end, wherein the link round-trip delay calculation formula is as follows: in, It is the time when the Sync message is sent from the Master and is carried in the Sync message. It is the time when the Slave receives the Sync message; It is the time when Delay_Req is sent from the Slave; It is the time point when the Master receives the Delay_Req, and is carried in the Delay_Resp message and sent back to the Slave.

[0041] In this embodiment, "Sync" refers to the synchronous Ethernet technology, and through this technology, the source interface can use a high-precision clock to synchronously send data; The present invention provides a high-precision clock transmission and recovery method through synchronous Ethernet technology. The method accurately recovers the clock by calculating the link round-trip delay and uses it as the reference of the data code stream, thereby realizing frequency synchronization. This method improves the accuracy and stability of clock synchronization, reduces data transmission errors caused by clock errors, and enhances the reliability and efficiency of the network.

[0042] Preferably, the steps of the BMC algorithm in S6 are as follows: S6.1: Receive and authenticate Announce messages. Each clock node extracts clock source attributes by exchanging Announce messages. S6.2: Select the best message, compare the first priority, time level, time accuracy and time source of the clock in sequence, and select the best message; S6.3: Compare the best message with its own attributes to calculate the final state, which includes comparing the data sets carried in the Announce messages exchanged between the clock nodes to select the best clock and determine the state of each PTP port; S6.4: Update the port data set according to the port recommended state, where the port data set includes local clock data and information related to clock synchronization; S6.5: Determine the actual state of the port according to the port state machine to establish a clock synchronization network.

[0043] The present invention realizes the selection of the best message between clock nodes and the establishment of a clock synchronization network through the steps of the BMC algorithm. This method selects the best message by comparing the attributes of the clock nodes, thereby improving the accuracy of clock synchronization and the efficiency of the network. At the same time, by updating the port data set and determining the actual state of the port, the method optimizes the construction of the clock synchronization network and improves the stability and reliability of the network.

[0044] Preferably, in S6.2, the priority comparison rule is: If the priority (Priority 1) of clock node A is higher than that of clock node B, then A is the better clock. The time quality level comparison rule is as follows: if two clock nodes have the same priority, their time quality levels are compared, and the clock with the higher quality level is the better clock; The time precision comparison rule is: if the time levels are the same, then compare the time precision (Time Precision), and the clock with higher precision is the better clock; The rule for comparing time sources is: if all the above attributes are the same, then compare the time sources (TimeSource), and external time sources take precedence over internal time sources.

[0045] The present invention provides a fair and effective clock node comparison method by clarifying the comparison rules of priority, time level, time accuracy and time source. This method ensures that the best clock node can be selected in a multi-node synchronization network, thereby improving the synchronization accuracy and efficiency of the entire network.

[0046] Preferably, the sensitivity of the phase detector is adjusted in S8 by the following formula: in is the output voltage of the phase detector; is the phase difference; is the sensitivity of the phase detector, in V / rad; The adjustment method of the present invention enables the phase detector to respond to the phase difference more accurately, improves the synchronization accuracy and response speed of the phase-locked loop, and enhances the adaptability of the system when facing rapidly changing signals.

[0047] Preferably, the adjustment of the cutoff frequency of the loop filter in S8 is achieved by changing the resistance and capacitance values ​​of the filter, wherein the transfer function of the loop filter is: Where R and C are the resistance and capacitance values ​​of the loop filter respectively, S is a complex variable, ,in is the real part, representing the time constant, It is the imaginary part, representing the frequency. Adjusting R and C can change the cutoff frequency of the filter, thereby affecting the dynamic performance of the loop.

[0048] The present invention adjusts the cut-off frequency of the loop filter by adjusting the resistance and capacitance values ​​of the loop filter. This method optimizes the dynamic performance of the loop, improves the stability and response speed of the system, and enables the system to better adapt to different working conditions.

[0049] Preferably, the gain of the digital voltage-controlled oscillator NCO is adjusted in S8 by the following formula: in, is the gain constant of the NCO; is the frequency of the NCO; is the sampling period; is the output of the loop filter; Adjustment The frequency adjustment speed of the NCO can be changed.

[0050] The present invention provides a method for optimizing the frequency adjustment speed of a digital voltage-controlled oscillator (NCO) by adjusting the gain of the NCO. This adjustment method enables the NCO to respond to the output of the loop filter more quickly, improves the synchronization speed and accuracy of the phase-locked loop, and enhances the system's adaptability when facing rapidly changing signals. Preferably, the integral and proportional gains of the loop filter are adjusted specifically by the following formula: in, The loop filter is The output voltage at each sampling moment; is the integral gain, is the proportional gain, is the phase error; is the integral term of the phase error, which represents the cumulative sum of all phase errors from the past to the present, where Is a virtual index used to traverse from 0 to All sampling points; Adjustment and The dynamic response and steady-state error of the loop can be optimized.

[0051] The present invention optimizes the dynamic response and steady-state error of the loop by adjusting the integral and proportional gain of the loop filter. This method improves the synchronization accuracy and stability of the system, reduces data transmission errors caused by phase errors, and enhances the reliability and efficiency of the network.

[0052] Preferably, in S1, a digital phase detector (DPD) is used to compare the phases of a reference signal and a controlled signal and output a phase difference signal, a digital loop filter (DLF) is used to convert the phase difference signal into a delay signal for controlling the DCO, a digital voltage-controlled oscillator (DCO) is used to control the delay of an internal loop according to an input delay control signal to output different frequencies, the synchronous Ethernet configuration includes configuring a PTP domain, selecting or configuring a master clock (Grandmaster), and configuring a slave clock (Slave) device to receive and apply time correction, and the clock synchronization cascade configuration includes configuring cascaded PTP devices to ensure that the clock signal remains synchronized when it is passed from one device to another.

[0053] In this embodiment, the sensitivity of the phase detector refers to the degree of response of the phase detector to the phase change of the input signal. Adjusting the sensitivity of the phase detector usually involves changing the gain setting of the phase detector or adjusting the parameters of its internal circuit. In a digital phase detector, it is specifically implemented through a software algorithm; In this embodiment, increasing the sensitivity of the phase detector can make the DPLL more sensitive to the phase change of the input signal, thereby quickly responding to the phase change and improving the phase locking speed; In this embodiment, the cutoff frequency of the loop filter determines the cutoff point of the filter for the signal, that is, the frequency at which the filter begins to significantly attenuate the signal. In a digital loop filter, this is achieved by changing the digital parameters of the filter; In this embodiment, increasing the cutoff frequency can allow the loop filter to pass more high-frequency components, thereby improving the response speed of the system; In this embodiment, the gain of a digital voltage-controlled oscillator (DCO) refers to the proportional relationship between the input control signal and the output frequency change. The DCO gain is adjusted by changing the control algorithm parameters of the DCO; In this embodiment, increasing the DCO gain can make the DCO more responsive to the control signal, thereby quickly adjusting the output frequency to match the input signal frequency; The present invention provides a comprehensive synchronization solution by configuring a digital phase detector, a digital loop filter and a digital voltage-controlled oscillator, as well as synchronous Ethernet and clock synchronization cascade. This method not only improves the synchronization accuracy and response speed, but also enhances the anti-interference ability and flexibility of the system, so that the system can adapt to different synchronization requirements and environmental conditions.

[0054] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A high-speed and high-precision phase-locking method, characterized in that: The steps include: S1: system initialization and configuration; Configure the DPLL system, including a digital phase detector DPD, a digital loop filter DLF and a digital voltage-controlled oscillator DCO; Configure the relevant parameters of the time mode, including synchronous Ethernet and clock synchronization cascade; S2: extracting a phase reference from the input signal through a phase reference extraction circuit; S3: Use a digital phase detector to compare the phase of the input signal with the DCO output signal to generate a phase error signal; S4: Send the phase error signal to the digital loop filter to filter out high-frequency noise and generate a control voltage; S5: Control voltage to adjust the frequency of DCO to synchronize it with the frequency of input signal; S6: Use synchronous Ethernet technology to recover the clock through the physical link to achieve frequency synchronization, use the BMC algorithm to achieve time synchronization, and use the SSM synchronization status information message to build a synchronous network and select the optimal clock source; S7: DPLL locks the phase and frequency of the input signal through closed-loop control to achieve stable frequency tracking; S8: According to the system performance requirements, adjust the DPLL parameters, including phase detector sensitivity, loop filter cutoff frequency, digital voltage-controlled oscillator gain, and integral and proportional gains of the loop filter to optimize the system performance.

2. A high-speed and high-precision phase-locking method according to claim 1, characterized in that: In S5, the DCO adjusts its oscillation frequency according to the output signal of the phase detector to track the frequency of the input signal. At the same time, through the feedback mechanism, the output signal of the DCO is phase-synchronized with the input signal, that is, phase-locked. The frequency adjustment of the DCO is achieved by the following formula: in, Indicates the frequency value of DCO at the current time n; is the frequency of DCO at the previous moment; represents the total gain of the loop filter; Indicates the integral value of the previous moment; is the frequency control sensitivity of the DCO; is the phase of the reference signal; is the phase of the DCO output signal.

3. A high-speed and high-precision phase-locking method according to claim 1, characterized in that: In S6, the synchronous Ethernet technology Sync uses a high-precision clock to send data through the Ethernet source interface. The clock is recovered and extracted at the receiving end and used as the basis for the data stream sent by the receiving end. The round-trip delay calculation formula of the link is as follows: in, It is the time when the Sync message is sent from the Master and is carried in the Sync message. It is the time when the Slave receives the Sync message; It is the time when Delay_Req is sent from the Slave; It is the time point when the Master receives the Delay_Req, and is carried in the Delay_Resp message and sent back to the Slave.

4. A high-speed and high-precision phase-locking method according to claim 1, characterized in that: The steps of the BMC algorithm in S6 are as follows: S6.1: Receive and authenticate Announce messages. Each clock node extracts clock source attributes by exchanging Announce messages. S6.2: Select the best message, compare the first priority, time level, time accuracy and time source of the clock in sequence, and select the best message; S6.3: Compare the best message with its own attributes to calculate the final state, which includes comparing the data sets carried in the Announce messages exchanged between the clock nodes to select the best clock and determine the state of each PTP port; S6.4: Update the port data set according to the port recommended state, where the port data set includes local clock data and information related to clock synchronization; S6.5: Determine the actual state of the port according to the port state machine to establish a clock synchronization network.

5. A high-speed and high-precision phase-locking method according to claim 4, characterized in that: In S6.2, the rules for priority comparison are: If the priority of clock node A is higher than that of clock node B, then A is the better clock; The time level comparison rule is: if two clock nodes have the same priority, their time levels are compared, and the clock with the higher level is the more preferred clock; The time accuracy comparison rule is: if the time levels are the same, then the time accuracy is compared, and the clock with higher accuracy is the better clock; The rules for comparing time sources are: If all the above attributes are the same, the time sources are compared, and external time sources take precedence over internal time sources.

6. A high-speed and high-precision phase-locking method according to claim 1, characterized in that: The sensitivity of the phase detector in S8 is adjusted by the following formula: in is the output voltage of the phase detector; is the phase difference; is the sensitivity of the phase detector, and its unit is V / rad.

7. A high-speed and high-precision phase-locking method according to claim 1, characterized in that: In S8, the cutoff frequency of the loop filter is adjusted by changing the resistance and capacitance values ​​of the filter, where the transfer function of the loop filter is: Where R and C are the resistance and capacitance values ​​of the loop filter respectively, S is a complex variable, ,in is the real part, representing the time constant, It is the imaginary part, representing the frequency. Adjusting R and C can change the cutoff frequency of the filter, thereby affecting the dynamic performance of the loop.

8. A high-speed and high-precision phase-locking method according to claim 1, characterized in that: The digital voltage-controlled oscillator NCO gain is adjusted in S8 by the following formula: in, is the gain constant of the NCO; is the frequency of the NCO; is the sampling period; is the output of the loop filter; Adjustment The frequency adjustment speed of the NCO can be changed.

9. A high-speed and high-precision phase-locking method according to claim 1, characterized in that: The integral and proportional gains of the loop filter are adjusted by the following formula: in, The loop filter is The output voltage at each sampling moment; is the integral gain, is the proportional gain, is the phase error; is the integral term of the phase error, which represents the cumulative sum of all phase errors from the past to the present, where Is a virtual index used to traverse from 0 to All sampling points; Adjustment and The dynamic response and steady-state error of the loop can be optimized.

10. A high-speed and high-precision phase-locking method according to claim 1, characterized in that: In S1, the digital phase detector is used to compare the phase of the reference signal and the controlled signal and output a phase difference signal. The digital loop filter converts the phase difference signal into a delay signal to control the digital voltage-controlled oscillator. The digital voltage-controlled oscillator controls the delay of the internal loop according to the input delay control signal to output different frequencies. The synchronous Ethernet configuration includes configuring the PTP domain, selecting or configuring the master clock, and configuring the slave clock device to receive and apply time correction. The clock synchronization cascade configuration includes configuring the cascaded PTP devices to ensure that the clock signal remains synchronized when it is passed from one device to another.

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