Integrated circuit, data routing method, system on chip and electronic equipment

Abstract

The invention provides an integrated circuit, a data routing method, a system on chip and electronic equipment, and is applied to the technical field of computers, the integrated circuit comprises a plurality of bare chips which are stacked in the vertical direction, each bare chip comprises a plurality of routing nodes, and the routing nodes in the same bare chip are communicated with one another. According to the integrated circuit provided by the invention, the routing nodes in the same bare chip are communicated with each other, and different bare chips are communicated with each other through the end routing nodes on the first side and the second side, so that the routing nodes on the first side and the end routing nodes on the second side of the bare chips are communicated with each other, and the routing nodes on the first side and the second side of the bare chips are communicated with each other. Therefore, mutual communication between the bare chips in the integrated circuit and between the routing nodes in each bare chip is realized, efficient interconnection communication between the bare chips in the 3D chip is ensured, and actual application requirements are met.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an integrated circuit, a data routing method, a system on a chip, and an electronic device. Background Art

[0002] With the advent of the post-Moore era, 3D chip technology has become one of the important directions for further improving chip performance. In the prior art, a 3D chip integrates multiple dies, which are stacked in a vertical direction to increase the number of transistors integrated per unit area.

[0003] However, in the actual design and manufacturing process of 3D chips, how to achieve efficient interconnection and communication between the dies and make the 3D chip more powerful through the mutual cooperation between the dies has always been one of the problems that technical personnel in this field need to solve urgently. Summary of the invention

[0004] In view of this, the present application is committed to providing an integrated circuit, a data routing method, a system on chip and an electronic device to achieve efficient interconnection and communication between the bare chips inside the 3D chip to meet practical application needs.

[0005] In a first aspect, the present application provides an integrated circuit, comprising: a plurality of bare chips, each of the bare chips comprising a plurality of routing nodes, wherein:

[0006] The dies are stacked in a vertical direction;

[0007] The routing nodes within the same die are interconnected;

[0008] The end routing nodes on the first side of each of the bare chips are connected to each other, and the end routing node is a routing node located at the end of any routing path in the bare chip to which it belongs;

[0009] The end routing nodes on the second side of each of the bare chips are connected to each other, and the second side is opposite to the first side.

[0010] In an optional embodiment, the end routing nodes on the first side of each of the bare chips are interconnected in a grid structure;

[0011] The end routing nodes on the second side of each of the bare chips are interconnected in a grid structure.

[0012] In an optional implementation, in any two adjacent dies, two end routing nodes located on the first side or the second side are connected through a through silicon via TSV.

[0013] In an optional implementation, routing nodes within the same die are connected in a grid structure.

[0014] In an optional implementation, routing nodes within the same die are interconnected via metal lines.

[0015] In an optional implementation, the plurality of dies include a first die located at a top layer, a second die located at a bottom layer, and at least one third die located between the first die and the second die.

[0016] In an optional implementation, the end routing nodes of the first die and the second die include one routing port for connecting to other die, and the end routing node of the third die includes two routing ports for connecting to other die.

[0017] In a second aspect, the present application provides a data routing method, applied to the integrated circuit as described in any one of the first aspect of the present application, the method comprising:

[0018] Get the source routing node and the destination routing node;

[0019] Determining whether the source routing node and the destination routing node belong to the same die;

[0020] If the source routing node and the destination routing node belong to different dies, determining a target routing path for inter-die routing;

[0021] Transmitting data to a target die to which the destination routing node belongs according to the target routing path;

[0022] The data is transmitted to the destination routing node according to the preset on-chip routing strategy.

[0023] In an optional embodiment, the end routing nodes on the first side of each bare die of the integrated circuit are interconnected, and the end routing nodes on the second side are interconnected, and the second side is opposite to the first side;

[0024] The determining of a target routing path for inter-die routing includes:

[0025] Determine a first routing path with the shortest path when inter-die routing is performed through the end routing node of the first side;

[0026] Determine a second routing path with the shortest path when inter-die routing is performed through the end routing node of the second side;

[0027] The first routing path or the second routing path is determined as a target routing path for inter-die routing.

[0028] In an optional embodiment, the end routing nodes of any two adjacent bare chips in the integrated circuit are interconnected through a through silicon via TSV;

[0029] Determining the first routing path or the second routing path as a target routing path for inter-die routing includes:

[0030] respectively determining whether the TSV included in the first routing path and the TSV included in the second routing path are faulty;

[0031] If the TSV of the first routing path or the TSV of the second routing path fails, determine a routing path with a normal TSV among the first routing path and the second routing path as a target routing path;

[0032] If the TSV of the first routing path and the TSV of the second routing path are both normal, a routing path with the shortest path between the first routing path and the second routing path is determined as a target routing path.

[0033] In an optional implementation, transmitting data to a target die to which the destination routing node belongs according to the target routing path includes:

[0034] The data is transmitted to a target end routing node of a target die to which the destination routing node belongs according to the target routing path, wherein the target end routing node is an end routing node to which the TSV of the target routing path is connected in the target die.

[0035] In an optional implementation manner, determining whether the source routing node and the destination routing node belong to the same die includes:

[0036] Respectively obtaining a node identifier of the source routing node and a node identifier of the destination routing node;

[0037] If the node identifier of the source routing node and the node identifier of the destination routing node indicate the same die, determining that the source routing node and the destination routing node belong to the same die;

[0038] If the node identifier of the source routing node and the node identifier of the destination routing node indicate different dies, it is determined that the source routing node and the destination routing node belong to different dies.

[0039] In an optional implementation manner, determining whether the source routing node and the destination routing node belong to the same die includes:

[0040] Creating a three-dimensional rectangular coordinate system, wherein a Z axis of the three-dimensional rectangular coordinate system is parallel to a stacking direction of each die in the integrated circuit;

[0041] Respectively obtain the coordinate values ​​of the source routing node and the destination routing node in the Z-axis direction;

[0042] If the coordinate values ​​of the source routing node and the destination routing node in the Z-axis direction are the same, it is determined that the source routing node and the destination routing node belong to the same die;

[0043] If the coordinate values ​​of the source routing node and the destination routing node in the Z-axis direction are different, it is determined that the source routing node and the destination routing node belong to different dies.

[0044] In an optional implementation manner, the data routing method provided in the second aspect of the present application further includes:

[0045] If the source routing node and the destination routing node belong to the same bare chip, the data is transmitted to the destination routing node according to a preset on-chip routing strategy.

[0046] In an optional implementation manner, transmitting the data to the destination routing node according to a preset on-chip routing strategy includes:

[0047] The data is transmitted to the destination routing node according to a preset static routing strategy or a preset dynamic routing strategy.

[0048] In a third aspect, the present application provides a system on chip, comprising an integrated circuit as described in any one of the first aspect of the present application.

[0049] In an optional implementation, the system on chip provided in the third aspect of the present application further includes: a routing controller, wherein the routing controller is configured to execute the data routing method as described in any one of the second aspect of the present application.

[0050] In a fourth aspect, the present application provides an electronic device, comprising a system on chip as described in any one of the third aspects of the present application.

[0051] Based on the above content, the integrated circuit provided by the present application includes multiple bare chips stacked in the vertical direction, each bare chip includes multiple routing nodes and the routing nodes in the same bare chip are interconnected. Furthermore, the end routing nodes on the first side of each bare chip are interconnected, and the end routing nodes on the second side of each bare chip are interconnected. In the integrated circuit provided by the present application, the routing nodes in the same bare chip are interconnected, and different bare chips are connected through the end routing nodes on the first side and the second side, thereby realizing mutual connectivity between the bare chips inside the integrated circuit and between the routing nodes inside each bare chip, ensuring efficient interconnection and communication between the bare chips inside the 3D chip, and meeting actual application needs.

[0052] Furthermore, when realizing interconnection between different bare chips, only the end routing nodes of the first side and the second side are interconnected, and the routing nodes inside the bare chip are not interconnected with the routing nodes of other bare chips. Such a setting can ensure that the bare chips are interconnected in the simplest way, thereby reducing the impact of signal crosstalk caused by bare chip interconnection, improving the reliability of data transmission, and at the same time reducing the overall cost of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 It is a structural block diagram of an integrated circuit provided by this application.

[0055] Figure 2 This is a schematic diagram of the connection relationship of routing nodes in an integrated circuit provided by the present application.

[0056] Figure 3 It is a structural block diagram of another integrated circuit provided by the present application.

[0057] Figure 4 This is a flow chart of a data routing method provided by this application.

[0058] Figure 5 This is a schematic diagram of the connection relationship of routing nodes in another integrated circuit provided by the present application.

[0059] Figure 6 This is a flow chart of another data routing method provided by the present application. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0061] In order to solve the problem of efficient interconnection and communication between different dies in the actual design and manufacturing process of 3D chips, and to enable the 3D chip to achieve powerful functions through the cooperation of the dies, the present application provides an integrated circuit, in which routing nodes in the same die are interconnected, and different dies are connected through the end routing nodes on the first side and the second side, thereby achieving interconnection between the dies inside the integrated circuit and between the routing nodes inside each die, ensuring efficient interconnection and communication between the dies inside the 3D chip, and meeting actual application needs.

[0062] See also Figure 1 As shown, the integrated circuit provided by the present application includes: a plurality of bare chips. First of all, it should be noted that the plurality mentioned in the present application specifically refers to two or more bare chips. Figure 1 In the illustrated embodiment, the integrated circuit includes four bare dies, namely, die0, die1, die2, die3 and die4. Of course, in practical applications, the integrated circuit may also include other numbers of bare dies, which are not listed one by one here.

[0063] The dies included in the integrated circuit are stacked in the vertical direction. In practical applications, the dies should be arranged so that the central axes of the planes to which the dies belong in the vertical direction coincide with each other, thereby reducing the volume of the package.

[0064] In an optional embodiment, the integrated circuit includes more than two bare chips. In this case, the bare chips included in the integrated circuit can be further subdivided into a first bare chip located at the top layer, a second bare chip located at the bottom layer, and at least one third bare chip located between the first bare chip and the second bare chip. Figure 1 As shown in the example, die4 is the top die, die0 is the bottom die, and die1, die2 and die3 are the third die. It should be noted that in actual applications, the functions implemented by the dies included in the integrated circuit can be the same or different, and this application does not limit this.

[0065] It can be understood that if the integrated circuit includes two dies, in this case, it can be regarded as the integrated circuit only including the top die and the bottom die, and does not include the third die.

[0066] Furthermore, in the integrated circuit provided by the present application, each bare chip includes a plurality of routing nodes. Figure 1In the example shown, the routing nodes included in each lock chip are shown as a rectangular block. In practical applications, routing nodes refer to routing modules or routers used to implement data transmission in integrated circuits, and are usually key components of on-chip networks. As for the specific implementation of routing nodes, reference can be made to related technical implementations, and this application does not limit this. As a preferred embodiment, the functions of each bare chip are the same or similar, and the number and arrangement of routing nodes set on each bare chip are the same. Figure 1 As shown in the figure as an example, the routing nodes in any bare chip are arranged in a grid format, and when the bare chips are stacked in sequence in the vertical direction, a corresponding routing node matrix can be obtained.

[0067] In practical applications, as a key component of the on-chip network of any die, the routing nodes in the same die are interconnected. As a preferred implementation, and also to facilitate the construction of the aforementioned routing node matrix, the routing nodes in the same die are interconnected in a mesh structure.

[0068] For ease of expression, we establish Figure 1 In the three-dimensional rectangular coordinate system shown, in practical applications, any position of the integrated circuit can be used as the origin of the coordinate system. The Z axis of the coordinate system is parallel to the vertical stacking direction of each die from bottom to top, the X axis of the coordinate system extends in one direction of the integrated circuit, and the Y axis of the coordinate system extends in another direction of the integrated circuit. Based on this, the planes where the dies are located are parallel to the plane formed by the X axis and the Y axis. In any die, multiple routing nodes are arranged in the X axis direction and the Y axis direction respectively. The routing nodes in the X axis direction are interconnected, and the routing nodes in the Y axis direction are interconnected, that is, a mesh connection architecture is formed.

[0069] In an optional implementation, the routing nodes in the same die are connected to each other through metal wires. As for the specific implementation method of connecting the routing nodes in the same die through metal wires, reference can be made to the relevant technical implementation, which will not be described in detail here. Of course, the routing nodes in the same die can also be interconnected in other ways, which also fall within the scope of protection of this application without exceeding the core idea of ​​this application.

[0070] In this application, the routing node at the end of any routing path in each die is defined as an end routing node. Figure 1As shown, die4 includes three routing paths in the X-axis direction and three routing paths in the Y-axis direction. Based on this, the routing node at the end of each routing path is the end routing node. In other words, the end routing node mentioned in this application is the outermost routing node among the routing nodes included in the die. In the same die, the end routing node can only be connected to two or three other routing nodes, while other routing nodes need to be connected to four routing nodes. Taking die4 as an example, the routing node in the middle of die4 needs to be connected to four end routing nodes at the same time.

[0071] Based on the above content, in the integrated circuit provided by the present application, the end routing nodes on the first side of each bare chip are interconnected, and the end routing nodes on the second side of each bare chip are interconnected, wherein the second side is opposite to the first side. Figure 1 Taking the scenario shown as an example, in the X-axis direction, the left side of each die (close to the origin of the coordinate system) is the first side, and the right side of each die (away from the origin of the coordinate system) is the second side. In another embodiment, in the Y-axis direction, the front side of each die (close to the origin of the coordinate system) is the first side, and the back side of each die (away from the origin of the coordinate system) is the second side. It can be understood that if the aforementioned routing node matrix is ​​regarded as a rectangular parallelepiped structure, the top surface of the rectangular parallelepiped is the plane corresponding to die4, and the bottom surface of the rectangular parallelepiped is the plane corresponding to die0. Based on this, in Figure 1 In the illustrated scenario, the left side of the cuboid is the first side, and the right side of the cuboid is the second side. Correspondingly, in another embodiment, the front side of the cuboid is the first side, and the back side of the cuboid is the second side.

[0072] It should be noted that the first side and the second side mentioned in the above content are only exemplary illustrations, and the first side and the second side can be interchanged. For example, in the X-axis direction, the left side of each bare chip (close to the origin of the coordinate system) is the second side, and the right side of each bare chip (away from the origin of the coordinate system) is the first side.

[0073] Based on the above definition, the integrated circuit provided in this embodiment connects the end routing nodes located on the first side of each bare chip, and at the same time, connects the end routing nodes located on the second side of each bare chip. The remaining routing nodes inside each bare chip are only connected to the routing nodes belonging to the same bare chip, and are not connected to the routing nodes of other bare chips. In other words, different bare chips are connected only through the end routing nodes on both sides.

[0074] In an optional embodiment, referring to the connection method between routing nodes inside any bare chip, the end routing nodes on the first side of each bare chip are interconnected according to a grid structure, and correspondingly, the end routing nodes on the second side of each bare chip are also interconnected according to a grid structure.

[0075] For details, see Figure 2 , Figure 2 FIG. 1 is a schematic diagram showing the connection relationship between the routing nodes in the integrated circuit provided by the present application. Figure 2 Each dot shown in the figure represents a routing node. The routing nodes belonging to the same bare chip are interconnected in a grid structure. Still in the X-axis direction, the left side of each bare chip is the first side, and the right side of each bare chip is the second side. The end routing nodes on the first side of each bare chip are interconnected according to the grid structure, and correspondingly, the end routing nodes on the second side of each bare chip are also interconnected according to the grid structure.

[0076] From another perspective, in the integrated circuit provided by the present application, the routing nodes between adjacent dies are connected to each other in a ring structure. Using the aforementioned three-dimensional rectangular coordinate system, the routing nodes in each plane parallel to the XY plane respectively form a grid structure on the corresponding die, and each row of routing nodes in the X-axis direction and the same row of routing nodes of the upper and lower adjacent dies together form a ring structure on the XZ plane. Figure 2 Taking the scenario shown as an example, routing nodes A, B, C, and D are the four routing nodes on die1. These four routing nodes and other routing nodes in the same plane together constitute the mesh topology of die1. Correspondingly, routing nodes E, F, G, and H are the four routing nodes on die2. These four routing nodes and other routing nodes in the same plane together constitute the mesh topology of die2. The end routing node A located on the first side is interconnected with the end routing node E, and the end routing node D located on the second side is interconnected with the end routing node H. Based on this, the eight routing nodes A, B, C, D, E, F, G, and H constitute a ring structure between adjacent die1 and die2. By analogy, there are three other ring interconnection structures between die1 and die2 in the Y-axis direction, and any other two adjacent dies also include similar ring interconnection structures, which will not be described in detail here.

[0077] In an optional implementation, in any two adjacent bare chips, two end routing nodes on the first side or the second side are connected via a TSV (Through Silicon Via).

[0078] It is understandable that, in order to realize the above connection architecture, each routing node, especially the end routing node, needs to be provided with a corresponding routing port. In the case where the integrated circuit includes a first die, a second die, and at least one third die, the end routing nodes of the first die and the second die are respectively provided with a routing port for connecting to the end routing nodes of other die. Since the third die needs to connect to the end routing nodes in two directions, the end routing nodes of each third die include two routing ports for connecting to other die. Correspondingly, in the case where the integrated circuit includes only a first die and a second die, the end routing nodes of the first die and the second die are respectively provided with a routing port.

[0079] Combination Figure 1 In the example shown, the routing port of the end routing node in the first die faces downward, the routing port of the end routing node in the second die faces upward, and the two routing ports of the end routing node in the third die, one of which faces upward and the other faces downward.

[0080] Based on the above content, it can be seen that in the integrated circuit provided by this embodiment, the routing nodes in each bare chip are interconnected to form an on-chip network of the corresponding bare chip, and the on-chip network of each bare chip is relatively independent. Therefore, any bare chip in the integrated circuit provided by this application can be independently designed and fully functional, and any bare chip can operate independently.

[0081] To summarize, in the integrated circuit provided by the present application, the routing nodes within the same bare chip are interconnected, and different bare chips are connected through the end routing nodes on the first side and the second side, thereby realizing interconnection between the bare chips inside the integrated circuit and between the routing nodes inside each bare chip, ensuring efficient interconnection and communication between the bare chips inside the 3D chip and meeting actual application needs.

[0082] Furthermore, when interconnecting different bare chips, only the end routing nodes of the first side and the second side are interconnected, and the routing nodes inside the bare chip are not interconnected with the routing nodes of other bare chips. This arrangement can ensure that the bare chips are interconnected in the simplest way, saving a large number of TSVs. In addition, since the number of interconnection paths is effectively reduced, the distance between the interconnection paths becomes larger, and the coupling capacitance becomes smaller, thereby reducing the impact of signal crosstalk caused by bare chip interconnection, improving the reliability of data transmission, and reducing the overall cost of the integrated circuit. The space saved by not setting up interconnection TSVs inside the bare chip can also be used to set up other connection paths, which helps to improve the overall space utilization of the integrated circuit and the integration of components, and is beneficial to the volume control of the integrated circuit.

[0083] During the integrated circuit design stage, any bare die can be designed independently, and the on-chip network architecture of the bare die itself will not be affected in any way. Each bare die can be used individually. The simple interconnection structure also helps to shorten the timing verification cycle, thereby shortening the overall design cycle of the integrated circuit, which is of great significance to improving the efficiency of integrated circuit design.

[0084] Furthermore, in practical applications, each bare chip in the integrated circuit is also provided with a plurality of functional units for realizing different preset functions. Figure 3 As shown, as an optional implementation, each functional unit is connected to a corresponding routing node, mounted on the on-chip network through the corresponding routing node, and then based on the interconnection structure provided by the present application, mutual communication between different functional units in the same bare chip is realized, and mutual communication between different bare chips and different functional units can also be realized, so that the integrated circuit becomes a complete and reliably interconnected whole, thereby providing users with a powerful and rich integrated circuit.

[0085] Based on the integrated circuit provided in the aforementioned embodiment, the present application also provides a data routing method, which is applied to a control module that can perform data routing process control based on the integrated circuit provided in the present application. In a possible implementation, a routing controller can be configured in the integrated circuit provided in the present application, and the data routing method provided in the present application is executed by the routing controller. Of course, the data routing method provided in the present application can also be executed by other functional modules in the integrated circuit. These will not be described in detail here one by one. Without exceeding the core idea of ​​the present application, they also fall within the scope of protection of the present application.

[0086] The following takes the routing controller as an example to introduce the execution process of the data routing method provided by this application. Figure 4 As shown, the data routing method provided in this embodiment may include the following steps.

[0087] S100: Acquire a source routing node and a destination routing node.

[0088] After the integrated circuit is powered on, the transmission of any data needs to rely on the routing architecture provided by this application. As mentioned above, each bare chip includes multiple functional units. When any functional unit needs to communicate with other functional units, it needs to go through the routing architecture provided by this application. Taking the processor core of any bare chip as an example, when the processor core needs to transmit data with other functional units, a data transmission instruction is sent to the routing controller. The data transmission instruction includes not only the data to be transmitted, but also the routing node corresponding to the processor core, that is, the source routing node information, and the routing node corresponding to the functional unit receiving the data, that is, the destination routing node information. Based on this, the routing controller can determine the source routing node and the destination routing node involved in the data transmission process by parsing the obtained data transmission instruction.

[0089] In practical applications, the routing controller may also obtain the source routing node and the destination routing node through other methods, which will not be described in detail here. This application does not limit the specific process of obtaining the source routing node and the destination routing node.

[0090] S110, determine whether the source routing node and the destination routing node belong to the same bare chip, if so, execute S140, if not, execute S120.

[0091] After determining the source routing node and the destination routing node, it is necessary to further determine whether the two belong to the same die. It is understandable that if the source routing node and the destination routing node belong to the same die, the data routing between the two belongs to intra-die routing. On the contrary, if the source routing node and the destination routing node belong to different dies, the data routing between the two belongs to inter-die routing. These two situations need to be handled differently, which will be expanded in the subsequent content and will not be described in detail here.

[0092] In an optional implementation, a node identifier is added to each routing node in each bare die in the integrated circuit. Importantly, the node identifier of the routing node can indicate the bare die to which the routing node belongs. For example, the node identifier includes two fields, one of which is used to record the number of the corresponding routing node, and the other field is used to record the bare die to which it belongs. Of course, the node identifier can also indicate the bare die to which the routing node belongs in other ways, which will not be described in detail here. Unless it exceeds the core idea of ​​the present application, it also falls within the scope of protection of the present application.

[0093] Based on the above content, the routing controller obtains the node identifier of the source routing node and the node identifier of the destination routing node respectively. If the node identifier of the source routing node and the node identifier of the destination routing node indicate the same bare chip, it is determined that the source routing node and the destination routing node belong to the same bare chip. On the contrary, if the node identifier of the source routing node and the node identifier of the destination routing node indicate different bare chips, it is determined that the source routing node and the destination routing node belong to different bare chips.

[0094] In another optional implementation, a three-dimensional rectangular coordinate system is created based on the physical architecture of the integrated circuit. Similar to the three-dimensional rectangular coordinate system described in the previous embodiment, the Z axis of the three-dimensional rectangular coordinate system created in this embodiment is parallel to the stacking direction of each die in the integrated circuit. After the three-dimensional rectangular coordinate system is created, each routing node in the integrated circuit can be located using the coordinates of the coordinate system. As for the coordinates of the routing nodes in the coordinate system, any base data can be used to represent them, as long as they can fully express the position of each routing node in the coordinate system. Figure 5 In the example shown, the coordinates of the routing nodes are represented by decimal numbers, counting from left to right, with the leftmost side recorded as 0 (i.e., the origin), and 1 is added to the right, for example, source routing node A (2, 0, 3), and another example, destination routing node B (2, 3, 0). Taking source routing node A (2, 0, 3) as an example, the first digit 2 represents the third routing node in the X-axis direction, the second digit 0 represents the first routing node in the Y-axis direction, and the third digit 3 represents the fourth routing node in the Z-axis direction.

[0095] It can be understood that, since each bare chip is stacked in sequence in the Z-axis direction, the Z-axis coordinates corresponding to the routing nodes belonging to the same bare chip must be the same, and accordingly, the Z-axis coordinates corresponding to the routing nodes belonging to different bare chips must be different. Based on this, the coordinate values ​​of the source routing node and the destination routing node in the Z-axis direction are respectively obtained. If the coordinate values ​​of the source routing node and the destination routing node in the Z-axis direction are the same, it can be determined that the source routing node and the destination routing node belong to the same bare chip. On the contrary, if the coordinate values ​​of the source routing node and the destination routing node in the Z-axis direction are different, it is determined that the source routing node and the destination routing node belong to different bare chips. In another optional implementation, the difference between the Z-axis coordinate of the destination routing node and the Z-axis coordinate of the source routing node can also be calculated. If the result is equal to 0, it means that the two are on the same die and intra-die routing is required. If the result is not equal to 0, it means that the two are on different die and inter-die routing is required. Furthermore, if the result is greater than 0, it means that the die to which the destination routing node belongs is above the die to which the source routing node belongs, that is, in a direction away from the origin, and upward routing is required. If the result is less than 0, it means that the die to which the destination routing node belongs is below the die to which the source routing node belongs, that is, in a direction close to the origin, and downward routing is required.

[0096] Of course, other methods can also be used to determine whether the source routing node and the destination routing node belong to the same bare chip, which will not be described in detail here. As long as it does not exceed the core idea of ​​this application, it also falls within the scope of protection of this application.

[0097] S120 , determining a target routing path for inter-die routing.

[0098] As mentioned above, in the integrated circuit provided by the present application, the end routing nodes on the first side of each bare chip are interconnected, and the end routing nodes on the second side are interconnected, so that Figure 5 As shown in the figure as an example, in the X-axis direction, the left side of each bare chip, that is, the side where the routing node C is located, is the first side, and the right side of each bare chip, that is, the side where the routing node D is located, is the second side.

[0099] It should be noted that the target routing path mentioned in this embodiment refers to the routing path from the source routing node to the target bare chip to which the destination routing node belongs. The process of data routing within the target bare chip belongs to intra-chip routing, which will be expanded in subsequent content and will not be described in detail here.

[0100] by Figure 5 Taking the scenario shown in the figure as an example, the die to which the source routing node A belongs is die3, and the target die to which the destination routing node B belongs is die0. The source routing node A can be connected to the target die0 through the end routing node on the first side, or through the end routing node on the second side. Based on this, it can be connected according to Figure 6 The process shown determines the target routing path.

[0101] S1201: Determine a first routing path with the shortest path when inter-die routing is performed through an end routing node on a first side.

[0102] In practical applications, there are multiple routing paths connecting the target bare chip die0 through the end routing node of the first side. In order to save routing time and improve data transmission efficiency, it is necessary to select the shortest routing path as the first routing path.

[0103] It is understandable that the dies are stacked and the distances of the possible routing paths in the Z-axis direction are consistent. Therefore, it is only necessary to determine the shortest routing path from the source routing node and the destination routing node to the TSV on the first side when routing through the end routing node on the first side. Figure 5As shown, the coordinates of the TSV on the first side are (0, *), so the shortest routing path from the source routing node A to the first side is the distance from the source routing node A to the routing node C, that is, |Y_tsv1|=|0-2|=2, and correspondingly, the shortest routing path from the destination routing node B (2, 3, 0) to the first side is the distance from the destination routing node B to the routing node E, that is, |M_tsv1|=|0-2|=2, and the shortest first routing path in the case of inter-die routing through the end routing node of the first side is |Y_tsv1|+|M_tsv1|. Of course, the length of the TSV used for inter-die connection is also included, and since the first side and the second side are consistent, this value is not calculated here.

[0104] S1202: Determine a second routing path with the shortest path when inter-die routing is performed through an end routing node on the second side.

[0105] Continue to use Figure 5 In the example shown, the coordinates of the TSV on the second side are (3, *), based on which the shortest routing path from the source routing node A to the second side is the distance from the source routing node A to the routing node D, i.e. |Y_tsv2|=|3-2|=1. Correspondingly, the shortest routing path from the destination routing node B (2, 3, 0) to the second side is the distance from the destination routing node F to the routing node F, i.e. |M_tsv2|=|3-2|=1. The second routing path with the shortest path in the case of inter-die routing through the end routing node on the second side is

[0106] |Y_tsv2|+|M_tsv2|.

[0107] S1203 . Determine the first routing path or the second routing path as a target routing path for inter-die routing.

[0108] It can be understood that whether it is the first routing path or the second routing path, especially when the routing path includes TSV, it is possible to cause a circuit break due to an abnormality. Therefore, before selecting the target routing path, it is necessary to determine whether the TSV included in the first routing path and the TSV included in the second routing path are faulty. If the TSV of the first routing path or the TSV of the second routing path is faulty, the routing path with normal TSV in the first routing path and the second routing path will be used as the target routing path. Correspondingly, if the TSV of the first routing path and the TSV of the second routing path are both normal, the routing path with the shortest path in the first routing path and the second routing path will be used as the target routing path.

[0109] In an optional implementation, the state of any TSV in the integrated circuit can be detected by a dedicated TSV test circuit, and whether the corresponding TSV is faulty can be determined based on the obtained detection results. Of course, whether the TSV is faulty can also be determined by other methods, which can be specifically implemented with reference to related technologies, and this application does not make specific limitations on this.

[0110] S130 , transmitting the data to the target bare chip to which the destination routing node belongs according to the target routing path.

[0111] After the target routing path is determined, the data can be transmitted to the target die to which the destination routing node belongs according to the target routing path. Figure 5 As shown, for a determined target routing path, it must be connected to a certain end routing node in the target bare chip. Based on this, the end routing node connected to the TSV included in the target routing path in the target bare chip is defined as the target end routing node, and data is transmitted to the target end routing node according to the target routing path, that is, it is considered to be transmitted to the target bare chip.

[0112] S140: Transmit the data to the destination routing node according to the preset on-chip routing strategy.

[0113] Combination Figure 4 As shown, the execution of S140 includes two possible situations, one is the situation where it is determined in S110 that the source routing node and the destination routing node belong to the same bare chip, and the other is the situation where the data is transmitted to the target bare chip after S130. In both cases, the process of transmitting data to the destination routing node belongs to data transmission within the target bare chip, and the data can be transmitted to the destination routing node according to the preset on-chip routing strategy. Specifically, the data can be transmitted to the destination routing node according to the preset static routing strategy or the preset dynamic routing strategy. As for the specific implementation process of the preset static routing strategy and the preset dynamic routing strategy, it can be realized with reference to the relevant technology, and this application does not make specific limitations on this.

[0114] In summary, the present application also provides a data routing method, which is based on the integrated circuit provided by the present application, especially the routing architecture in the integrated circuit, to realize data routing between any source routing node and destination routing node inside the integrated circuit, and can realize data transmission within the same bare chip and between different bare chips, so that the bare chips inside the 3D chip can be efficiently interconnected and communicated to meet the actual application needs.

[0115] Furthermore, when the integrated circuit realizes the interconnection between different bare chips, only the end routing nodes of the first side and the second side are interconnected, and the routing nodes inside the bare chip are not interconnected with the routing nodes of other bare chips. Such a setting can reduce the impact of signal crosstalk caused by the interconnection of bare chips, and can effectively improve the reliability of data transmission.

[0116] The present application also provides a system on chip, comprising an integrated circuit provided by any of the above embodiments of the present application.

[0117] In an optional implementation, the system on chip provided by the present application further includes: a routing controller, and the routing controller is configured to execute the data routing method provided in any of the above embodiments.

[0118] The present application also provides an electronic device, comprising the system on chip provided in the aforementioned embodiment of the present application.

[0119] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more instructions for implementing the above steps are stored, and when the one or more instructions are executed by one or more processors, the processors execute the data routing method described above. For the relevant specific implementation, please refer to the above description, which will not be repeated here.

[0120] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes the steps in the data routing method according to various embodiments of the present application described in the above content of this specification.

[0121] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0122] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0123] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0124] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0125] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0126] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0127] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. An integrated circuit, characterized in that: include: A plurality of bare chips, each of which comprises a plurality of routing nodes, wherein: The dies are stacked in a vertical direction; The routing nodes within the same die are interconnected; The end routing nodes on the first side of each of the bare chips are connected to each other, and the end routing node is a routing node located at the end of any routing path in the bare chip to which it belongs; The end routing nodes on the second side of each of the bare chips are connected to each other, and the second side is opposite to the first side.

2. The integrated circuit according to claim 1, characterized in that The end routing nodes on the first side of each of the bare chips are interconnected in a grid structure; The end routing nodes on the second side of each of the bare chips are interconnected in a grid structure.

3. The integrated circuit according to claim 2, characterized in that In any two adjacent dies, two end routing nodes on the first side or the second side are connected through a through silicon via TSV.

4. The integrated circuit according to claim 1, characterized in that The routing nodes within the same die are connected in a grid structure.

5. The integrated circuit according to claim 4, characterized in that Routing nodes within the same die are interconnected via metal lines.

6. The integrated circuit according to claim 1, characterized in that The plurality of dies include a first die located at a top layer, a second die located at a bottom layer, and at least one third die located between the first die and the second die.

7. The integrated circuit according to claim 6, characterized in that The end routing nodes of the first die and the second die include one routing port for connecting to other dies, and the end routing node of the third die includes two routing ports for connecting to other dies.

8. A data routing method, characterized in that: Applied to the integrated circuit according to any one of claims 1 to 7, the method comprising: Get the source routing node and the destination routing node; Determining whether the source routing node and the destination routing node belong to the same die; If the source routing node and the destination routing node belong to different dies, determining a target routing path for inter-die routing; Transmitting data to a target die to which the destination routing node belongs according to the target routing path; The data is transmitted to the destination routing node according to the preset on-chip routing strategy.

9. The data routing method according to claim 8, characterized in that: The end routing nodes on the first side of each bare die of the integrated circuit are interconnected, and the end routing nodes on the second side are interconnected, the second side being opposite to the first side; The determining of a target routing path for inter-die routing includes: Determine a first routing path with the shortest path when inter-die routing is performed through the end routing node of the first side; Determine a second routing path with the shortest path when inter-die routing is performed through the end routing node of the second side; The first routing path or the second routing path is determined as a target routing path for inter-die routing.

10. The data routing method according to claim 9, characterized in that: The end routing nodes of any two adjacent bare chips in the integrated circuit are connected to each other through silicon vias TSV; Determining the first routing path or the second routing path as a target routing path for inter-die routing includes: respectively determining whether the TSV included in the first routing path and the TSV included in the second routing path are faulty; If the TSV of the first routing path or the TSV of the second routing path fails, determine a routing path with a normal TSV among the first routing path and the second routing path as a target routing path; If the TSV of the first routing path and the TSV of the second routing path are both normal, a routing path with the shortest path between the first routing path and the second routing path is determined as a target routing path.

11. The data routing method according to claim 10, characterized in that: Transmitting data to a target bare chip to which the destination routing node belongs according to the target routing path, including: The data is transmitted to a target end routing node of a target die to which the destination routing node belongs according to the target routing path, wherein the target end routing node is an end routing node to which the TSV of the target routing path is connected in the target die.

12. The data routing method according to claim 8, characterized in that: Determining whether the source routing node and the destination routing node belong to the same die includes: Respectively obtaining a node identifier of the source routing node and a node identifier of the destination routing node; If the node identifier of the source routing node and the node identifier of the destination routing node indicate the same die, determining that the source routing node and the destination routing node belong to the same die; If the node identifier of the source routing node and the node identifier of the destination routing node indicate different dies, it is determined that the source routing node and the destination routing node belong to different dies.

13. The data routing method according to claim 8, characterized in that: Determining whether the source routing node and the destination routing node belong to the same die includes: Creating a three-dimensional rectangular coordinate system, wherein a Z axis of the three-dimensional rectangular coordinate system is parallel to a stacking direction of each die in the integrated circuit; Respectively obtain the coordinate values ​​of the source routing node and the destination routing node in the Z-axis direction; If the coordinate values ​​of the source routing node and the destination routing node in the Z-axis direction are the same, it is determined that the source routing node and the destination routing node belong to the same die; If the coordinate values ​​of the source routing node and the destination routing node in the Z-axis direction are different, it is determined that the source routing node and the destination routing node belong to different dies.

14. The data routing method according to claim 8, characterized in that: Also includes: If the source routing node and the destination routing node belong to the same bare chip, the data is transmitted to the destination routing node according to a preset on-chip routing strategy.

15. The data routing method according to claim 8 or 14, characterized in that: The transmitting the data to the destination routing node according to the preset on-chip routing strategy includes: The data is transmitted to the destination routing node according to a preset static routing strategy or a preset dynamic routing strategy.

16. A system on chip, characterized in that: Comprising an integrated circuit as claimed in any one of claims 1 to 7.

17. The system on chip according to claim 16, characterized in that: Also includes: A routing controller, wherein the routing controller is configured to execute the data routing method according to any one of claims 8 to 15.

18. An electronic device, characterized in that: Comprising a system on chip as claimed in claim 16 or 17.

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